CN102779813A - 半导体装置及其制造方法以及采用它的半导体模块 - Google Patents

半导体装置及其制造方法以及采用它的半导体模块 Download PDF

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Publication number
CN102779813A
CN102779813A CN201210031263XA CN201210031263A CN102779813A CN 102779813 A CN102779813 A CN 102779813A CN 201210031263X A CN201210031263X A CN 201210031263XA CN 201210031263 A CN201210031263 A CN 201210031263A CN 102779813 A CN102779813 A CN 102779813A
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mentioned
semiconductor
projected electrode
semiconductor device
circuit board
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渡部武志
井本孝志
武部直人
黑勇旗
堂前佑辅
涩谷克则
小玉义宗
唐金祐次
川户雅敏
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明提供半导体装置及其制造方法以及采用它的半导体模块。根据一个实施方式提供的半导体装置，具备：布线基板；在布线基板的第1面搭载的半导体芯片；在布线基板的第1面设置的第1突起电极；在布线基板的第2面设置的第2突起电极；和将半导体芯片与第1突起电极一起密封的密封树脂层。密封树脂层具有使第1突起电极的一部分露出的凹部。半导体装置多个层叠，构成POP构造的半导体模块。该场合，下级侧装置的第1突起电极与上级侧装置的第2突起电极电气连接。

Description

半导体装置及其制造方法以及采用它的半导体模块
相关申请
本申请以日本专利申请2011-106875(申请日2011年5月12日)作为基础申请，享有优先权。本申请通过参照该基础申请，包含基础申请的全部的内容。
技术领域
这里公开的实施方式一般地说，涉及半导体装置及其制造方法以及采用它的半导体模块。
背景技术
为了实现半导体装置的小型化、高密度安装化，在一个封装内层叠多个半导体芯片并树脂密封的堆栈型多芯片封装实用化。为了实现多芯片封装的进一步高集成化、高功能化，推进了具有将在布线基板上安装多个半导体芯片并树脂密封的半导体封装立体层叠的构造，即POP(Package onPackage，层叠封装)构造的半导体模块的实用化。
具有POP构造的半导体模块中，多个半导体封装间的连接使用在布线基板上设置的包括焊料球的突起电极(凸起电极)和/或在密封树脂层内设置的贯通电极。突起电极比贯通电极容易形成，因此有利于POP构造的半导体模块的制造成本的降低。多个半导体封装间用突起电极连接的场合，突起电极配置在密封半导体芯片的密封树脂层的周围，其高度必须设定成下级侧的半导体封装的密封树脂层的高度以上。因而，突起电极(焊料球)的直径和/或形成间距存在变大的倾向。这成为妨碍半导体模块的小型化、输入输出数的增大、半导体封装中的半导体芯片的层叠数的增加的主要因素。
发明内容
本发明的实施方式提供不妨碍半导体模块的小型化、输入输出数的增大、半导体芯片的层叠数的增加等，可以在POP构造中的上下的装置间低成本连接的半导体装置及其制造方法以及采用该半导体装置的半导体模块。
根据一个实施方式，提供一种半导体装置，具备：布线基板，其具有具备芯片搭载区域和第1布线层的第1面以及具备与第1布线层电气连接的第2布线层的第2面；半导体芯片，其搭载于布线基板的第1面，具有电极衬垫(pad)；连接部件，其将第1布线层和电极衬垫电气连接；第1突起电极，其设置在布线基板的第1面，与第1布线层电气连接；第2突起电极，其设置在布线基板的第2面，与第2布线层电气连接；和密封树脂层，其以将半导体芯片与连接部件及第1突起电极一起密封的方式，设置在布线基板的第1面上，且具有使第1突起电极的一部分露出的凹部。
根据本发明的实施方式，可提供不妨碍半导体模块的小型化、输入输出数的增大、半导体芯片的层叠数的增加等，可以在POP构造中的上下的装置间进行低成本连接的半导体装置及其制造方法以及采用该半导体装置的半导体模块。
附图说明
图1是第1实施方式的半导体装置的截面图。
图2是第2实施方式的半导体装置的截面图。
图3A至图3G是实施方式的半导体装置的制造工序(步骤)的截面图。
图4表示图3A至图3G所示半导体装置的制造工序中的密封树脂层的形成工序的第1例。
图5表示图3A至图3G所示半导体装置的制造工序中的密封树脂层的形成工序的第2例。
图6表示图3A至图3G所示半导体装置的制造工序中的密封树脂层的形成工序的第3例。
图7是第1实施方式的半导体模块的截面图。
图8是第1实施方式的半导体模块的变形例的截面图。
图9是第1实施方式的半导体模块的其他变形例的截面图。
图10是第2实施方式的半导体模块的截面图。
图11是第3实施方式的半导体模块的截面图。
具体实施方式
参照附图说明实施方式的半导体装置及其制造方法以及采用它的半导体模块。图1是第1实施方式的半导体装置的截面图。图2是第2实施方式的半导体装置的截面图。这些图所示半导体装置1具备布线基板2。布线基板2具有成为芯片搭载面的第1面(上面)2a和成为外部连接面的第2面(下面)2b。布线基板2的第1面2a具有在中央附近设置的芯片搭载区域。
在布线基板2的第1面2a设置了第1布线层3。在布线基板2的第2面2b设置了第2布线层4。根据需要，也可以在布线基板2的内部设置布线层。第1布线层3和第2布线层4经由布线基板2内设置的通孔5电气连接。第1布线层3具有在芯片搭载区域的周围配置的第1连接衬垫3a和在第1连接衬垫3a的外周侧配置的第2连接衬垫3b。第2布线层4具有与第2连接衬垫3b对应配置的第3连接衬垫4a。第1连接衬垫3a起到与布线基板2上搭载的半导体芯片的连接部的功能。第2及第3连接衬垫3b、4a起到后述突起电极的形成部的功能，在除了芯片搭载区域及与其对应的区域外的外周区域设置。
在布线基板2的芯片搭载区域搭载了半导体芯片6。对布线基板2的半导体芯片6的搭载数没有特别限定，也可以是1个或2个以上。图1及图2表示在布线基板2的芯片搭载区域层叠搭载多个半导体芯片6、6...的半导体装置1。半导体芯片6的具体例有NAND型闪速存储器等的半导体存储器芯片，但是不限于此。多个半导体芯片6、6...分别具有沿一个外形边排列的电极衬垫6a。
多个半导体芯片6以使电极衬垫6a露出的方式阶梯状层叠。图1及图2所示半导体装置1中，多个半导体芯片6分为第1芯片群7和第2芯片群8。第1及第2芯片群7、8分别由4个半导体芯片6构成。构成第1芯片群7的4个半导体芯片6在布线基板2的芯片搭载区域上顺序阶梯状层叠。构成第2芯片群8的4个半导体芯片6在第1芯片群7上顺序阶梯状层叠。第2芯片群8的阶梯方向与第1芯片群8的阶梯方向成为逆向。第1芯片群7和第2芯片群8的衬垫排列边的方向成为逆向。
半导体芯片6的层叠形状不限于上述阶梯形状，也可以采用使多个半导体芯片6仅仅在一个方向阶梯状层叠，或者以衬垫排列边交替成为逆向的方式使多个半导体芯片6层叠等的层叠形状。多个半导体芯片6也可以使外形边对齐层叠。该场合，作为后述连接部件的金属线埋入在多个半导体芯片6间粘接的粘接剂层内。也可以利用半导体芯片6内设置的贯通电极，在半导体芯片6间用微细焊料凸起连接并层叠。半导体芯片6的层叠形状、层叠数没有特别限定。
构成第1芯片群7的多个半导体芯片6的电极衬垫6a经由位于其附近的第1连接衬垫3a和金属线(Au线等)9电气连接。同样，构成第2芯片群8的多个半导体芯片6的电极衬垫6a经由位于其附近的第1连接衬垫3a和金属线9电气连接。构成第1及第2芯片群7、8的半导体芯片6中，电气特性和/或信号特性相同的电极衬垫6a可以用金属线9顺序连接。将半导体芯片6的电极衬垫6a和第1连接衬垫3a电气连接的连接部件不限于金属线9，可以是由喷墨印刷等形成的布线层(导体层)，根据情况，也可以是上述微细的焊料凸起。
在第1布线层3的第2连接衬垫3b上，形成第1突起电极10，作为第1外部连接端子。在第2布线层4的第3连接衬垫4a上，形成第2突起电极11，作为第2外部连接端子。第1及第2突起电极10、11可以采用例如焊料球。通过在第2及第3连接衬垫上分别载置焊料球并回流，形成包括焊料球(焊料凸起)的第1及第2突起电极10、11。突起电极10、11不限于焊料球，也可以采用金属镀层膜的层叠体等。但是，因为可以低成本制作具有某程度的高度的突起电极10、11，因此，最好采用包括焊料球的突起电极10、11。
在布线基板2的第1面2a上，形成将半导体芯片6与金属线9和/或第1突起电极10一起密封的树脂密封层12。半导体芯片6和/或金属线9虽然由树脂密封层12完全密封，但是第1突起电极10为了起到外部连接端子的功能，其一部分从树脂密封层12露出。树脂密封层12具有使第1突起电极10的一部分露出的凹部13。换言之，第1突起电极10的大部分在树脂密封层12内埋设，但是其一部分在从树脂密封层12的表面向第1突起电极10形成的凹部13内露出。
如后详述，凹部13通过切削或溶融与树脂密封层12的第1突起电极10相当的部分，或通过在树脂密封用的模具内设置与凹部13对应的凸部而形成。切削或溶融树脂密封层12的一部分而形成凹部13的场合，通过与树脂密封层12一起切削或溶融第1突起电极10的一部分，使第1突起电极10的一部分在树脂密封层12的凹部13内露出。采用具有凸部的模具的场合，通过将凸部的高度调节到与第1突起电极10接触而形成露出面的高度，在由模具的凸部形成的凹部13内，使第1突起电极10的一部分露出。
图1所示半导体装置1的凹部13具有在树脂密封层12的端面侧的侧面开口的形状。即，图1所示凹部13以除去到树脂密封层12的端面为止的方式形成，从而使一方的侧面开口。凹部13的形状不限于图1所示的形状。图2所示半导体装置1的凹部13具有以全部侧面作为壁面的沟状的形状。凹部13不阻碍半导体芯片6和/或金属线9的树脂密封状态，从树脂密封层12的表面向深度方向，形成到使第1突起电极10的一部分露出的位置为止即可。
如后详述，第1及第2突起电极10、11的高度设定成在多个半导体装置1层叠时，可电气连接上下的半导体装置1间的高度。层叠多个半导体装置1，构成POP构造的半导体模块的场合，通过连接下级侧的半导体装置1的第1突起电极10和上级侧的半导体装置1的第2突起电极11，上下的半导体装置1间被电气连接。从而，第1突起电极10和第2突起电极11的合计高度(连接高度)设定成半导体装置1的树脂密封层12的厚度(除凹部13的部分的高度)以上。例如，第1及第2突起电极10、11的高度，分别设定成树脂密封层12的厚度的约1/2。第1及第2突起电极10、11的高度不一定相同。
通过使用上述第1突起电极10和第2突起电极11电气连接POP构造中的上下的半导体装置1间，可以减小突起电极10、11的高度、基于它们的宽度(例如为焊料球的场合是直径)、和/或形成间距。与上下的半导体装置间仅仅由在上级侧的半导体装置设置的突起电极连接的场合比，可以使各突起电极10、11的大小为约1/2，而且形成间距也可以减小。从而，不妨碍半导体模块的小型化，可以实现输入输出数的增大和/或半导体芯片的层叠数的增加。
构成POP构造的半导体模块时，下级侧的半导体装置1的凹部13的宽度设定成可在其中配置上级侧的半导体装置1的第2突起电极11。例如，第1突起电极10和第2突起电极11的大小近似同一的场合，凹部13的宽度最好设为突起电极10、11的大小(例如为焊料球的场合是直径)的1.2倍以上。从而，可以将下级侧的半导体装置1的第1突起电极10和上级侧的半导体装置1的第2突起电极11进行稳定的电气连接。凹部13的宽度的上限没有特别限定。但是，凹部13的宽度过大会导致半导体装置1的形状大型化，因此，凹部13的宽度最好设为突起电极10、11的大小3倍以下。
上述实施方式的半导体装置1例如制作如下。半导体装置1的制造工序参照图3A至图3G、图4、图5及图6进行说明。如图3A所示，准备具有设置了第1布线层3的第1面2a和设置了第2布线层4的第2面2b的布线基板2。布线基板2具有多个与半导体装置1对应的装置形成区域X。以下的各工序对多个装置形成区域X实施。在布线基板2的第1面2a设置的第1布线层3的第2连接衬垫上，形成第1突起电极10。第1突起电极10采用焊料球的场合，在第2连接衬垫上载置焊料球后回流。
接着，如图3B及图3C所示，在设置于布线基板2的第1面2a的芯片搭载区域搭载半导体芯片6。半导体芯片6的搭载工序根据半导体芯片6的层叠数和/或层叠形状适宜实施。图3B表示与第1芯片群7相当的多个半导体芯片6阶梯状层叠后，将这些半导体芯片6的电极衬垫和第1布线层3的第1连接衬垫用Au线等的金属线9电气连接后的状态。图3C表示在第1芯片群7上将与第2芯片群8相当的多个半导体芯片6以与第1芯片群7的逆向阶梯状层叠后，将这些半导体芯片6的电极衬垫和第1布线层3的第1连接衬垫用Au线等的金属线9电气连接后的状态。
然后，如图3D所示，在布线基板2的第1面2a上，例如通过模具成型形成将半导体芯片6与金属线9和/或第1突起电极10一起密封的密封树脂层12。图3D表示半导体芯片6用密封树脂层12覆盖后，形成凹部13的场合。该场合，密封树脂层12以可以覆盖半导体芯片6的厚度一样且平坦地形成。密封树脂层12以包含装置形成区域X间的切断区域的方式一体地形成。在密封树脂层12形成的同时形成凹部13的场合，密封树脂层12的形状在刚刚模具成型后成为图3E所示的形状。
接着，如图3E所示，在密封树脂层12形成使第1突起电极10的一部分露出的凹部13。凹部13的形成工序如图4所示，通过刀片14对与密封树脂层12的第1突起电极10的形成位置(形成区域)对应的部分从密封树脂层12的表面侧进行切削加工而实施。此时，通过将凹部13的深度设定成使第1突起电极10的一部分被削去的方式，在凹部13内露出第1突起电极10的一部分。由密封树脂层12的切削加工形成凹部13的形成工序也可以取代刀片加工而采用铣床(rooter)加工等实施。
凹部13的形成工序如图5所示，也可以将与密封树脂层12的第1突起电极10的形成位置(形成区域)对应的部分用例如激光15溶融加工而实施。此时，通过使密封树脂层12溶融除去到使第1突起电极10的一部分露出的深度为止，形成使第1突起电极10的一部分露出的凹部13。即，可以使第1突起电极10的一部分在凹部13内露出。密封树脂层12的溶融加工也可以采用激光15以外的局部加热。
在密封树脂层12的切削加工和/或溶融加工实施时，也可以一次切削或者溶融相邻的装置形成区域X的密封树脂层12的加工区域。该场合，在分割为装置形成区域X后，形成图1所示的凹部13。通过仅仅切削或者溶融一处的装置形成区域X的加工区域，在分割为装置形成区域X后，形成图2所示的凹部13。凹部13的形状可以是图1及图2之一。但是，为了降低凹部13的形成成本，最好一次切削或者溶融相邻的装置形成区域X的密封树脂层12的加工区域。
如图6所示，凹部13的形成工序也可以通过采用与凹部13对应的凸部16的模具17来形成密封树脂层12而实施。该场合，在密封树脂层12形成的同时形成凹部13。即，在密封树脂的模具成型中采用的上模(模具17)，预先形成与凹部13对应的凸部16。通过采用这样的上模(模具17)使密封树脂层12模具成型，可以获得具有凹部13的密封树脂层12。通过以与第1突起电极10接触规定面积的方式调节凸部16的高度，在由凸部16形成的凹部13内使第1突起电极10的一部分露出。
然后，如图3F所示，在设置于布线基板2的第2面2b的第2布线层4的第4连接衬垫上，形成第2突起电极11。第2突起电极11与第1突起电极10同样形成。如图3G所示，通过由刀片等沿装置形成区域32切断布线基板2，制作单片化的半导体装置1。图3A至图3G表示图1所示的半导体装置1的制造工序。
图2所示的半导体装置1除了凹部13的形状不同以外，与图1所示的半导体装置1同样地制作。凹部13的形状可以通过形成凹部13的刀片14的形状、激光15的加工形状、模具17的凸部16的形状等来调节。
接着，参照图7至图11说明采用上述实施方式的半导体装置1的半导体模块。如这些图所示，实施方式的半导体模块具备多个上述实施方式的半导体装置1。半导体模块具有将多个半导体装置1层叠构成的POP构造。图7表示第1实施方式的半导体模块20。半导体模块20具备第1至第4半导体封装1A～4D。4个半导体封装1A～4D都采用实施方式的半导体装置1。半导体装置1的层叠数不限于4个，也可以是其以下或以上。
在第1半导体封装1A上层叠了第2半导体封装1B。第2半导体封装1B的第2突起电极11在第1半导体封装1A的凹部13内配置，其上与第1半导体封装1A的第1突起电极10电气连接。第2半导体封装1B的第2突起电极11与在第1半导体封装1A的第1突起电极10的凹部13内露出的部分即从第1突起电极10的密封树脂层12露出的部分电气连接。第1及第2突起电极10、11由焊料球构成的场合，通过回流工序等将焊料球彼此电气及机械地连接。
第2半导体封装1B上，层叠第3半导体封装1C。第3半导体封装1C上，层叠第4半导体封装1D。第2半导体封装1B和第3半导体封装1C之间，及第3半导体封装1C和第4半导体封装1D之间，同样进行电气及机械地连接。即，上级侧的半导体封装(1C，1D)的第2突起电极11在下级侧的半导体封装(1B，1C)的凹部13内配置，且与第1突起电极10的露出部分电气连接。
如上所述，使用上级侧的半导体封装(1B，1C，1D)的第2突起电极1和下级侧的半导体封装(1A，1B，1C)的第1突起电极10，将POP构造中的上下的半导体装置1间电气连接。从而，可以减小突起电极10、11的高度、基于它们的宽度(例如为焊料球的场合是直径)、和/或形成间距。与上下的半导体封装间仅仅由设置于上级侧的半导体装置的突起电极连接的场合比，可以使突起电极10、11的大小减小为约1/2，而且形成间距也减少。
通过减小连接上下的半导体装置1间的突起电极10、11的大小和/或形成间距，可以增大突起电极10、11的设置数。在半导体模块20的形状相同的场合，可以实现多针化(输入输出数的增大)。在实现相同输入输出数时，可以使半导体模块20小型化。而且，一个半导体装置1中的半导体芯片6的层叠数增加的场合，换言之根据半导体芯片6的层叠数，密封树脂层12的高度变高的场合中，也可以抑制突起电极10、11的大小和/或形成间距的增大。从而，不会妨碍半导体模块20的小型化、多针化，可以实现半导体芯片6的层叠数的增加。
该实施方式中的POP构造的半导体模块20由同一构造的半导体装置1层叠构成，因此，可以容易使半导体装置1多级化。从而，可以容易增大半导体模块20中的半导体芯片6的层叠数(例如半导体芯片6为存储器芯片时与存储容量对应)。通过使用同一构造的半导体装置1，各构成材料(布线基板1等)、成型部件(模具等)为一种即可，因此可以降低半导体模块20的制造成本。而且，由于可以匹配半导体装置1间的翘曲方向，因此可以提高半导体模块20的制造性和可靠性。
成为下级侧的半导体装置1的连接端子的第1突起电极10，除露出部分外埋设在密封树脂层12内，因此，与露出的突起电极彼此连接的场合比，可以提高第1突起电极10和成为上级侧的半导体装置1的连接端子的第2突起电极11的连接性和/或连接后的强度。而且，成为上级侧的半导体装置1的连接端子的第2突起电极11在下级侧的半导体装置1的凹部13内配置，因此，容易提高对第1突起电极10的位置精度。从而，可以提高上下的半导体装置1间的连接精度。
构成半导体模块20的半导体装置1的构成可以有各种变形。第1及第2突起电极10、11不限于在半导体芯片6的周围设置1列，也可以在半导体芯片6的周围设置2列以上。图8表示具有分别形成2列的第1及第2突起电极10A、10B、11A、11B的半导体装置1A～1D层叠而成的半导体模块20。在位于最上级的半导体封装1D上不层叠半导体封装，因此可以如图9所示省略第1突起电极10和凹部13。也可以仅仅省略凹部13。
图10表示第2实施方式的半导体模块30。图10所示半导体模块30具备第1半导体封装1A和其上层叠的第2半导体封装1B。第1及第2半导体封装1A、1B具有与第1实施方式的半导体模块20同样的构成，且半导体封装1A、1B间与第1实施方式的半导体模块20同样地连接。半导体装置1的层叠数只要是2个以上，没有特别限定，也可以与第1实施方式同样为4个或者以上。
第2实施方式的半导体模块30在最下级配置了具有采用焊料凸起作为外部连接端子的突起电极31的布线基板32。第1半导体封装1A和最下级用布线基板32通过将第1半导体封装1A的第2突起电极11与布线基板32的上面侧的布线层33接合而电气连接。布线基板32的突起电极31以与半导体模块1中的第2突起电极11不同的图形排列。
半导体模块30的第2突起电极11仅仅在布线基板2的外周区域配置，因此其排列形状受制约。对于该点，通过使用最下级用布线基板32，可以提高作为外部连接端子的突起电极31的排列形状的自由度。例如，通过使突起电极31的排列形状与既有布线图形对应，可以提高半导体模块30的通用性。
图11表示第3实施方式的半导体模块。图11所示半导体模块与第2实施方式的半导体模块30同样，具备第1半导体封装1A和第2半导体封装1B。半导体封装1A、1B的构成、层叠数、连接形态等与第2实施方式同样。第3实施方式的半导体模块在最下级配置专用的半导体封装41。最下级专用的半导体封装41与第2实施方式中的布线基板32同样，具备具有以与半导体装置1中的第2突起电极11不同的图形排列的突起电极42作为外部连接端子的布线基板43。
通过采用最下级专用的半导体封装41，也可以提高半导体模块的通用性。采用最下级专用的半导体封装41的场合，可以在半导体封装41内配置不同于半导体芯片6的半导体芯片44，例如在半导体芯片6为存储芯片的场合，可以配置控制芯片44。而且，在最下级专用的半导体封装41也可以配置受动部件等的芯片部件45。通过采用这样的最下级专用的半导体封装41，可以实现半导体模块的高功能化。最下级专用的半导体封装41与第1及第2半导体封装1A、1B同样，具备使第1突起电极10、密封树脂层12、第1突起电极10露出的凹部13等。
虽然说明本发明的几个实施方式，但是这些实施方式只是作为例示而不是限定发明的范围。这些新实施方式可以其他方式实施，在不脱离发明的要旨的范围，可以进行各种省略、置换、变更。这些实施方式及其变形也是发明的范围、要旨所包含的，同时也是权利要求范围所述的发明及其均等的范围所包含的。

Claims (20)

1.一种半导体装置，其特征在于，具备：
布线基板，其具有具备芯片搭载区域和第1布线层的第1面以及具备与上述第1布线层电气连接的第2布线层的第2面；
半导体芯片，其搭载于上述布线基板的上述第1面，具有电极衬垫；
连接部件，其将上述第1布线层和上述电极衬垫电气连接；
第1突起电极，其设置在上述布线基板的上述第1面，与上述第1布线层电气连接；
第2突起电极，其设置在上述布线基板的上述第2面，与上述第2布线层电气连接；和
密封树脂层，其以将上述半导体芯片与上述连接部件及上述第1突起电极一起密封的方式，设置在上述布线基板的上述第1面上，且具有使上述第1突起电极的一部分露出的凹部。
2.如权利要求1所述的半导体装置，其特征在于，
上述第1及第2突起电极具备焊料球。
3.如权利要求1所述的半导体装置，其特征在于，
上述凹部具有使上述密封树脂层的端面侧的侧面开口的形状。
4.如权利要求1所述的半导体装置，其特征在于，
上述第1突起电极和上述第2突起电极的合计高度在上述密封树脂层的厚度以上。
5.如权利要求1所述的半导体装置，其特征在于，
上述第1及第2突起电极具有上述树脂密封层的厚度的近似1/2的高度。
6.如权利要求1所述的半导体装置，其特征在于，
上述凹部具有上述第1及第2突起电极的大小的1.2倍以上且3倍以下的范围的宽度。
7.如权利要求1所述的半导体装置，其特征在于，
在上述布线基板的上述第1面层叠有多个上述半导体芯片。
8.如权利要求7所述的半导体装置，其特征在于，
上述多个半导体芯片中的最下级的上述半导体芯片的上述电极衬垫和上述第1布线层之间，以及上述多个半导体芯片的上述电极衬垫之间，由作为上述连接部件的金属线顺序连接。
9.一种半导体装置的制造方法，其特征在于，包括：
在设置于布线基板的第1面的芯片搭载区域搭载具有电极衬垫的半导体芯片的步骤；
将设置于上述布线基板的上述第1面的第1布线层和上述电极衬垫经由连接部件电气连接的步骤；
在上述布线基板的上述第1面上，形成与上述第1布线层电气连接的第1突起电极的步骤；
在上述布线基板的上述第1面上，形成将上述半导体芯片与上述连接部件及上述第1突起电极一起密封并具有使上述第1突起电极的一部分露出的凹部的密封树脂层的步骤；和
在具备与上述第1布线层电气连接的第2布线层的上述布线基板的第2面上，形成与上述第2布线层电气连接的第2突起电极的步骤。
10.如权利要求9所述的半导体装置的制造方法，其特征在于，
上述密封树脂层的形成步骤具备：在上述布线基板的上述第1面上平坦形成密封上述半导体芯片、上述连接部件及上述第1突起电极的树脂层的步骤；和以上述第1突起电极的一部分被削去的方式切削与上述树脂层的上述第1突起电极的形成位置对应的部分，形成上述凹部的步骤。
11.如权利要求9所述的半导体装置的制造方法，其特征在于，
上述密封树脂层的形成步骤具备：在上述布线基板的第1面上平坦形成密封上述半导体芯片、上述连接部件及上述第1突起电极的树脂层的步骤；和以上述第1突起电极的一部分露出的方式使与上述树脂层的上述第1突起电极的形成位置对应的部分溶融，形成上述凹部的步骤。
12.如权利要求9所述的半导体装置的制造方法，其特征在于，
上述密封树脂层的形成步骤具备：采用具有与上述凹部对应的凸部的模具，成型具有上述凹部的密封树脂层的步骤。
13.如权利要求9所述的半导体装置的制造方法，其特征在于，
上述第1及第2突起电极具备焊料球。
14.如权利要求9所述的半导体装置的制造方法，其特征在于，
在上述布线基板的第1面层叠多个上述半导体芯片。
15.一种半导体模块，其特征在于，具备：
具有如权利要求1所述的半导体装置的第1半导体封装；和
具有如权利要求1所述的半导体装置并在上述第1半导体封装上层叠的第2半导体封装，
上述第2半导体封装中的上述第2突起电极在上述第1半导体封装中的上述凹部内配置，且与上述第1突起电极的从上述密封树脂层露出的部分电气连接。
16.如权利要求15所述的半导体模块，其特征在于，
上述第1及第2突起电极具备焊料球。
17.如权利要求15所述的半导体装置，其特征在于，
上述第1半导体封装中的上述第1突起电极和上述第2半导体封装中的上述第2突起电极的连接高度，在上述第1半导体封装中的前记密封树脂层的厚度以上。
18.如权利要求15所述的半导体模块，其特征在于，
上述第1半导体封装和上述第2半导体封装具备同一构造的上述半导体装置。
19.如权利要求15所述的半导体模块，其特征在于，
还具备在上述第1半导体封装的下侧配置的最下级用布线基板，
上述最下级用布线基板具有以与上述第1半导体封装的上述第2突起电极不同的图形排列的外部连接端子，且与上述第1半导体封装中的上述第2突起电极电气连接。
20.如权利要求15所述的半导体模块，其特征在于，
还具备在上述第1半导体封装的下侧配置的最下级专用的半导体装置，
上述最下级专用的半导体装置具备：在布线基板的第1面设置的第1突起电极；和在上述布线基板的第2面设置，以与上述第1半导体封装的上述第2突起电极不同的图形排列的外部连接端子，
上述最下级专用的半导体装置的上述第1突起电极，与上述第1半导体封装中的上述第2突起电极电气连接。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051374A (zh) * 2013-03-15 2014-09-17 株式会社东芝 半导体存储装置
CN106952879A (zh) * 2016-01-06 2017-07-14 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
JP2017135286A (ja) * 2016-01-28 2017-08-03 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN110707051A (zh) * 2019-10-14 2020-01-17 华天科技（西安）有限公司 一种带有散热盖的ssd存储芯片封装结构及制造方法
CN110767615A (zh) * 2019-10-14 2020-02-07 华天科技（西安）有限公司 一种ssd存储芯片封装结构及制造方法
CN114145080A (zh) * 2019-07-30 2022-03-04 三菱电机株式会社 芯片部件、芯片部件的制造方法以及电子设备的制造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6115505B2 (ja) * 2013-06-21 2017-04-19 株式会社デンソー 電子装置
KR20150071934A (ko) 2013-12-19 2015-06-29 에스케이하이닉스 주식회사 워페이지를 억제할 수 있는 패키지 온 패키지
US9627367B2 (en) 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
JP2017112325A (ja) * 2015-12-18 2017-06-22 Ｔｏｗａ株式会社 半導体装置及びその製造方法
US9806048B2 (en) 2016-03-16 2017-10-31 Qualcomm Incorporated Planar fan-out wafer level packaging
US10566310B2 (en) * 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
KR102517379B1 (ko) * 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083257A (zh) * 2006-05-31 2007-12-05 索尼株式会社 半导体装置
US20080258289A1 (en) * 2007-04-23 2008-10-23 Pendse Rajendra D Integrated circuit package system for package stacking
US20090045525A1 (en) * 2007-08-17 2009-02-19 Kabushiki Kaisha Toshiba Semiconductor element and semiconductor device
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083257A (zh) * 2006-05-31 2007-12-05 索尼株式会社 半导体装置
US20080258289A1 (en) * 2007-04-23 2008-10-23 Pendse Rajendra D Integrated circuit package system for package stacking
US20090045525A1 (en) * 2007-08-17 2009-02-19 Kabushiki Kaisha Toshiba Semiconductor element and semiconductor device
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051374A (zh) * 2013-03-15 2014-09-17 株式会社东芝 半导体存储装置
CN106952879A (zh) * 2016-01-06 2017-07-14 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
CN106952879B (zh) * 2016-01-06 2019-07-19 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
JP2017135286A (ja) * 2016-01-28 2017-08-03 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN114145080A (zh) * 2019-07-30 2022-03-04 三菱电机株式会社 芯片部件、芯片部件的制造方法以及电子设备的制造方法
CN110707051A (zh) * 2019-10-14 2020-01-17 华天科技（西安）有限公司 一种带有散热盖的ssd存储芯片封装结构及制造方法
CN110767615A (zh) * 2019-10-14 2020-02-07 华天科技（西安）有限公司 一种ssd存储芯片封装结构及制造方法

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Application publication date: 20121114