TW201232762A - Method and apparatus for manufacturing memory device having 3-dimensional structure - Google Patents

Method and apparatus for manufacturing memory device having 3-dimensional structure Download PDF

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TW201232762A
TW201232762A TW100136238A TW100136238A TW201232762A TW 201232762 A TW201232762 A TW 201232762A TW 100136238 A TW100136238 A TW 100136238A TW 100136238 A TW100136238 A TW 100136238A TW 201232762 A TW201232762 A TW 201232762A
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substrate
layer
group
holder
sacrificial
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TW100136238A
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TWI570890B (zh
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Sung-Gil Cho
Hai-Won Kim
Sang-Ho Woo
Seung-Woo Shin
Gil-Sun Jang
Wan-Suk Oh
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Eugene Technology Co Ltd
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Description

201232762 、發明說明: 【發明所屬之技術領域】 本文揭露之本發明係關於一種用於製造一記憶元 件之方法與設備,且更特別是關於一種用於製造具三維 結構之記憶元件的方法與設備。 【先前技術】 電子裝置雖然持續在微小化,但仍須處理大量的資 料。這個趨勢對於有微小化與高整合度電子裝置的記憶 元件是有需要的,因此,以三維結構來取代二維結構之 記憶元件已吸引到高度的關注。 【發明内容】 技術問題 本發明提供一種用於製造一微小化之記憶元件的 方法與設備。 本發明也提供一種用於有效製造具三維結構之記 憶元件的方法與設備。 本發明也提供一種用於製造一記憶元件之方法與 設備,其可避免基板因薄膜沉積期間薄膜之間的應力差 而產生變形。 在如附圖式與下述說明中係提出了 一或多種具體 實施例的細節。 技術方案 本發明之具體實施例提供了用於製造具三維結構
S 4 201232762 之,憶7^件的方法,方法包含:在-基板上交替地 堆疊-或多層介電層與—或多層犧牲層;形成一貫孔, 其=穿該等介電層與該等犧牲層;形成—圖樣,其填充 該貫孔;形成一開口,其貫穿該等介電層與該等犧牲 層,>以,經由该開口供應一钱刻劑,以移除該等犧牲 層。該等介電層之堆4係包含對該基板供應-或多種氣 體,以沉積一氧化矽層,該一或多種氣體係選自由 S1H4、Si#6、SuHs以及SLjH丨〇所組成之群組。該等犧 牲層之堆疊係包含對該基板供應—或多種氣體,以沉積 7氮化矽層’該一或多種氣體係選自由SiH4、Si2H6、、 、SUHm、二氯矽烷與含氨氣體所組成之 群組。 在某些具體實施例中,該介電層與該犧牲層對該蝕 刻劑具有一蝕刻選擇性,且該犧牲層具有一蝕刻速率, 其比該介電層的蝕刻速率大約5倍至約300倍。 在其他具體實施例中,該触刻劑包含自由H3p〇、 HF與一緩衝氧化物蝕刻劑(B〇E)所組成之群組3中所4 擇之至少一者。 、 人在另外其他具體實施例中,該等介電層之堆疊係包 合供應含乙基之氣體,且該氧化矽層包含氧化矽碳 (SiCO) 〇 在進一步其他具體實施例中,該等介電層之堆疊勺 含供應含甲基之氣體,且該氧化矽層包含氧化矽= (SiC〇)。 、 在又其他具體實施例中,該含氨氣體包含nh3。 201232762 攝氏3〇〇度至約攝氏79〇度之-^度以及介於^^ 托耳至約25〇托耳之一處理壓力。 、、、鼋 不同ΐΐ他具體實關巾,職切層與錢切層為 在進一步的具體實施例中,該等介電層鱼兮 層之交替堆疊係包含以一邊緣環對該基板之 壓。 運緣加 〜在其他具體實施例中,基板的邊緣具有—寬卢, 覓度係由該基板的一邊界向内約介於〇 5爪 間。 .王Jmm之 在更其他的具體實_巾,該邊緣環可由陶究所形 /vS4 在本發明之其他具體實施例中,用於製造具有 ^之記憶元件的方法包含:在—基板上交替地堆疊^ 或夕層介電層與一或多層犧牲層;形成一貫孔,並 該等介電層與該等犧牲層;形成-圖樣,其填^該貫 孔形成一開口,其貫穿該等介電層與該等犧牲層〔以 及經由該開口而供應一蝕刻劑,以移除該等犧牲層,1 中堆叠該等介電層係包含對該基板供應—或多種^ 體,以沉積-第-氧切層,該—或多種氣體係選自由 吨、s丨Λ、siA以及_丨0所組成之群組,且堆聶 該等犧牲層係包含對該基板供應選自由8泔4、&2取二 S!A、%ΗΙ0、二氯矽烷卿呢)與含氨氣體所組成之 鮮組之-或多種氣體’以及選自由响與%所組成
S 6 201232762 之群組之一或多種氣體,以沉積一氮化矽層,該氮化矽 層中係佈植有硼或磷。 在本發明之其他具體實施例中,用於製造具有三維 結構之§己憶元件的設備係包含:一腔體,一基板係於該 腔體中進行處理;一基板支座,設置於該腔體中,該基 板支座支撐該基板且垂直移動於一解除位置與一處理 位置之間’其中在該解除位置時可使允許基板被帶入該 腔體及自該腔體移出’且在該處理位置時該基板係被處 理;以及一邊緣環,其於該基板支座被置於該解除位置 時係配置於該基板上方,且包含一加壓表面,其於該基 板支座置於該處理位置中時對放置在該基板支座上之 該基板的一邊緣加壓。 該基板支座具有圍繞該基板之一環形邊緣,且該邊 緣環包含:一支座,其配置於該基板支座的該邊緣上 方;一加壓部件,其從該支座向該基板的該邊緣延伸, 且包含該加壓表面;一水平支座,其從該支座向該腔體 之一侧壁延伸,且當該基板支座位於該解除位置時,該 水平支座係放置於§亥腔體之該側壁上的一固定突出部 的一頂部表面上;以及一垂直支座,其從該支座向下延 伸’且當該基板支座位於該解除位置時,該垂直支座係 接觸在該腔體之該側壁上的該固定突出部的一側部表 面上。 有利效果 根據這些具體貫施例,一記憶元件係以三維結構來 形成,以減少其體積。此外,介電層與犧牲層係交替地 201232762 堆疊在一基板上,接著,利用如多晶矽薄膜之圖樣來作 為半導體電晶體之通道,此圖樣係被形成以支持介電 層,使得犧牲層可以被有效移除。此外,在沉積薄膜時,, 可避免因薄膜間應力差所導致之基板變形。 【實施方式】 現將參照第一圖至第十二圖,於下文中更詳細說明 本發明之較佳具體實施例。然而,本發明係可以不同形 式=以體現’且不應被解釋為僅受限於本文所提出的具 體實施例;反而,這些具體實施例係使得本文對於該領 域^術人士而言是通盤且完整的,並且完全涵蓋本發明 之範,。在圖式中’元件的維度係經放大以求說明清晰。 第一圖至第六圖為截面圖,其說明了根據本發明一 具體實施例之用於製造-記憶元件的方法。下文中,將 第一圖至第六圖來說明一種用於製造記憶元件的 參照第一圖,提供一基板105。基板105包含一半 體材料如第Iv族半導體、ΠΙ_ν族化合物半導體、 y-vi族氧化物半導體。舉例而言,第ιν族半導體係 矽鍺、或矽鍺化物。基板105可以塊材晶圓或磊 曰曰層的方式來提供。 册可在基板105的上方部分中佈植雜質,以限定出一 雜質區110。然後,在基板105上交替地堆疊介電層115 與犧牲層120。介電層115與犧牲層12〇可構成為8χ8、
Uxl8、或ηχη之多層體。在目前具體實施例中係先
S 8 201232762 形成介電層115,然後再形成犧牲層120。然而,也可 以先形成犧牲層12〇,然後再形成介電層115。 介電層115是由二氧化矽(Si〇2)所形成,其可藉由 使石夕烧(腿4)與氧化亞ll(N20)在基板105上反應而形 成。石夕烧可由Si2H6、Si3H8或Si4H10加以取代。 犧牲層120可由氮化矽(Si3NH4)形成,其可藉由使矽烷 與έ氨氣體在基板1〇5上反應而形成。石夕烧也可以 %Ηό、Si3tl8、%Η10或二氯矽烷(SiCl2H2)加以取代,而 含氨氣體可為NH3。或者是,可於基板1G5上供應選自 由随4、、SiA、SUH丨〇與SiCl#2所組成之群組 的一或多種氣體’含氨氣體,以及選自由B2H6和PH3 =〇且或多種氣體’以形成用於形成犧牲層 此例中,可於氮切中佈植衝或構。 ;,經:::二光接 經由形成多晶㈣層成之+程導序 序(或 130。在此時間點’圖樣 :真充圖樣 可具有一多晶結構或一薄腺 °圖樣130 之 蠢晶層。U錢祕’例如具有單晶結構 接著,參照第三圖,在圖樣13〇 與犧牲層120係經蝕刻以形成開口 135。可利丨:層115 術或蝕刻技術來形成開口 135。 ⑺用光微影 201232762 八者’參照第四圖’移除犧牲層12G。如上所述, ‘ ::由氧化矽所形成’而犧牲I UO是由氮化 盥一 ί疋措由供應選自由SiH4、Si2H6、Si3H8、Si4H10 自、由=^(Sl^2H2)所組成之群組的—或多種氣體和選 之氮化所組成之群組的一或多種氣體所形成 12〇與介電中佈植侧及/或•而形成。犧牲層 有約fcl··人蕾L 1 有蝕刻選擇性,且犧牲層120可具 此,當;電二倍至約300倍之银刻速率。因 犧牲層m “刻量暴露於姓刻劑時, 倍,且介電層心=:約5™
過開牲層120 °可利用等向性韻刻、通 式钱刻或化學乾115之間導入㈣劑’且包含濕 與緩衝氧化物2:0^3含選自由味⑽、HF 因此’犧牲層120係於介二,中的任-種。 連接至開口 135t^ 曰 之間被移除,以形成 的側壁。 ⑽道⑽。係暴露出圖樣!30 由開五於介電層115的側壁上以及 二 1:=:: =暴; 連、$形成-穿隧介電層142 上】50係措由 —阻播介電層】46而形成 電二了儲存層⑷、以及 成一傳導層i5 5。舉例而t,儲存存媒介15 0上形 係利用化學氡相沉積方法。或電
S 10 201232762 塗佈到-角落。 n’參照第六圖,對傳導層155(參照第五 數應之一部分選擇性㈣,以形。 以及電極162、複數個控制閘極電極164、 及,數個條帶選擇閘極電極166。 CH ^ Ϊ是’含乙基氣體(例如阳4)或含甲基氣體(例如 介二〇/、矽烷(SlH4)一起供應,因此介電層115可為氧 而低於犧牲層120 ’因而使介電層115 犧牲層120之移除所致之損失達最小化。第七圖為— ,其根據本發明一具體實施例說明沉積薄膜之蝕 =;;與含乙基氣體之供應量之間的關係。參照第七圖, h著含乙基氣體之供應量增加,沉積薄膜的蝕刻速;即 降低。因此,可控制介電層115與犧牲層12〇的蝕刻選 擇性。 、 第八圖為一示意圖,其說明根據本發明一具體實施 例之用於製造一記憶元件的設備。參照第八圖,用於製 造一記憶元件之設備10包含一導入部件12。來源氣體 或反應氣體係經由導入部件12而導入,並經由一喷淋 頭13而注入一腔體11中。在處理期間,可以約isccm 至約 1000sccm(standard cubic centimeter per minute,標 準狀態毫升/分鐘)的流量來供應石夕烧,並以約1 OOsccm 至約50000sccm供應反應氣體(例如N20或NH3)。如上 所述,可以約50sccm至約lOOOOsccm供應含乙基氣體(例 如C2H4)或含曱基氣體(例如CH3)。 201232762 一基板100(其為處理之物體)係放置在一基板支座 14上,該基板支座14係由一支座16支撐。基板支座 14可使基板100在處理期間保持在介於約攝氏3〇〇度至 約攝氏790度之溫度。在此時間點,腔體n的内壓係 介於約10毫托耳至約250托耳之間。當處理完成時, 係經由一排出部件17而排出基板15。 第九圖為一截面圖,其根據本發明另一具體實施例 而說明用於製造一記憶元件之設備。第十圖為一透視 圖,其說明第九圖之邊緣環。在目前的具體實施例中, 基本上將說明與前述具體實施例不同之部件,並將省略 與前述具體實施例相同部件之說明。 參照第九圖,用於製造一記憶元件之設備21()包含 一基板支座214,其置於一腔體211中。基板支座214 係由一支座216所支撐。一獨立驅動部件(未示)係使基 板支座214與支座216在一解除位置(參照第九圖)與一 處理位置(參照第十一圖)之間垂直移動,其中在解除位 置中,基板215係可被導入腔體211且從腔體211排出, 而基板215係在處理位置時被處理,其將於下文中加以 說明。 基板215係經由一排出部件217而被導入腔體211 與自腔體211排出,排出部件217係置於腔體211的一 側壁中。經由排出部件217而被導入腔體211的基板215 係置於基板支座214上方。基板支座214具有之直徑大 於基板215的直徑’基板215係置於基板支座214的中 央部分中。在此例中’基板215係由通過基板支座214 201232762 的舉升拴220所支撐,且與基板支座214朝上隔開。一 213係置於基板支座214上方。來源氣體或反應 軋體係經由喷淋頭213注入至腔體211中。 *腔體211包含一真空導件m與一邊緣環no。真 空導件212具有圓柱形狀,且置於腔體211中。參照第 十圖,邊緣環230具有與腔體211之内部形狀 環形形狀’且包含一支座232、一水平支座23:::垂 直支座236、以及一加壓部件238(其包含—加壓表面 38a)邊緣環230係置於基板支座214與喷淋頭213之 ,,且放置在自真空導件212的内壁突出之一固定突出 邻212a上(第十二圖)。參照第九圖,當基板支座214處 於解除位置時,邊緣環230係放置在固定突出部212a 上。s基板支座214置於處理位置時,邊緣環230係從 固定突出部212a移除、且放置在基板支座214上,其將 於下文中說明。 第十一圖與第十二圖為截面圖,其說明第九圖的邊 ’’彖環之運作。如上文所述,基板支座214與支座216係 藉由驅動部件(未示)而垂直移動於解除位置和處理位置 之間。 參照第十二圖,水平支座234係從支座232向腔體 211的側壁延伸,而垂直支座230係從支座232向下延 伸。加壓部件238從支座232朝腔體211的内部向下傾 斜延伸。 參照第九圖’當基板支座214置於解除位置時,邊 緣環230係經由水平支座234與垂直支座230而放置在 13 201232762 固定突出部212a上。在此時,水平支座234係接觸固定 突出部212a的頂部表面,而垂直支座236係接觸固定突 出部212a的側部表面。此外,支座232與加壓部件238 係朝向腔體211的内部而突出。 參照第十一圖’當基板支座214移動至處理位置 時,基板支座214利用其圍繞基板215之環形邊緣而自 固定突出部212a升高及使邊緣環230被移除。在此時, 參照第十二圖’支座232係與基板支座214的邊緣相 鄰’且加壓部件238接觸並加壓放置在基板支座214上 的基板215之邊緣。亦即’置於基板支座214上的邊緣 環230係利用其重量來加壓基板215的邊緣,而加壓部 件238的加壓表面238a係接觸基板215的邊緣。 當氧化矽層與氮化矽層交替地堆疊在第一圖所述 之基板上時’在處理期間會在氧化矽層與氮化矽層之間 產生一應力差,因而使基板翹曲。因此,基板的邊緣會 與基板支座分開’且基板的中央部分會變形為U字型。 這會影響基板中的溫度分佈(基板的中央與邊緣之間的 溫度分佈)’因而嚴重影響處理均勻度(例如沉積速率)。 在一領域中,在上述處理之後,基板邊緣中所測得的沉 積速率系明顯低於在基板的中央部分中所測得者。因 此’利用邊緣環230的加壓部件238來加壓基板215的 邊緣’以避免基板215的邊緣與基板支座214分開,因 而避免基板215之變形。 參照第十二圖’邊緣環230的加壓部件238所加壓 之基板215的邊緣之寬度w係介於從基板215的邊界向 201232762 内約0.5mm至約3mm之間。由於在半導體處理中對 應於寬度w的區域實質上並不用於作為半導體元件,因 此對應於寬度w之區域並不影響半導體元件的產率。同 時,加壓表面238a可具有寬度w。 參照第十二圖,邊緣環230可僅使用加壓部件238 來對基板支座214加壓基板215,且支座232係與基板 支座214的邊緣分隔一段距離d。在此例中,由 環230的總重量係經由加壓部件238的加壓表面只 而傳送至基板215的邊緣,即使當邊緣環23()的旦a 達最小時,仍可對基板215的邊崚絲w ^ @ 〜重里 壓力係與接觸面積成反比。4為以祕。這是因為 以上揭露標的係僅為描述之 如附申社直剎r鬥土外、了用而非限制之用,且 戈附申明專利犯H涵盍落於本 範疇中的所有這些修飾例、改良: ' 月,貫精神與 例。因此,;Μ曰岛丨、>馇分例、以及其他具體實施 =下述申請專利範圍之最廣可行解釋與其等效ί; 決疋,且不應受限於前述詳細說明。 又例采 【圖式簡單說明】 牛圖式係包含於本發明中以提供對本發明之進 且其係併入,書中而構成其-部分3 二月了本發日狀㈣彳具體實施例,且與發明制一= 於解釋本發明之原理。在圖式中: 起用 體第六圖為截面圖’其說明根據本發明一且 體貫%例之製造記憶元件的方法; 八 201232762 第=圖為-圖表,其根據本發明一具體實施例而說 明沉^相之_率與含乙基氣體之供應量的關係; 第八圖為一示意圖,其說明了根據本發明一具體實 施例之用於製造記憶元件的設備; —第九圖為一截面圖,其說明了根據本發明另一具體 貫施例之用於製造記憶元件的設備; 第十圖為一透視圖,其說明第九圖之一邊緣環;以 第十一 緣環的運作 圖與第十二圖為截面圖,其說明第九圖之邊 【主要天 10 11 12 13 14 16 17 1〇0 1〇5 110 115 120 125 70件符號說明 设備 腔體 導入部件 嘴淋頭 基板支座 支座 排出部件 基板 基板 雜質區 介電層 犧牲層 貫孔
S 16 201232762 130 135 140 142 144 146 150 155 162 164 166 210 211 212 212a 213 214 215 216 217 220 230 232 234 236 圖樣 開口 隧道 穿隧介電層 電荷儲存層 阻擋介電層 儲存媒介 傳導層 接地選擇閘極電極 控制閘極電極 條帶選擇閘極電極 設備 腔體 真空導件 固定突出部 喷淋頭 基板支座 基板 支座 排出部件 舉升栓 邊緣環 支座 水平支座 垂直支座 201232762 238 加壓部件 238a 加壓表面

Claims (1)

  1. 201232762 維結構之記憶元件的方法,其包 七、申請專利範圍: ι· 一種製造一具有一 括: 在一基板上交替地堆疊一或多層 多層犧牲層; 1电層與或 穿該等介電層與該等犧牲層; 形成一圖樣’其填充該貫孔; 形成-開口,其貫穿該等介電層與該等犧牲層; 以》及 經由該開口供應-㈣劑,以移除該等犧牲層. 《中堆疊該等介電層係包含對該基板供應一曰或 =種氣體,以沉積-氧切層,該—或多種氣體係選 自由S2H4、Sl2H6、Si3H8以及Si4Hl〇所組成之群組, 及 々堆疊該等犧牲層係包含對該基板供應一或多種 氣體’以沉積-氮切層,該—或多種氣體係選自由 =H4、Si2H6、Si3H8、Si4H10、二氯矽烧(sici2H2)與含 氣氣體所組成之群組。 2. 如申請專利範圍^項之方法,其中該介電層與該犧 牲層對该飯刻劑具有一钱刻選擇性,且 該犧牲層具有一蝕刻速率,其比該介電層的蝕刻 速率大約5倍至約300倍。 3. 如申請專利範圍帛1項或第2項之方法,其中該侧 劑包括自由H3P〇4、HF與一緩衝氧化物蝕刻劑(]50£;) 所組成之群組中所選擇之至少一者。 19 2〇1232762 .^申請專利範圍第i項或第2項之方法,其中堆疊該. 等介電層係包括供應含乙基之氣體,且 該氧化矽層包含氧化矽碳(SiCO)。 5·,申請專利範圍第1項或第2項之方法,其中堆疊該 等介電層包括供應含曱基之氣體,且 且 6. δ亥氧化矽層包括氧化矽碳(SiCO)。 ί二=範圍第1項或第2項之方法,其中該含氨 乳體包括ΝΗ3。 7. 8. 範圍第1項或第2項之方法,其中該基板 ]、、准持在;|於約攝氏300度至約攝氏790度之一溫度 乂,”於杓1〇毫托耳至約2s〇托耳之一處理壓力。 9. ‘ Γί ΐ利範圍第1項或第2項之方法’其中該氧化 夕層與δ亥氮化矽層為不同厚度。 ^清專利範圍第1項之方法,其巾交替地堆疊該等 該等犧牲層係包括以-邊緣環加壓該基板 10.圍第9項之方法,其中該基㈣該邊緣 以土板❸邊界向内的一寬度,該寬度係 、·勺0.5mm至約3mm之間。 ".=::=項或第〗。項之方法,其中該邊 件的方法’該記憶元件具有-三維 多層板上交替地堆疊-或多層介電層與-或 S 20 201232762 形成一貫孔,其貫穿該等介電層與該等犧牲層; 形成一圖樣,其填充該貫孔; 形成一開口,其貫穿該等介電層與該等犧牲層; 以及 經由該開口而供應一蝕刻劑,以移除該等犧牲 層; 其中堆疊該等介電層係包含對該基板供應一或 多種氣體,以沉積一第一氧化矽層,該一或多種氣體 係選自由SiH4、Si2H6、Si3H8以及Si4H10所組成之群 組,及 .堆疊該等犧牲層係包含對該基板供應選自由 SiH4、Si2H6、Si3H8、Si4H1()、二氯矽烷(SiCl2H2)與含 氨氣體所組成之群組之一或多種氣體,以及選自由 B2H6與PH3所組成之群組之一或多種氣體,以沉積 一氮化矽層,該氮化矽層中係佈植有硼或磷。 13. —種用於製造一具有三維結構之記憶元件之設備,其 包括: 一腔體,一基板係於該腔體中進行處理; 一基板支座’置於該腔體中’該基板支座支撐該 基板且垂直移動於一解除位置與一處理位置之間,其 中在該解除位置時可允許該基板被帶入該腔體及自 該腔體移出,且在該處理位置時該基板係被處理;以 及 一邊緣環,當該基板支座置於該解除位置時係配 置於該基板上方,且包含一加壓表面,其於該基板支 21 201232762 座置於該處理位置中時,對放置在該基板支座上之該 基板的一邊緣加壓。 14. 如申請專利範圍第丨3項之設備,其中該基板的該邊 緣具有由該基板的一邊界向内的一寬度,該寬度係介 於約0.5mm至約3mm之間。 15. 如申請專利範圍第13項或第14項之設備,其中該邊 緣環係由陶瓷所形成。 16. 如申請專利範圍第13項或第14項之設備,其中該基 板支座具有圍繞該基板之一環形邊緣;且 該邊緣環包括: 一支座,其;置於該基板支座的該邊緣上方; 加壓部件,其從該支座向該基板的該邊緣延 伸’且包含該加壓表面; 一水平支座,其從該支座向該腔體之一側壁延 =,.且當該基板支座位於該解除位置時,該水平支庙
    或多層介電層與一或多 I,該設備包括: 由在一基板上交替地堆疊一 ^ 層犧牲層而形成之一三維結才冓 腔體’該基板係於該腔體中進行處理. 基板支座,其配置於魏體中且切該基板; S 22 201232762 以及 一喷淋頭,其於該等介電層堆疊在該基板上時對 該基板供應一或多種氣體,該一或多種氣體係選自由 SiH4、Si2H6、Si3Hg以及SiqHi〇所組成之群組,且於 該等犧牲層堆疊於該基板上時對該基板供應一或多 種氣體,該一或多種氣體係選自由SiH4、Si2H6、 Si3H8、Si4H1G、二氯矽烷(SiCl2H2)與含氨氣體所組成 之群組。 18. —種用於製造一記憶元件之設備,該記憶元件具有藉 由在一基板上交替地堆疊一或多層介電層與一或多 層犧牲層而形成之一三維結構,該設備包含: 一腔體,該基板係於該腔體中進行處理; 一基板支座,其配置於該腔體中且支持該基板; 以及 一喷淋頭,其於該等介電層堆疊在該基板上時對 該基板供應選自由SiH4、Si2H6、Si3H8以及Si4H丨〇所 組成之群組之一或多種氣體,且於該等犧牲層堆疊在 該基板上時對該基板供應選自由SiH4、Si2H6、Si3H8、 Si4H1G、二氯矽烷(SiCl2H2)與含氨氣體所組成之群組 之一或多種氣體,以及選自由B2H6與PH3所組成之 群組之一或多種氣體。 23
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