TW201432885A - 製造具有三維結構之記憶元件的方法與設備 - Google Patents

製造具有三維結構之記憶元件的方法與設備 Download PDF

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TW201432885A
TW201432885A TW103116489A TW103116489A TW201432885A TW 201432885 A TW201432885 A TW 201432885A TW 103116489 A TW103116489 A TW 103116489A TW 103116489 A TW103116489 A TW 103116489A TW 201432885 A TW201432885 A TW 201432885A
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Sung-Gil Cho
Hai-Won Kim
Sang-Ho Woo
Seung-Woo Shin
Gil-Sun Jang
Wan-Suk Oh
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Eugene Technology Co Ltd
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Abstract

提供了一種製造具有三維結構之記憶元件的方法，其包含在一基板上交替地堆疊一或多層介電層與一或多層犧牲層；形成一貫孔，其貫穿該等介電層與該等犧牲層；形成一圖樣，其填充該貫孔；形成一開口，其貫穿該等介電層與該等犧牲層；以及經由該開口供應一蝕刻劑，以移除該等犧牲層。該等介電層之堆疊係包含對該基板供應一或多種氣體，以沉積一氧化矽層，該一或多種氣體係選自含SiH4、Si2H6、Si3H8以及Si4H10之群組。該等犧牲層之堆疊係包含對該基板供應一或多種氣體，以沉積一氮化矽層，該一或多種氣體係選自含SiH4、Si2H6、Si3H8、Si4H10、二氯矽烷(SiCl2H2)與含氨氣體之群組。

Description

製造具有三維結構之記憶元件的方法與設備
本文揭露之本發明係關於一種用於製造一記憶元件之方法與設備，且更特別是關於一種用於製造具三維結構之記憶元件的方法與設備。
電子裝置雖然持續在微小化，但仍須處理大量的資料。這個趨勢對於有微小化與高整合度電子裝置的記憶元件是有需要的，因此，以三維結構來取代二維結構之記憶元件已吸引到高度的關注。
本發明提供一種用於製造一微小化之記憶元件的方法與設備。
本發明也提供一種用於有效製造具三維結構之記憶元件的方法與設備。
本發明也提供一種用於製造一記憶元件之方法與設備，其可避免基板因薄膜沉積期間薄膜之間的應力差而產生變形。
在如附圖式與下述說明中係提出了一或多種具體實施例的細節。
本發明之具體實施例提供了用於製造具三維結構之記憶元件的方法，該等方法包含：在一基板上交替地堆疊一或多層介電層與一或多層犧牲層；形成一貫孔，其貫穿該等介電層與該等犧牲層；形成一圖樣，其填充該貫孔；形成一開口，其貫穿該等介電層與該等犧牲層；以及經由該開口供應一蝕刻劑，以移除該等犧牲層。該等介電層之堆疊係包含對該基板供應一或多種氣體，以沉積一氧化矽層，該一或多種氣體係選自由SiH4、Si2H6、Si3H8以及Si4H10所組成之群組。該等犧牲層之堆疊係包含對該基板供應一或多種氣體，以沉積一氮化矽層，該一或多種氣體係選自由SiH4、Si2H6、Si3H8、Si4H10、二氯矽烷(SiCl2H2)與含氨氣體所組成之群組。
在某些具體實施例中，該介電層與該犧牲層對該蝕刻劑具有一蝕刻選擇性，且該犧牲層具有一蝕刻速率，其比該介電層的蝕刻速率大約5倍至約300倍。
在其他具體實施例中，該蝕刻劑包含自由H3PO4、HF與一緩衝氧化物蝕刻劑(BOE)所組成之群組中所選擇之至少一者。
在另外其他具體實施例中，該等介電層之堆疊係包含供應含乙基之氣體，且該氧化矽層包含氧化矽碳(SiCO)。
在進一步其他具體實施例中，該等介電層之堆疊包含供應含甲基之氣體，且該氧化矽層包含氧化矽碳(SiCO)。
在又其他具體實施例中，該含氨氣體包含NH3。
在進一步的具體實施例中，該基板係維持為介於約攝氏300度至約攝氏790度之一溫度以及介於約10毫托耳至約250托耳之一處理壓力。
在其他具體實施例中，該氧化矽層與該氮化矽層為不同厚度。
在進一步的具體實施例中，該等介電層與該等犧牲層之交替堆疊係包含以一邊緣環對該基板之一邊緣加壓。
在其他具體實施例中，基板的邊緣具有一寬度，該寬度係由該基板的一邊界向內約介於0.5mm至3mm之間。
在更其他的具體實施例中，該邊緣環可由陶瓷所形成。
在本發明之其他具體實施例中，用於製造具有三維結構之記憶元件的方法包含：在一基板上交替地堆疊一或多層介電層與一或多層犧牲層；形成一貫孔，其貫穿該等介電層與該等犧牲層；形成一圖樣，其填充該貫孔；形成一開口，其貫穿該等介電層與該等犧牲層；以及經由該開口而供應一蝕刻劑，以移除該等犧牲層，其中堆疊該等介電層係包含對該基板供應一或多種氣體，以沉積一第一氧化矽層，該一或多種氣體係選自由SiH4、Si2H6、Si3H8以及Si4H10所組成之群組，且堆疊該等犧牲層係包含對該基板供應選自由SiH4、Si2H6、Si3H8、Si4H10、二氯矽烷(SiCl2H2)與含氨氣體所組成之群組之一或多種氣體，以及選自由B2H6與PH3所組成之群組之一或多種氣體，以沉積一氮化矽層，該氮化矽層中係佈植有硼或磷。
在本發明之其他具體實施例中，用於製造具有三維結構之記憶元件的設備係包含：一腔體，一基板係於該腔體中進行處理；一基板支座，設置於該腔體中，該基板支座支撐該基板且垂直移動於一解除位置與一處理位置之間，其中在該解除位置時可使允許基板被帶入該腔體及自該腔體移出，且在該處理位置時該基板係被處理；以及一邊緣環，其於該基板支座被置於該解除位置時係配置於該基板上方，且包含一加壓表面，其於該基板支座置於該處理位置中時對放置在該基板支座上之該基板的一邊緣加壓。
該基板支座具有圍繞該基板之一環形邊緣，且該邊緣環包含：一支座，其配置於該基板支座的該邊緣上方；一加壓部件，其從該支座向該基板的該邊緣延伸，且包含該加壓表面；一水平支座，其從該支座向該腔體之一側壁延伸，且當該基板支座 位於該解除位置時，該水平支座係放置於該腔體之該側壁上的一固定突出部的一頂部表面上；以及一垂直支座，其從該支座向下延伸，且當該基板支座位於該解除位置時，該垂直支座係接觸在該腔體之該側壁上的該固定突出部的一側部表面上。
根據這些具體實施例，一記憶元件係以三維結構來形成，以減少其體積。此外，介電層與犧牲層係交替地堆疊在一基板上，接著，利用如多晶矽薄膜之圖樣來作為半導體電晶體之通道，此圖樣係被形成以支持介電層，使得犧牲層可以被有效移除。此外，在沉積薄膜時，可避免因薄膜間應力差所導致之基板變形。
10‧‧‧設備
11‧‧‧腔體
12‧‧‧導入部件
13‧‧‧噴淋頭
14‧‧‧基板支座
16‧‧‧支座
17‧‧‧排出部件
100‧‧‧基板
105‧‧‧基板
110‧‧‧雜質區
115‧‧‧介電層
120‧‧‧犧牲層
125‧‧‧貫孔
130‧‧‧圖樣
135‧‧‧開口
140‧‧‧隧道
142‧‧‧穿隧介電層
144‧‧‧電荷儲存層
146‧‧‧阻擋介電層
150‧‧‧儲存媒介
155‧‧‧傳導層
162‧‧‧接地選擇閘極電極
164‧‧‧控制閘極電極
166‧‧‧條帶選擇閘極電極
210‧‧‧設備
211‧‧‧腔體
212‧‧‧真空導件
212a‧‧‧固定突出部
213‧‧‧噴淋頭
214‧‧‧基板支座
215‧‧‧基板
216‧‧‧支座
217‧‧‧排出部件
220‧‧‧舉升栓
230‧‧‧邊緣環
232‧‧‧支座
234‧‧‧水平支座
236‧‧‧垂直支座
238‧‧‧加壓部件
238a‧‧‧加壓表面
如附圖式係包含於本發明中以提供對本發明之進一步瞭解，且其係併入說明書中而構成其一部分。圖式說明了本發明之示例具體實施例，且與發明說明一起用於解釋本發明之原理。在圖式中：第一圖至第六圖為截面圖，其說明根據本發明一具體實施例之製造記憶元件的方法；第七圖為一圖表，其根據本發明一具體實施例而說明沉積薄膜之蝕刻率與含乙基氣體之供應量的關係；第八圖為一示意圖，其說明了根據本發明一具體實施例之用於製造記憶元件的設備；第九圖為一截面圖，其說明了根據本發明另一具體實施例之用於製造記憶元件的設備；第十圖為一透視圖，其說明第九圖之一邊緣環；以及第十一圖與第十二圖為截面圖，其說明第九圖之邊緣環的運作。
現將參照第一圖至第十二圖，於下文中更詳細說明本發明之較佳具體實施例。然而，本發明係可以不同形式予以體現，且不應被解釋為僅受限於本文所提出的具體實施例；反而，這些具體實施例係使得本文對於該領域技術人士而言是通盤且完整的，並且完全涵蓋本發明之範疇。在圖式中，元件的維度係經放大以求說明清晰。
第一圖至第六圖為截面圖，其說明了根據本發明一具體實施例之用於製造一記憶元件的方法。下文中，將參照第一圖至第六圖來說明一種用於製造記憶元件的方法。
參照第一圖，提供一基板105。基板105包含一半導體材料，例如第IV族半導體、III-V族化合物半導體、或II-VI族氧化物半導體。舉例而言，第IV族半導體係包含矽、鍺、或矽鍺化物。基板105可以塊材晶圓或磊晶層的方式來提供。
可在基板105的上方部分中佈植雜質，以限定出一雜質區110。然後，在基板105上交替地堆疊介電層115與犧牲層120。介電層115與犧牲層120可構成為8×8、18×18、或n×n之多層體。在目前具體實施例中，係先形成介電層115，然後再形成犧牲層120。然而，也可以先形成犧牲層120，然後再形成介電層115。
介電層115是由二氧化矽(SiO2)所形成，其可藉由使矽烷(SiH4)與氧化亞氮(N2O)在基板105上反應而形成。矽烷(SiH4)可由Si2H6、Si3H8或Si4H10加以取代。犧牲層120可由氮化矽(Si3NH4)形成，其可藉由使矽烷與含氨氣體在基板105上反應而形成。矽烷也可以Si2H6、Si3H8、Si4H10或二氯矽烷(SiCl2H2)加以取代，而含氨氣體可為NH3。或者是，可於基板105上供應選自由 SiH4、Si2H6、Si3H8、Si4H10與SiCl2H2所組成之群組的一或多種氣體，含氨氣體，以及選自由B2H6和PH3所組成之群組的一或多種氣體，以形成用於形成犧牲層120之氧化矽。在此例中，可於氮化矽中佈植硼及/或磷。
其次，參照第二圖，介電層115與犧牲層120係經蝕刻以形成貫孔125，其貫穿介電層115與犧牲層120。貫孔125係利用習知的光微影術或蝕刻技術而形成。接著，經由習知用於形成半導體電晶體之通道形成程序(或經由形成多晶矽薄層之程序)，於貫孔125中填充圖樣130。在此時間點，圖樣130可具有一中空圓柱形狀，且其通過介電層115與犧牲層120。舉例而言，圖樣130可具有一多晶結構或一薄膜形狀，例如具有單晶結構之磊晶層。
接著，參照第三圖，在圖樣130之間的介電層115與犧牲層120係經蝕刻以形成開口135。可利用光微影術或蝕刻技術來形成開口135。
接著，參照第四圖，移除犧牲層120。如上所述，介電層115是由氧化矽所形成，而犧牲層120是由氮化矽、或是藉由供應選自由SiH4、Si2H6、Si3H8、Si4H10與二氯矽烷(SiCl2H2)所組成之群組的一或多種氣體和選自由B2H6和PH3所組成之群組的一或多種氣體所形成之氮化矽、並在氮化矽中佈植硼及/或磷而形成。犧牲層120與介電層115具有蝕刻選擇性，且犧牲層120可具有約比介電層115大約5倍至約300倍之蝕刻速率。因此，當介電層115與犧牲層120同時暴露於蝕刻劑時，犧牲層120的蝕刻量大於介電層115的約5倍至約300倍，且介電層115的蝕刻量是非常小的。
因此，可移除犧牲層120。可利用等向性蝕刻、通過開口135而在介電層115之間導入蝕刻劑，且包含濕式蝕刻或化學乾式蝕刻。蝕刻劑可含選自由H3PO4、HF與緩衝氧化物蝕刻劑 (BOE)所組成之群組中的任一種。因此，犧牲層120係於介電層115之間被移除，以形成連接至開口135之隧道140。隧道140係暴露出圖樣130的側壁。
接著，參照第五圖，可於介電層115的側壁上以及由開口135(參照第四圖)與隧道140(參照第四圖)所暴露的圖樣130上形成儲存媒介150。儲存媒介150係藉由連續形成一穿隧介電層142、一電荷儲存層144、以及一阻擋介電層146而形成。然後，於儲存媒介150上形成一傳導層155。舉例而言，儲存媒介150與傳導層155係利用化學氣相沉積方法或電鍍方法而形成，其可有效塗佈到一角落。
接著，參照第六圖，對傳導層155(參照第五圖)與開口135(參照第四圖)對應之一部分選擇性蝕刻，以形成複數個接地選擇閘極電極162、複數個控制閘極電極164、以及複數個條帶選擇閘極電極166。
或者是，含乙基氣體(例如C2H4)或含甲基氣體(例如CH3)可與矽烷(SiH4)一起供應，因此介電層115可為氧化矽碳(SiCO)之薄膜。在此例中，介電層115之蝕刻速率會進一步降低而低於犧牲層120，因而使介電層115因犧牲層120之移除所致之損失達最小化。第七圖為一圖表，其根據本發明一具體實施例說明沉積薄膜之蝕刻速率與含乙基氣體之供應量之間的關係。參照第七圖，隨著含乙基氣體之供應量增加，沉積薄膜的蝕刻速率即降低。因此，可控制介電層115與犧牲層120的蝕刻選擇性。
第八圖為一示意圖，其說明根據本發明一具體實施例之用於製造一記憶元件的設備。參照第八圖，用於製造一記憶元件之設備10包含一導入部件12。來源氣體或反應氣體係經由導入部件12而導入，並經由一噴淋頭13而注入一腔體11中。在處理期間，可以約1sccm至約1000sccm(standard cubic centimeter per minute，標準狀態毫升/分鐘)的流量來供應矽烷，並以約100sccm至約50000sccm供應反應氣體(例如N2O或NH3)。如上所述，可以約50sccm至約10000sccm供應含乙基氣體(例如C2H4)或含甲基氣體(例如CH3)。
一基板100(其為處理之物體)係放置在一基板支座14上，該基板支座14係由一支座16支撐。基板支座14可使基板100在處理期間保持在介於約攝氏300度至約攝氏790度之溫度。在此時間點，腔體11的內壓係介於約10毫托耳至約250托耳之間。當處理完成時，係經由一排出部件17而排出基板15。
第九圖為一截面圖，其根據本發明另一具體實施例而說明用於製造一記憶元件之設備。第十圖為一透視圖，其說明第九圖之邊緣環。在目前的具體實施例中，基本上將說明與前述具體實施例不同之部件，並將省略與前述具體實施例相同部件之說明。
參照第九圖，用於製造一記憶元件之設備210包含一基板支座214，其置於一腔體211中。基板支座214係由一支座216所支撐。一獨立驅動部件(未示)係使基板支座214與支座216在一解除位置(參照第九圖)與一處理位置(參照第十一圖)之間垂直移動，其中在解除位置中，基板215係可被導入腔體211且從腔體211排出，而基板215係在處理位置時被處理，其將於下文中加以說明。
基板215係經由一排出部件217而被導入腔體211與自腔體211排出，排出部件217係置於腔體211的一側壁中。經由排出部件217而被導入腔體211的基板215係置於基板支座214上方。基板支座214具有之直徑大於基板215的直徑，基板215係置於基板支座214的中央部分中。在此例中，基板215係由通過基板支座214的舉升栓220所支撐，且與基板支座214朝上隔開。一噴淋頭213係置於基板支座214上方。來源氣體或 反應氣體係經由噴淋頭213注入至腔體211中。
腔體211包含一真空導件212與一邊緣環230。真空導件212具有圓柱形狀，且置於腔體211中。參照第十圖，邊緣環230具有與腔體211之內部形狀對應的一環形形狀，且包含一支座232、一水平支座234、一垂直支座236、以及一加壓部件238(其包含一加壓表面238a)。邊緣環230係置於基板支座214與噴淋頭213之間，且放置在自真空導件212的內壁突出之一固定突出部212a上(第十二圖)。參照第九圖，當基板支座214處於解除位置時，邊緣環230係放置在固定突出部212a上。當基板支座214置於處理位置時，邊緣環230係從固定突出部212a移除、且放置在基板支座214上，其將於下文中說明。
第十一圖與第十二圖為截面圖，其說明第九圖的邊緣環之運作。如上文所述，基板支座214與支座216係藉由驅動部件(未示)而垂直移動於解除位置和處理位置之間。
參照第十二圖，水平支座234係從支座232向腔體211的側壁延伸，而垂直支座236係從支座232向下延伸。加壓部件238從支座232朝腔體211的內部向下傾斜延伸。
參照第九圖，當基板支座214置於解除位置時，邊緣環230係經由水平支座234與垂直支座236而放置在固定突出部212a上。在此時，水平支座234係接觸固定突出部212a的頂部表面，而垂直支座236係接觸固定突出部212a的側部表面。此外，支座232與加壓部件238係朝向腔體211的內部而突出。
參照第十一圖，當基板支座214移動至處理位置時，基板支座214利用其圍繞基板215之環形邊緣而自固定突出部212a升高及使邊緣環230被移除。在此時，參照第十二圖，支座232係與基板支座214的邊緣相鄰，且加壓部件238接觸並加壓放置在基板支座214上的基板215之邊緣。亦即，置於基板支座214上的邊緣環230係利用其重量來加壓基板215的邊緣，而 加壓部件238的加壓表面238a係接觸基板215的邊緣。
當氧化矽層與氮化矽層交替地堆疊在第一圖所述之基板上時，在處理期間會在氧化矽層與氮化矽層之間產生一應力差，因而使基板翹曲。因此，基板的邊緣會與基板支座分開，且基板的中央部分會變形為U字型。這會影響基板中的溫度分佈(基板的中央與邊緣之間的溫度分佈)，因而嚴重影響處理均勻度(例如沉積速率)。在一領域中，在上述處理之後，基板邊緣中所測得的沉積速率系明顯低於在基板的中央部分中所測得者。因此，利用邊緣環230的加壓部件238來加壓基板215的邊緣，以避免基板215的邊緣與基板支座214分開，因而避免基板215之變形。
參照第十二圖，邊緣環230的加壓部件238所加壓之基板215的邊緣之寬度w係介於從基板215的邊界向內約0.5mm至約3mm之間。由於在半導體處理中，對應於寬度w的區域實質上並不用於作為半導體元件，因此對應於寬度w之區域並不影響半導體元件的產率。同時，加壓表面238a可具有寬度w。
參照第十二圖，邊緣環230可僅使用加壓部件238來對基板支座214加壓基板215，且支座232係與基板支座214的邊緣分隔一段距離d。在此例中，由於邊緣環230的總重量係經由加壓部件238的加壓表面238a而傳送至基板215的邊緣，即使當邊緣環230的總重量達最小時，仍可對基板215的邊緣施以高壓。這是因為壓力係與接觸面積成反比。
以上揭露標的係僅為描述之用、而非限制之用，且如附申請專利範圍意欲涵蓋落於本發明之真實精神與範疇中的所有這些修飾例、改良例、以及其他具體實施例。因此，為得到法律允許之最大範圍，本發明之範疇係由下述申請專利範圍之最廣可行解釋與其等效例來決定，且不應受限於前述詳細說明。
105‧‧‧基板
110‧‧‧雜質區
115‧‧‧介電層
120‧‧‧犧牲層

Claims (6)

  1. 一種用於製造一具有三維結構之記憶元件之設備，其包括：一腔體，一基板係於該腔體中進行處理；一基板支座，置於該腔體中，該基板支座支撐該基板且垂直移動於一解除位置與一處理位置之間，其中在該解除位置時可允許該基板被帶入該腔體及自該腔體移出，且在該處理位置時該基板係被處理；以及一邊緣環，當該基板支座置於該解除位置時係配置於該基板上方，且包含一加壓表面，其於該基板支座置於該處理位置中時，對放置在該基板支座上之該基板的一邊緣加壓。
  2. 如申請專利範圍第1項之設備，其中該基板的該邊緣具有由該基板的一邊界向內的一寬度，該寬度係介於約0.5mm至約3mm之間。
  3. 如申請專利範圍第1項或第2項之設備，其中該邊緣環係由陶瓷所形成。
  4. 如申請專利範圍第1項或第2項之設備，其中該基板支座具有圍繞該基板之一環形邊緣；且該邊緣環包括：一支座，其置於該基板支座的該邊緣上方；一加壓部件，其從該支座向該基板的該邊緣延伸，且包含該加壓表面；一水平支座，其從該支座向該腔體之一側壁延伸，且當該基板支座位於該解除位置時，該水平支座係放置於該腔體之該側壁上的一固定突出部的一頂部表面上；以及一垂直支座，其從該支座向下延伸，且當該基板支座位於該解除位置時，該垂直支座係接觸在該腔體之該側壁上的該固定突出部的一側部表面上。
  5. 如申請專利範圍第1項或第2項之設備，其中更包括一噴淋 頭，其於該等介電層堆疊在該基板上時對該基板供應一或多種氣體，該一或多種氣體係選自由SiH4、Si2H6、Si3H8以及Si4H10所組成之群組，且於該等犧牲層堆疊於該基板上時對該基板供應一或多種氣體，該一或多種氣體係選自由SiH4、Si2H6、Si3H8、Si4H10、二氯矽烷(SiCl2H2)與含氨氣體所組成之群組。
  6. 如申請專利範圍第1項或第2項之設備，其中更包括一噴淋頭，其於該等介電層堆疊在該基板上時對該基板供應選自由SiH4、Si2H6、Si3H8以及Si4H10所組成之群組之一或多種氣體，且於該等犧牲層堆疊在該基板上時對該基板供應選自由SiH4、Si2H6、Si3H8、Si4H10、二氯矽烷(SiCl2H2)與含氨氣體所組成之群組之一或多種氣體，以及選自由B2H6與PH3所組成之群組之一或多種氣體。
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