WO2022000119A1 - 三维存储器及三维存储器的制备方法 - Google Patents

三维存储器及三维存储器的制备方法 Download PDF

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Publication number
WO2022000119A1
WO2022000119A1 PCT/CN2020/098475 CN2020098475W WO2022000119A1 WO 2022000119 A1 WO2022000119 A1 WO 2022000119A1 CN 2020098475 W CN2020098475 W CN 2020098475W WO 2022000119 A1 WO2022000119 A1 WO 2022000119A1
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layer
channel structure
sacrificial
storage
single crystal
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PCT/CN2020/098475
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English (en)
French (fr)
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景蔚亮
王正波
崔靖杰
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华为技术有限公司
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Priority to CN202080101285.1A priority Critical patent/CN115669261A/zh
Priority to PCT/CN2020/098475 priority patent/WO2022000119A1/zh
Publication of WO2022000119A1 publication Critical patent/WO2022000119A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present application relates to the field of semiconductor devices, in particular to a three-dimensional memory and a method for preparing the three-dimensional memory.
  • Three-dimensional (3-dimension, 3D) memory has high storage capacity and low production cost, and has received extensive attention.
  • the three-dimensional memory includes a stack structure formed on a substrate, a channel structure penetrating the stack structure, and a storage layer on a surface of the channel structure.
  • the stacked structure includes alternating multiple conductor layers and multiple dielectric layers.
  • the conductive material in each conductor layer in the stack is obtained by replacing the sacrificial material. In the process of replacing the sacrificial material, there may be process deviations in the etching of the sacrificial material, resulting in over-etching or under-etching of the sacrificial material in the horizontal direction for one or more conductor layers, affecting the performance parameters of the transistor. . Over-etching may even damage the memory structure on the surface of the channel structure, so that the transistor corresponding to the conductor layer does not have the ability to store data, that is, the memory cell fails.
  • the present application provides a three-dimensional memory, which can improve the reliability of the memory.
  • a three-dimensional memory including a stacked structure, a channel structure, and a storage structure.
  • the stacked structure includes alternately stacked conductor layers and dielectric layers; the channel structure penetrates the stacked structure.
  • the conductor layer includes conductive material.
  • the storage structure is in the conductor layer, formed on the surface of the channel structure, and between the channel structure and the conductive material.
  • the storage structure of the three-dimensional memory is located in the conductor layer and formed on the surface of the channel structure, so that when manufacturing the three-dimensional memory, it is avoided that the performance of the three-dimensional memory is affected by excessive etching or insufficient etching due to process errors in the process of removing the sacrificial material. The effect of improving the performance of 3D memory.
  • the channel structure includes a single crystal semiconductor material.
  • the electron mobility of the single crystal semiconductor material is high, and the channel structure adopts the single crystal semiconductor material, which can improve the performance of the three-dimensional memory.
  • the dielectric layer includes a protection structure, and the protection structure is located on a surface of the channel structure.
  • the channel structure can be formed by selective epitaxial growth (SEG) technology.
  • SEG selective epitaxial growth
  • elements eg, nitrogen
  • the sacrificial layer of the stacked structure may diffuse into the single crystal semiconductor of the channel structure, thereby affecting the performance of the three-dimensional memory.
  • the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated.
  • removing the protective layer whose surface of the channel structure is located at the removed sacrificial layer can avoid the influence of the process deviation of the etching process on the performance parameters of the transistor.
  • the material of the channel structure is monocrystalline silicon; the material of each protection structure is amorphous silicon.
  • amorphous silicon is significantly lower than that of crystalline silicon, and its chemical properties are more active than that of crystalline silicon. Therefore, single-crystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.
  • a surface of the channel structure includes a groove, and the storage structure is located in the groove.
  • the number of defects in the single crystal silicon channel structure can be reduced, thereby reducing the influence of the defects on the performance of the three-dimensional memory.
  • the material of the channel structure is single crystal silicon with a single crystal lattice direction of "001" along the channel structure running through the stacked structure.
  • Single crystal silicon with a lattice direction of "001" grows faster.
  • the number of defects can be reduced by providing grooves where the conductive layer on the surface of the channel structure is located.
  • the height of the channel structure can be increased while meeting the mobility requirements for the channel structure.
  • the time required for the growth of single crystal silicon is normal.
  • the channel structure adopts single crystal silicon with a lattice direction of "001", so that a faster growth rate of single crystal silicon can be obtained, the process time for preparing a three-dimensional memory is shortened, and the manufacturing cost is reduced.
  • the storage structure includes a tunneling layer, a charge trapping layer, and a blocking layer that are sequentially arranged in a direction away from the channel structure.
  • a method for preparing a three-dimensional memory comprising: forming a stacked structure on a substrate, the stacked structure including alternately stacked sacrificial layers and dielectric layers; and forming a channel structure, the channel structure penetrating the stacked structure , and pass through the sacrificial material in the sacrificial layer; remove the sacrificial material; form a storage structure at the position where the sacrificial material is removed on the surface of the channel structure; deposit a conductive material to replace the removed sacrificial material.
  • the storage structure is formed after removing the sacrificial material in the stacked structure, which avoids the influence of excessive etching or insufficient etching on the performance of the three-dimensional memory due to process errors when the sacrificial layer is removed, and improves the performance of the three-dimensional memory.
  • the channel structure is a single crystal semiconductor material.
  • the forming the channel structure includes: forming a storage hole, the storage hole penetrating the stacked structure and passing through the sacrificial material; A protective layer is formed on the sidewall of the storage hole; a single crystal semiconductor material is grown in the storage hole to form the channel structure.
  • elements such as nitrogen
  • the sacrificial material of the stacked structure may diffuse into the single crystal semiconductor of the channel structure, thereby affecting the performance of the three-dimensional memory.
  • a protective layer on the surface of the channel structure, the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated, thereby improving the performance of the three-dimensional memory.
  • the method further includes: removing the protective layer at the position of each sacrificial layer on the surface of the channel structure.
  • removing the protective layer whose surface of the channel structure is located at the removed sacrificial layer can avoid the influence of the process deviation of the etching process on the performance parameters of the transistor.
  • the material of the channel structure is monocrystalline silicon; the material of each protection structure is amorphous silicon.
  • removing the protective layer at the position of the sacrificial material on the surface of the channel structure includes: using an etching process to remove the protective layer at the position of the sacrificial material on the surface of the channel structure,
  • the semiconductor material grown in the storage hole is an etch stop layer.
  • the time precision requirement for the etching process can be reduced, and the difficulty of the etching process can be reduced.
  • the semiconductor material grown in the storage hole is monocrystalline silicon; the material of the protective layer is amorphous silicon.
  • amorphous silicon is significantly lower than that of crystalline silicon, and its chemical properties are more active than that of crystalline silicon. Therefore, single-crystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.
  • the channel structure includes a single crystal semiconductor material.
  • the method also includes forming grooves in the surface of the channel structure where the sacrificial material is removed. Forming a storage structure on the surface of the channel structure where the sacrificial material is removed includes: forming the storage structure in a groove.
  • the number of defects in the single crystal silicon channel structure can be reduced, thereby reducing the effect of defects on the performance of the three-dimensional memory.
  • the forming a groove at each position on the surface of the channel structure where the sacrificial layer is removed includes: forming an oxide at the position on the surface of the channel structure where the sacrificial material is removed; The oxide is removed to form the grooves.
  • the channel structure is usually monocrystalline silicon or polycrystalline silicon, and the material of the dielectric layer is usually silicon oxide. If the channel structure is etched, the structure of the dielectric layer may be affected.
  • the material of the channel structure is a single crystal lattice direction of "001" single crystal silicon along a direction of the channel structure away from the substrate.
  • Single crystal silicon with a lattice direction of "001" grows faster.
  • the number of defects can be reduced by providing grooves where the conductive layer on the surface of the channel structure is located.
  • the height of the channel structure can be increased while meeting the mobility requirements for the channel structure.
  • the time required for the growth of single crystal silicon is normal.
  • the channel structure adopts single crystal silicon with a lattice direction of "001", so that a faster growth rate of single crystal silicon can be obtained, the process time for preparing a three-dimensional memory is shortened, and the manufacturing cost is reduced.
  • forming a storage structure at the position where the sacrificial layer is removed on the surface of the channel structure includes: at the position where the sacrificial layer is removed on the surface of the channel structure , forming a tunneling layer, a charge trapping layer and a blocking layer stacked in the storage structure in sequence.
  • an electronic device including the three-dimensional memory of the first aspect.
  • FIG. 1 is a schematic diagram of a circuit structure of a NAND string.
  • FIG. 2 is a schematic structural diagram of a three-dimensional memory.
  • FIG. 3 is a schematic structural diagram of a partial area of a three-dimensional memory.
  • FIG. 4 is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the crystal structure of single crystal silicon.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present application.
  • FIG. 7 to 19 are schematic structural diagrams of a three-dimensional memory provided in an embodiment of the present application in a manufacturing process.
  • FIG. 20 is a schematic structural diagram of a three-dimensional memory and a control circuit provided by an embodiment of the present application.
  • FIG. 21 is a schematic flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present application.
  • on, “over”, “to”, “between”, and “on”, etc. as used herein may refer to the relative relationship of one layer with respect to another layer Location.
  • a layer is “on”, “over” or “on” another layer, or, connected or bonded “to” or “in contact with” another layer may be in direct contact with the other layer or may have a or multiple intervening layers.
  • a layer “between” multiple layers may be in direct contact with the multiple layers or may have one or more intervening layers.
  • three-dimensional (3-dimension, 3D) memory has higher storage capacity and lower production cost, and has received extensive attention.
  • FIG. 1 is a schematic circuit topology diagram of a three-dimensional NAND string.
  • FIG. 2 is a schematic structural diagram of a three-dimensional memory.
  • NAND is an operation method, if and only if the value of all operands is 1, the result of the operation is zero; otherwise, the result of the operation is 1.
  • the Boolean operator for AND operation is NAND.
  • NAND strings can also be referred to as NAND strings.
  • Three-dimensional memory may include multiple NAND strings.
  • Each NAND string may include a plurality of transistors arranged in series, and four series-connected transistors Q0 , Q1 , Q2 , and Q3 are taken as an example for illustration.
  • a NAND string includes transistors with storage capabilities. Each transistor with storage capability has a control gate (CG) and a charge storage region (CSR).
  • the CSR may include, for example, a charge trapping layer.
  • transistors Q1 and Q2 have memory capability.
  • the select gate of transistor Q1 is connected to word line (WL) 0, and the select gate of transistor Q2 is connected to WL1.
  • Each transistor can be understood as a memory cell.
  • transistors may also be included in the NAND string.
  • the gate of the transistor Q3 can be connected through the select line SGS to control the turn-on or turn-off of the transistor Q3, thereby controlling whether the NAND string is connected to the bit line (BL) 111.
  • the gate of the transistor Q0 can also be connected through the select line SGD to control the turn-on or turn-off of the transistor Q0, thereby controlling whether the NAND string is connected to the common source line 128.
  • Transistors Q0 and Q3 may also include charge storage regions, but, during use, do not store charge in the charge storage regions of transistors Q0 and Q3.
  • the charge storage region can store charge in a non-volatile manner using a non-conducting dielectric material.
  • the charge storage region may be a three-layer dielectric formed of oxide, nitride layer, oxide-nitride-oxide (ONO) sandwiched between the control gate and the channel of the transistor.
  • ONO may be composed of silicon oxide (SiO 2 )-silicon nitride (Si 3 N 4 )-silicon oxide, or ONO may be aluminum oxide (Al 2 O 3 )-Si 3 N 4 -SiO 2 or the like.
  • the charge trapping layer 243 is sandwiched between the blocking layer 244 and the tunneling layer 242 .
  • the first layer of oxide is a blocking layer 244 for blocking electron tunneling from the charge trapping layer 243 to the control gate or from the control gate to the charge trapping layer 243 .
  • the barrier layer 244 may be a stack of dielectrics, eg, in one embodiment, the barrier layer may be a stack of dielectrics Al 2 O 3 -SiO 2 .
  • the second layer of oxide is the tunneling layer 242 through which electrons can tunnel from the channel to the charge trapping layer 243 during programming. Electrons tunnel from the channel to the charge trapping layer 243 through the tunneling layer 242 , which may also be referred to as electron injection into the charge trapping layer 243 .
  • a transistor with memory capability can be programmed by injecting electrons from channel structure 240 into the nitride of charge trapping layer 243 where electrons are trapped and stored in a limited area.
  • the charge stored by the charge trapping layer 243 can change the threshold voltage of the transistor.
  • the threshold voltage of the transistor when electrons are not injected into the charge trapping layer 243 is VT1
  • the threshold voltage of the transistor after electrons are injected into the charge trapping layer 243 is VT2.
  • the voltage of the control gate of the transistor is between VT1 and VT2
  • the on and off states of the transistor can respectively represent "1" and "0" in digital logic, thereby realizing data storage.
  • the erasing of data stored in the transistor can be realized by injecting holes into the charge trapping layer 243 formed by the nitride, and recombining the injected holes with electrons.
  • Data stored in the transistor can also be erased by extracting electrons from the nitride, eg, by applying an electric field to tunnel electrons from the charge trapping layer 243 formed by the nitride to the channel.
  • these two mechanisms can also be used to erase data at the same time.
  • an insulating film 220 is provided on the substrate 210 , a metal layer is provided on the insulating film 220 , and a common source line SL0 is provided in the metal layer.
  • the stacked structure includes alternately stacked metal layers and insulating layers.
  • a channel structure 240 is provided in the stacked structure.
  • the NAND string shown in (A) of FIG. 2 is a straight line, and the two channel structures 240 correspond to the NAND string C0 and the NAND string C1, respectively.
  • FIG. 2 is an enlarged schematic view of a partial region of (A) in FIG. 2 .
  • (C) of Fig. 2 is a cross-sectional view taken along line BB' of (B) of Fig. 2 .
  • (B) of Fig. 2 is a cross-sectional view taken along the line CC' of (C) of Fig. 2 .
  • the channel structure 240 includes a semiconductor channel 241 , a tunneling layer 242 , a charge trapping layer 243 , and a blocking layer 244 , which are sequentially arranged outward along the center of the channel structure 240 .
  • the semiconductor channel 241 may be a semiconductor, that is, a material whose electrical conductivity is between that of a conductor and an insulator at room temperature.
  • the barrier layer 244 may be an oxide, such as Al 2 O 3 , SiO 2 or a stack of Al 2 O 3 -SiO 2 .
  • the charge trapping layer 243 may be a nitride such as Si 3 N 4 .
  • the tunneling layer 242 may be an oxide such as SiO 2 or the like.
  • the semiconductor channel 241 is a solid cylinder, and the tunneling layer 242 , the charge trapping layer 243 , and the blocking layer 244 are all hollow cylinders.
  • the horizontal cross-section of the cylinder can be circular, oval, square or other shapes.
  • the horizontal cross-section of a cylinder may deviate from a perfect circle or ellipse.
  • the stacked structure may include alternately stacked sacrificial layers and insulating layers.
  • a through hole penetrating the stacked structure is provided in the stacked structure, and a channel structure 240 is formed in the through hole.
  • the material of the sacrificial layer in the stacked structure is replaced with a metal material, so as to realize the electrical connection of the gates of each transistor in the three-dimensional memory.
  • insulating layers D0 to D4 and metal layers SGS, WL0, WL1, SGD are alternately stacked.
  • the position of the metal in the metal layers SGS, WL0, WL1 and SGD is the sacrificial layer material.
  • the sacrificial layer material may be silicon nitride, for example.
  • the position where the metal material layer contacts the barrier layer 244 in the CSR can be understood as the gate of the transistor.
  • the position where the metal material layer WL1 contacts the barrier layer 244 can be understood as the gate of the transistor Q2
  • the position where the metal material layer WL1 contacts the barrier layer 244 can be understood as the control gate of the transistor Q2
  • the metal material layer SGD is in contact with the barrier layer 244
  • the position of can be understood as the gate of transistor Q3.
  • FIG. 3 is an enlarged schematic view of a partial region of (A) in FIG. 2 .
  • the sacrificial layer in the laminated structure needs to be removed first.
  • the sacrificial layer may be removed by an etching process.
  • one or more sacrificial layers may be over-etched in the horizontal direction, which affects the performance parameters of the transistor, such as erasing and writing operation voltage, erasing and writing life (endurance), data retention time (retention), etc., even destroying the charge trapping layer makes the memory cell fail, that is, the transistor does not have the ability to store data.
  • the etching of the sacrificial layer far from the substrate is faster, and the etching of the sacrificial layer close to the substrate is slower.
  • the sacrificial layer at the position of the metal layer 320 close to the substrate is insufficiently etched, and there is a sacrificial layer material between the metal layer 320 and the channel structure 240 .
  • the distance between the metal layer 320 and the channel structure 240 is relatively long, which affects the performance parameters of the transistor, the erase and write operation voltage, threshold voltage, etc., and may even fail to effectively control the on and off of the transistor, resulting in failure of the memory cell.
  • the height of the channel structure 240 increases.
  • the semiconductor channel 241 is made of a single crystal semiconductor material, the distance from the substrate 210 is farther, the greater the number of defects per unit volume of the semiconductor channel 241 is. Therefore, the increase in the number of layers of the stacked structure reduces the electron mobility of the transistor.
  • the performance of the NAND string is determined by the performance of the transistor with the lowest electron mobility in the NAND string. Therefore, as the number of layers of the stacked structure increases, the performance of the three-dimensional memory decreases.
  • an embodiment of the present application provides a three-dimensional memory.
  • FIG. 4 is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present application.
  • the three-dimensional memory includes a substrate 210 , a stacked structure, a channel structure 440 and a storage structure 450 .
  • a stacked structure may be located on the substrate 210 , and the stacked structure includes alternately stacked conductor layers 430 and dielectric layers 420 .
  • the stacked structure includes a plurality of conductor layers 430 and a plurality of dielectric layers 420 .
  • the three-dimensional memory may also not include the substrate 210 .
  • the three-dimensional memory can be fabricated on the substrate 210, after which the substrate can be removed.
  • the channel structure 440 runs through the stacked structure.
  • the conductor layer 430 includes the conductive material.
  • the storage structure 450 is formed in the conductor layer, on the surface of the channel structure, and between the channel structure 440 and the conductive material.
  • Each storage structure 450 and the channel structure 440 at the corresponding position of the storage structure 450 constitute a transistor.
  • the conductive material is connected to the storage structure, and the signal of the conductive material is the signal of the control gate CG of the transistor.
  • Each storage structure 450 is located on the surface of the channel structure 440 and is in contact with the conductive material in the conductor layer 430 corresponding to the storage structure 450 .
  • the storage structure is located on the conductor layer and formed on the surface of the channel structure, the storage structure is formed after the sacrificial layer is removed. Therefore, the memory structures 450 at different conductor layers are not in contact. In other words, on the surface of the channel structure 440, the storage structures 450 located in different conductor layers are not in contact.
  • the storage structures 450 in the upper and lower conductor layers are on the surface of the channel structure 440 and can be separated by the dielectric layer 420, as shown in FIG. 4 .
  • the storage structure 450 includes a tunneling layer 732 , a charge trapping layer 733 , and a blocking layer 734 .
  • the storage structures 450 in the upper and lower conductor layers are separated by a protection structure (ie, the protection layer 710 shown in FIG. 16 ) on the surface of the channel structure 440 .
  • the conductive layer 430 in the stacked structure is obtained by replacing the sacrificial material in the sacrificial layer in the stacked structure with a conductor material.
  • the sacrificial material in the sacrificial layer is removed, the storage structure 450 is formed on the surface of the channel structure 440 , and then the conductive material is deposited to form the conductive layer 430 .
  • the sacrificial layer is removed, the influence of excessive etching or insufficient etching on the performance of the three-dimensional memory due to process errors is avoided, and the performance of the three-dimensional memory is improved.
  • the material of the dielectric layer 420 may be an insulating material such as silicon oxide.
  • the material of the sacrificial layer may be silicon nitride.
  • the material of the conductive layer may be metal, or other conductive materials (such as graphene or polymer compounds, etc.).
  • Channel structure 440 may be a semiconductor material.
  • it may be a polycrystalline semiconductor or a single crystal semiconductor.
  • the channel structure 440 adopts a single crystal semiconductor, and the channel structure 440 has fewer defects, which can improve the performance of the three-dimensional memory.
  • the three-dimensional memory may further include a protective layer on the surface of the channel structure. Before forming the storage structure, the protective layer at the position where the conductive layer on the surface of the channel structure 440 is located may be removed, thereby forming a plurality of protective structures.
  • the three-dimensional memory may further include a protection structure, the protection structure is in the dielectric layer 420 , and the protection structure is located on the surface of the channel structure 440 . That is, the electrolyte material in the dielectric layer where the protective structure is located is in contact.
  • the memory hole can be formed in the memory hole 440.
  • the sidewalls form a protective layer.
  • the protective layer When removing the sacrificial material, the protective layer may be etched in whole or in part due to process deviation. If the protective layer is used as part of the storage structure, such as a tunneling layer or as part of the tunneling layer, the protective layer after the sacrificial material is removed. Thickness affects the performance parameters of the transistor.
  • the protective layer at the location of the surface sacrificial layer of the channel structure 440 may be removed.
  • the protective layer is divided into a plurality of protective structures.
  • the protection structures correspond to the dielectric layers 420 one-to-one.
  • Each protection structure is located on the surface of the channel structure 440 and is in contact with the dielectric layer 420 corresponding to the protection structure.
  • the protective layer whose surface of the channel structure 440 is located at the removed sacrificial layer By removing the protective layer whose surface of the channel structure 440 is located at the removed sacrificial layer, the influence of the process deviation of the etching process on the performance parameters of the transistor can be avoided.
  • the memory structure In each transistor of the 3D memory, the memory structure is located between the gate and the channel structure 440 .
  • the memory structure has two stable states, so that the transistor can be in both on and off states when equal gate voltages are provided. Data is stored by adjusting the two stable states.
  • the storage structure may be a charge trapping structure ONO including a tunneling layer, a charge trapping layer and a blocking layer.
  • the memory structure may also be a ferroelectric memory structure or the like. This embodiment of the present application does not limit this.
  • the material of the channel structure 440 may be a single crystal semiconductor.
  • the material of the channel structure 440 is single crystal silicon.
  • the material of the protective layer can be an amorphous semiconductor, such as amorphous silicon.
  • the hardness of amorphous silicon is significantly lower than that of crystalline silicon, and its chemical properties are more active than that of crystalline silicon, so the single crystal silicon of the channel structure 440 can be used as an etch stop layer.
  • an etchant with a lower etching rate for the silicon oxide dielectric layer can be selected.
  • amorphous silicon as the protective layer can reduce the difficulty of the etching process.
  • a groove may be formed on the surface of the channel structure 440 where the sacrificial layer was removed.
  • the memory structure 450 is formed in the groove, and then a conductive material is deposited to replace the sacrificial layer to form the conductive layer 430 .
  • each conductive layer 430 the surface of the channel structure 440 includes a groove, and the storage structure corresponding to the conductive layer 430 is located in the groove.
  • the height of the channel structure 440 increases.
  • the semiconductor channel 241 is made of a single crystal semiconductor material, the farther the distance from the substrate 210 is, that is, the higher the growth height of the single crystal silicon, the greater the number of defects per unit volume of the channel structure 440 .
  • the number of defects can be reduced, thereby reducing the influence of defects on the performance of the three-dimensional memory.
  • the material of the channel structure 440 may be single crystal silicon.
  • the crystal structure of single-crystal silicon is a face-centered cubic structure. As shown in FIG. 5 , Si atoms are located at the face centers of the 6 faces of the cube and the 8 vertices of the cube.
  • the four points A, B, C, and D are four Si atoms, which are located at the four vertices of the cube.
  • A, B, C are located on the three vertices of the same side of the cube
  • AB is one side of the cube
  • BC is the other side of the cube
  • AD is the body diagonal of the cube.
  • the direction of the line along the side length of the face-centered cube (for example, along the side length AB) is the lattice direction "001"
  • the direction of the line along the diagonal of one face of the face-centered cube (for example, along the line AC) is the lattice direction "110”
  • the direction along the straight line (for example, along the straight line AD) of the diagonal of the face-centered cube is the lattice direction "111”.
  • the lattice direction may also be referred to as the crystallographic orientation.
  • Single crystal silicon can be grown along the lattice direction "001", "110" or "111".
  • the channel structure adopts single crystal silicon with a single crystal lattice direction of "001" along the direction of the channel structure away from the substrate.
  • the single crystal silicon with the lattice direction of "110" grows slowly, but has fewer defects, so that better charge mobility can be obtained and the performance of the three-dimensional memory can be improved.
  • Single crystal silicon with a lattice direction of "001" grows faster.
  • the number of defects can be reduced.
  • the height of the channel structure 440 can be increased while meeting the mobility requirements for the channel structure.
  • the time required for the growth of single crystal silicon is normal.
  • the channel structure 440 adopts single crystal silicon with a lattice direction of "001", which can obtain a faster growth rate of single crystal silicon, shorten the process time for preparing the three-dimensional memory, and reduce the manufacturing cost.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present application.
  • one or more metal layers under the stacked structure may be formed on the substrate 201.
  • the metal layer may include patterned metal so that various circuits may be formed on the substrate 201 .
  • a metal layer for transmitting a power signal, a control signal of a three-dimensional memory, or the like can be formed.
  • circuits can also be formed on other chips and then bonded with the three-dimensional memory for signal transmission. Specifically, reference may be made to the description of FIG. 20 .
  • the material of the substrate 210 may be semiconductor materials such as silicon (Si), germanium (Ge), and gallium arsenide.
  • the materials of the plurality of metal layers may be the same or different.
  • the material of the substrate 210 is silicon.
  • the stacked structure includes a plurality of sacrificial (SAC) layers and a plurality of dielectric layers which are alternately stacked. As shown in FIG. 7 , the plurality of sacrificial layers are SAC0, SAC1, SAC2, and SAC3, respectively. The plurality of dielectric layers are respectively D0, D1, D2, D3, and D4.
  • SAC sacrificial
  • the sacrificial material in the sacrificial layer will be replaced by a conductive material in a subsequent process to form gate signal transmission lines of the respective transistors, such as word lines WL0, WL1 and the like.
  • the sacrificial material may be, for example, silicon nitride.
  • the dielectric layer is used for insulation between word lines.
  • the material of the dielectric layer may be an insulator such as silicon oxide (SiO 2 ).
  • the stacked structure may be formed by a deposition process.
  • a chemical vapor deposition process can be used to create the stacked structure.
  • the chemical vapor deposition (chemical vapor deposition) process introduces a gaseous reactant containing elements constituting a thin film into a reaction chamber, and a chemical reaction occurs on the surface of the wafer, thereby generating the desired solid film and depositing it on the surface.
  • the storage holes pass through the sacrificial material in the sacrificial layer.
  • the etching technology is mainly divided into dry etching and wet etching.
  • Dry etching is to expose the surface of the silicon wafer to the plasma generated in the gaseous state.
  • the plasma passes through the window opened in the photoresist and undergoes a physical or chemical reaction (or both) with the silicon wafer, thereby removing the exposed surface. surface material. Dry etching may also be referred to as reactive ion etching (RIE) or photolithography.
  • RIE reactive ion etching
  • Wet etching mainly uses chemical reagents to react with the material to be etched for etching. Wet etching is also used to etch certain layers on silicon wafers or to remove residues from dry etching.
  • the storage holes can be formed by reactive ion etching.
  • Reactive ion etching technology has the characteristics of faster etching in the vertical direction.
  • Storage holes extend vertically through alternating sacrificial and insulating layers. The storage holes may extend down to the substrate 210 .
  • the size of the storage holes may vary from far from the top of the substrate 210 to near the bottom of the substrate 210 .
  • the size of the storage holes may gradually decrease from top to bottom.
  • FIG. 7 shows the structure formed after S502.
  • the protective layer 710 can be formed by atomic layer deposition (ALD) at a temperature of less than 400°C.
  • the thickness of the protective layer 710 may be 5 to 20 angstroms (A).
  • the protective layer 710 may be, for example, amorphous silicon. It should be understood that the thicknesses of the sacrificial layer and the dielectric layer follow industry standards, and the thickness of the protective layer 710 is much smaller than that of the sacrificial layer and the dielectric layer.
  • Atomic layer deposition also known as single atomic layer deposition, is a method in which substances can be deposited on the surface of a substrate layer by layer in the form of a single atomic film. Atomic layer deposition is similar to ordinary chemical deposition. But in the ALD process, the chemical reaction of a new layer of atoms is directly linked to the previous layer, in such a way that only one layer of atoms is deposited per reaction.
  • the process temperature for atomic layer deposition may be less than 400 degrees Celsius (°C).
  • the protective layer 710 on the surface of the substrate 210 is removed by etching.
  • Reactive ion etching technology has the characteristics of faster etching in the vertical direction.
  • the protective layer 710 at the bottom of the storage hole may be removed by hydrogen plasma to expose the surface of the substrate 210 .
  • the storage holes vertically pass through the stacked structure, and the sidewalls of the storage holes cover the protective layer 710 .
  • a selective epitaxial growth (SEG) technique can be used to grow single crystal silicon in the storage hole.
  • Selective epitaxial growth refers to epitaxial growth in a defined area on a substrate.
  • the material of the substrate 210 is silicon, and the substrate 210 can be used as a single crystal seed to grow single crystal silicon in the storage hole. It should be understood that the crystal orientation of the single crystal silicon grown in the memory hole is the same as the crystal orientation of the substrate 210 .
  • the crystallographic direction is the lattice direction.
  • S504 is an optional step. Using a clean single crystal silicon substrate as a single crystal seed for SEG is an efficient way to perform SEG.
  • the single crystal seed of the SEG may also be in other ways, which are not limited in the embodiments of the present application.
  • the lattice direction of the single crystal silicon channel structure 440 may be "110" or "001” or the like.
  • the lattice direction of the single crystal silicon channel structure 440 is "110", the grown single crystal silicon has fewer defects and better charge mobility, so that the performance of the three-dimensional memory can be improved.
  • the lattice direction of the single crystal silicon channel structure 440 is "001", and the growth speed of the single crystal silicon is relatively fast, which can shorten the process time for preparing the three-dimensional memory and reduce the manufacturing cost.
  • a wafer with a lattice direction of “001” may be used as the substrate 210 .
  • Single crystal silicon can be grown in memory holes by various epitaxial growth techniques.
  • the temperature range of the SEG process is 400-1000°C, and the specific temperature selection is related to the grown semiconductor material.
  • atoms such as nitrogen (N) in the dielectric layer may enter the single crystal silicon through diffusion, which affects the performance of the single crystal silicon.
  • the protective layer 710 disposed on the sidewall of the storage hole can prevent atoms in the dielectric layer from diffusing into the single crystal silicon of the storage hole.
  • a pre-cleaning process may be performed on the bottom of the storage hole, that is, the surface of the substrate 210 in the storage hole.
  • FIG. 10 shows the structure after S505 is performed.
  • the protective layer 710 on the surface of the channel structure where the sacrificial material is located is exposed, and the protective layer 710 at the location can be removed.
  • amorphous silicon can be used as an etch stop layer. After that, an etchant having higher corrosiveness to amorphous silicon and lower corrosiveness to monocrystalline silicon is selected, and the protective layer 710 on the surface of the channel structure 440 where the sacrificial layer is located is removed.
  • the channel structure 440 can act as an etch stop layer. That is to say, the etching performance of the etchant on the dielectric layer and single crystal silicon is not strong, so during etching, the material of the sacrificial layer (such as nitride) will be etched away, and the amorphous silicon as the protective layer 710 will be etched away. The sidewall will be over-etched, and finally the etching stops on the surface of the monocrystalline silicon with higher hardness and difficult to etch.
  • the method of stopping the etching through the etch stop layer can be called a self-limited recess process.
  • the etch stop layer may also be referred to as a self-limited recess etch stop layer.
  • the etching rate of the top part far from the substrate is higher than that of the bottom part close to the substrate, so it is necessary to control the etching time to avoid completely removing the protective layer 710 on the sidewalls of single crystal silicon.
  • the selection of the material of the protective layer 710 and the etchant should be such that when removing the protective layer 710 on the surface of the channel structure where the sacrificial layer is located, damage to the dielectric layer structure and the channel structure 440 in the stacked structure can be avoided. That is to say, by using a self-limited recess process, single crystal silicon is used as an etch stop layer, and the silicon oxide layer 731 on the surface of the crystal silicon is removed, so as to avoid damage to the dielectric layer structure and channels in the stacked structure. Destruction of the structure 440, and reduce the difficulty of the process.
  • FIG. 11 shows the structure after S506 is performed.
  • FIG. 12 is a partial enlarged view of the broken line area in FIG. 11 .
  • the sacrificial layer is removed.
  • the protective layer 710 is etched as separate rings surrounding the pillars of the channel structure 440 .
  • pre-cleaning is performed on the surface of the channel structure 440 where the removed sacrificial layer is located.
  • a silicon oxide layer 731 may be grown on the surface of the channel structure 440 where the removed sacrificial layer is located by an oxidation process such as wet oxygen oxidation and dry oxygen oxidation, as shown in FIG. 13 .
  • the material of the protective layer 710 is also silicon
  • growth silicon oxide is also formed on the surface of the protective layer 710 . That is, the silicon oxide layer 731 is located on the surface of the channel structure 440 and the protective layer 710 where the sacrificial layer is located.
  • the oxide layer When the oxide layer is grown on the surface of the channel structure 440, the silicon atoms on the surface of the channel structure 440 undergo chemical reaction to generate silicon oxide, so as to form the oxide layer. Therefore, when the oxide layer is formed, the surface of the channel structure 440 where the sacrificial layer is located, that is, the interface between the single crystal silicon and the silicon oxide, gradually moves toward the center of the channel structure 440 . Because the oxide layer growth has no directionality, in the direction parallel to the substrate surface, the surface of the channel structure 440 moves toward the center of the channel structure 440, and in the direction perpendicular to the substrate surface, the surface of the channel structure 440 moves toward the center of the dielectric layer. move in the direction.
  • Removing the silicon oxide layer 731 on the surface of the channel structure 440 can expose the surface of the channel structure 440 .
  • wet etching can be used. Wet etching has no effect on the crystal lattice of single crystal silicon. Since the etching rate of the wet etching process is not directional, that is, the etching rate for each direction is basically the same. Etching the silicon oxide layer 731 on the surface of the channel structure 440 can also be understood as removing the silicon oxide layer 731 .
  • the oxidation process is a process in which the silicon oxide layer 731 is formed, and all or part of the silicon element in the silicon oxide layer 731 is derived from the single crystal silicon in the channel structure 440 .
  • FIG. 15 is a perspective view
  • FIG. 14 is a cross-sectional view.
  • the width of the groove is generally slightly larger than the width of the sacrificial layer (or the thickness of the sacrificial layer).
  • the material of the dielectric layer can also be silicon oxide.
  • S507b When S507b is performed, part of the surface of the dielectric layer is also removed. In order to avoid destroying the insulating function of the dielectric layer, the time for performing S507b should be controlled so that the silicon oxide on the surface of the single crystal silicon can be removed without affecting the insulating function of the dielectric layer.
  • the number of defects per unit volume of single crystal silicon increases. That is, in a single crystal silicon channel structure, the top (portion away from the substrate) of the channel structure will have more defects than the bottom (portion close to the substrate).
  • the number of defects per unit volume of single crystal silicon increases. That is, in the single crystal silicon channel structure, the number of defects on the surface is greater than that in the interior.
  • the etch rate at the top of the channel structure is greater than the etch rate at the bottom of the channel structure.
  • the oxide layer is grown on the surface of the channel structure 440 where the sacrificial layer is located and the oxide layer is etched to form a groove, which can effectively reduce the number of defects at the memory cell in the vertical channel and reduce the impact of the SEG process on the performance of the memory cell , thereby improving the capacity and performance of 3D memory.
  • the number of sacrificial layers and dielectric layers in the stacked structure can be increased, that is, the number of transistors per unit area can be increased, and the capacity of the three-dimensional memory can be effectively improved.
  • the memory structure may be a ferroelectric memory structure. That is, a three-dimensional ferroelectric memory can be fabricated by the method shown in FIG. 6 .
  • Ferroelectric memory is a non-volatile memory with a special process, which is formed by using artificially synthesized lead zirconium titanium (PZT) or hafnium zirconium oxide (HfZrOx) materials to form memory crystals.
  • PZT lead zirconium titanium
  • HfZrOx hafnium zirconium oxide
  • the central atom moves in the crystal along the direction of the electric field and stops in another low energy state II.
  • a large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field.
  • the polarization charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower. memory.
  • the ferroelectric domain can be reversed under the electric field to form a highly polarized charge, or no inversion can be formed.
  • the low polarization charge determines whether the memory cell is in the "1" or "0" state.
  • the inversion of the ferroelectric domain does not require a high electric field, and only the general working voltage can change the state of the memory cell to be in "1" or "0”; it also does not require a charge pump to generate high-voltage data erasure, so there is no erasure Write delay phenomenon. This feature enables the ferroelectric memory to continue to save data after power failure, with fast writing speed and unlimited write life, and it is not easy to write bad.
  • the storage structure may also be a charge trapping structure ONO or the like.
  • the charge trapping structure ONO includes a tunneling layer 732 , a charge trapping layer 733 , and a blocking layer 734 , as shown in FIG. 16 .
  • a tunnel layer 732, a charge trapping layer 733, and a blocking layer 734 are sequentially deposited and formed in the groove.
  • the charge trapping structure can be formed by chemical vapor deposition or atomic layer deposition.
  • the charge trapping structure includes a tunneling layer 732 , a charge trapping layer 733 , and a blocking layer 734 .
  • Atomic layer deposition is a method that can deposit substances on the surface of a substrate layer by layer in the form of a single atomic film. Atomic layer deposition is similar to ordinary chemical deposition. But in atomic layer deposition, the chemical reaction of a new layer of atoms is directly linked to the previous layer, in such a way that only one layer of atoms is deposited at each reaction.
  • the thickness of the charge trapping structure can be less than 50A, so that the erasing voltage can be reduced to 5 volts (V), the memory cell access speed can be increased, the erasing and writing life can be improved, and the data retention time can be reduced.
  • materials of the tunneling layer, the charge trapping layer, and the blocking layer will also grow on the surface of the dielectric layer. Since the materials of the tunneling layer, charge trapping layer, and blocking layer are all insulators, the materials of the tunneling layer, charge trapping layer, and blocking layer on the surface of the dielectric layer can also be understood as a part of the dielectric layer, which is used to replace the metal layer of the sacrificial layer. insulation between.
  • the conductive layer 430 may be formed using a standard 3D NAND replace gate process.
  • the conductive layer 430 may be formed by chemical vapor deposition or atomic layer deposition.
  • the conductive material may be a metal such as nickel (Ni), titanium Ti, cobalt (Co), or tungsten (W), or the like.
  • FIG. 17 The structure after performing S509 is shown in FIG. 17 .
  • FIG. 18 is a partial enlarged view of the dotted line area in FIG. 17 .
  • Fig. 19 is a plan view of the structure shown in Fig. 18, and Fig. 18 is a cross-sectional view of the structure shown in Fig. 19 taken along line AA'.
  • the sacrificial layer SAC0 is replaced with a selection line SGS
  • SAC1 is replaced with a word line WL0
  • SAC2 is replaced with a word line WL1
  • SAC3 is replaced with a selection line SGD.
  • Figure 19 shows one possible pattern for storage holes.
  • the memory holes shown in Figure 19 are staggered, but this is not the only possible pattern.
  • the memory holes need not be staggered as shown in FIG. 19 .
  • the storage hole shown in FIG. 19 has a circular cross section in the horizontal direction.
  • the storage hole may also have other shapes, which are not limited in this embodiment of the present application.
  • the size of the memory holes may be different in different layers. For example, layers close to substrate 210 may have smaller storage holes.
  • the substrate may be removed to reduce the thickness of the three-dimensional memory.
  • FIG. 20 is a schematic structural diagram of a three-dimensional memory and a control circuit provided by an embodiment of the present application.
  • Three-dimensional memory may be formed on the substrate of the chip to form a three-dimensional memory chip 1901 .
  • Circuitry may be formed on the substrate of the chip to form circuit chip 1902 .
  • the three-dimensional memory chip 1901 and the circuit chip 1902 may be bonded.
  • a face-to-face bonding process can be used to form a bonding interface between the three-dimensional memory chip 1901 and the upper surface of the circuit chip 1902, so that the three-dimensional memory chip 1901 and the upper surface of the circuit chip 1902 are electrically connected, and the two The wafers are stacked together, and signals are transmitted through the circuit chip 1902 to realize the control of the three-dimensional memory chip 1901 .
  • the substrate of the three-dimensional memory chip 1901 may use single crystal silicon with a single crystal lattice direction of "001".
  • the substrate of the circuit chip 1902 may be single-crystal silicon with a single-crystal lattice direction of "110".
  • FIG. 21 is a schematic flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present application.
  • a stacked structure is formed including alternately stacked sacrificial layers and dielectric layers.
  • a stacked structure can be formed on the substrate.
  • a channel structure is formed through the stacked structure and through the sacrificial material in the sacrificial layer.
  • the sacrificial material in the sacrificial layer is removed.
  • the sacrificial layer includes a sacrificial material, and the sacrificial material may be silicon nitride or the like.
  • the sacrificial layer may also include or not include other materials, which are not limited in this embodiment of the present application.
  • a storage structure is formed on the surface of the channel structure where the sacrificial material is removed.
  • a conductive material is deposited in place of the removed sacrificial material.
  • the channel structure is a single crystal semiconductor material.
  • a storage hole may be formed, the storage hole passing through the stacked structure and passing through the sacrificial material.
  • a protective layer is formed on the sidewalls of the storage holes.
  • a single crystal semiconductor material is filled in the storage hole to form the channel structure.
  • elements such as nitrogen
  • the sacrificial material of the stacked structure may diffuse into the single crystal semiconductor of the channel structure, thereby affecting the performance of the three-dimensional memory.
  • a protective layer on the surface of the channel structure, the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated.
  • the protective layer at the position of the sacrificial material on the surface of the channel structure may be removed, so that the position of each sacrificial layer on the surface of the channel structure is exposed.
  • the protective layer is divided into a plurality of protective structures, and the protective structures may correspond one-to-one with the dielectric layers in the stacked structure.
  • removing the protective layer whose surface of the channel structure is located at the removed sacrificial layer can avoid the influence of the process deviation of the etching process on the performance parameters of the transistor.
  • the semiconductor material filled in the storage hole may be single crystal silicon, and the material of the protective layer may be amorphous silicon.
  • amorphous silicon is significantly lower than that of crystalline silicon, and its chemical properties are more active than that of crystalline silicon. Therefore, single-crystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.
  • a groove is formed at each position of the removed sacrificial material on the surface of the channel structure.
  • the number of defects in the single crystal silicon channel structure can be reduced, thereby reducing the effect of defects on the performance of the three-dimensional memory.
  • oxides may be formed at each of the sacrificial material removal locations on the surface of the channel structure. Afterwards, the oxide can be removed to form the grooves.
  • the material of the channel structure is single crystal silicon with a single crystal lattice direction of “001” along the direction of the channel structure away from the substrate.
  • Single crystal silicon with a lattice direction of "001" grows faster.
  • the number of defects can be reduced.
  • the height of the channel structure 440 can be increased while meeting the mobility requirements for the channel structure.
  • the time required for the growth of single crystal silicon is normal.
  • the channel structure 440 adopts single crystal silicon with a lattice direction of "001", which can obtain a faster growth rate of single crystal silicon, shorten the process time for preparing the three-dimensional memory, and reduce the manufacturing cost.
  • a tunneling layer, a charge trapping layer and a blocking layer stacked in the storage structure are sequentially formed.
  • Embodiments of the present application provide an electronic device, including the aforementioned three-dimensional memory.
  • “at least one” refers to one or more, and “multiple” refers to two or more.
  • “And/or”, which describes the association relationship of the associated objects means that there can be three kinds of relationships, for example, A and/or B, which can indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • “At least one of the following” and similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple.

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Abstract

本申请提供了一种三维存储器和三维存储器的制备方法。三维存储器包括层叠结构、通道结构、存储结构。层叠结构包括交替堆叠的导体层和介质层。通道结构贯穿层叠结构。所述导体层中包括导电材料。所述存储结构在所述导体层中，形成于所述通道结构的表面，且处于所述通道结构和所述导电材料之间。三维存储器的存储结构位于导体层中，并且形成于通道结构的表面，从而制造三维存储器时，能够避免去除牺牲材料时由于工艺偏差对三维存储器的性能产生的影响。

Description

三维存储器及三维存储器的制备方法 技术领域
本申请涉及半导体器件领域，尤其涉及三维存储器及三维存储器的制备方法。
背景技术
三维(3 dimension，3D)存储器具有较高存储容量，较低的生产成本，受到了广泛的关注。
三维存储器包括在衬底上形成的层叠结构、贯穿层叠结构的通道结构、以及位于通道结构的表面的存储层。层叠结构包括交替的多个导体层和多个介质层。层叠结构中的每个导体层中的导电材料是替换牺牲材料得到的。在替换牺牲材料的过程中，对牺牲材料的刻蚀可能存在工艺偏差，导致对于一个或多个导体层，在水平方向存在对牺牲材料过刻蚀或刻蚀不足的情况，影响晶体管的性能参数。过刻蚀甚至可能破坏位于通道结构的表面的存储结构，使得该导体层对应的晶体管不具有存储数据的能力，即导致存储单元失效。
发明内容
本申请提供一种三维存储器，能够提高存储器的可靠性。
第一方面，提供一种三维存储器，包括层叠结构、通道结构、存储结构。所述层叠结构包括交替堆叠的导体层和介质层；所述通道结构贯穿所述层叠结构。所述导体层中包括导电材料。所述存储结构在所述导体层中，形成于所述通道结构的表面，且处于所述通道结构和所述导电材料之间。
三维存储器的存储结构位于导体层中，并且形成于通道结构的表面，从而制造三维存储器时，避免了去除牺牲材料过程中，由于工艺误差，存在刻蚀过量或刻蚀不足而对三维存储器的性能的影响，提高三维存储器的性能。
结合第一方面，在一些可能的实现方式中，所述通道结构包括单晶半导体材料。
单晶半导体材料的电子迁移率较高，通道结构采用单晶半导体材料，能够提高三维存储器的性能。
结合第一方面，在一些可能的实现方式中，所述介质层包括保护结构，保护结构位于所述通道结构的表面。
可以通过选择性外延生长(selective epitaxial growth，SEG)技术形成通道结构。在通道结构形成的过程中，层叠结构牺牲层中的元素(如氮)可能扩散至通道结构的单晶半导体中，影响三维存储器的性能。
通过在通道结构的表面设置保护层，可以降低甚至消除层叠结构牺牲层中的元素的扩散。在形成存储结构之前，去除通道结构的表面位于去除的牺牲层处的保护层，可以避免刻蚀过程的工艺偏差对晶体管的性能参数的影响。
结合第一方面，在一些可能的实现方式中，所述通道结构的材料为单晶硅；每个保护 结构的材料为非晶硅。
非晶硅(amorphous silicon)硬度明显低于晶体硅，化学性质比晶体硅活泼，因此可以将单晶硅作为刻蚀停止层，减小刻蚀工艺的难度。
结合第一方面，在一些可能的实现方式中，在所述导电层，所述通道结构的表面包括凹槽，所述存储结构位于所述凹槽中。
通过在通道结构表面设置凹槽，并将存储结构设置在凹槽中，可以减少单晶硅通道结构中的缺陷数量，从而降低缺陷对三维存储器的性能的影响。
结合第一方面，在一些可能的实现方式中，所述通道结构的材料为沿所述通道结构贯穿所述层叠结构的单晶晶格方向为“001”单晶硅。
晶格方向为“001”的单晶硅生长速度较快。通过在通道结构表面导电层所在的位置设置凹槽，可以减少缺陷数量。从而，在满足对通道结构的迁移率要求的情况下，通道结构的高度可以增加。随着通道结构的高度增加，单晶硅生长需要的时间正常。通道结构采用晶格方向为“001”的单晶硅，可以获得较快的单晶硅生长速度，缩短制备三维存储器的工艺时间，降低制造成本。
结合第一方面，在一些可能的实现方式中，所述存储结构包括沿远离所述通道结构的方向依次设置的隧穿层、电荷俘获层和阻挡层。
第二方面，提供一种三维存储器的制备方法，包括：在衬底上形成层叠结构，所述层叠结构包括交替堆叠的牺牲层和介质层；形成通道结构，所述通道结构贯穿所述层叠结构，并穿过所述牺牲层中的牺牲材料；去除所述牺牲材料；在所述通道结构表面的去除牺牲材料的位置，形成存储结构；沉积导电材料代替去除的所述牺牲材料。
存储结构在去除层叠结构中的牺牲材料之后形成，避免了去除牺牲层时，由于工艺误差，存在刻蚀过量或刻蚀不足而对三维存储器的性能的影响，提高三维存储器的性能。
结合第二方面，在一些可能的实现方式中，所述通道结构为单晶半导体材料。
结合第二方面，在一些可能的实现方式中，所述形成通道结构，包括：形成存储孔，所述存储孔贯穿所述层叠结构，并穿过所述牺牲材料；在形成有所述保护层的所述存储孔的侧壁形成保护层；在所述存储孔中生长单晶半导体材料，以形成所述通道结构。
在通道结构形成的过程中，层叠结构牺牲材料中的元素(如氮)可能扩散至通道结构的单晶半导体中，影响三维存储器的性能。通过在通道结构的表面设置保护层，可以降低甚至消除层叠结构牺牲层中的元素的扩散，从而提高三维存储器的性能。
结合第二方面，在一些可能的实现方式中，所述方法还包括：去除所述通道结构表面的每个牺牲层的位置的保护层。
在形成存储结构之前，去除通道结构的表面位于去除的牺牲层处的保护层，可以避免刻蚀过程的工艺偏差对晶体管的性能参数的影响。
结合第二方面，在一些可能的实现方式中，所述通道结构的材料为单晶硅；每个保护结构的材料为非晶硅。
结合第二方面，在一些可能的实现方式中，去除所述通道结构表面的牺牲材料的位置的保护层，包括：采用刻蚀工艺以去除所述通道结构表面的牺牲材料的位置的保护层，所述存储孔中生长的半导体材料为刻蚀停止层。
在去除牺牲材料时，通过将存储孔中生长的半导体材料(即通道结构的材料)作为刻 蚀停止层，可以降低对刻蚀工艺的时间精度要求，降低刻蚀的工艺难度。
结合第二方面，在一些可能的实现方式中，所述存储孔中生长的半导体材料为单晶硅；所述保护层的材料为非晶硅。
非晶硅(amorphous silicon)硬度明显低于晶体硅，化学性质比晶体硅活泼，因此可以将单晶硅作为刻蚀停止层，减小刻蚀工艺的难度。
结合第二方面，在一些可能的实现方式中，所述通道结构包括单晶半导体材料。所述方法还包括：在所述通道结构表面的去除牺牲材料的位置形成凹槽。在所述通道结构表面的所述去除牺牲材料的位置，形成存储结构，包括：在凹槽中，形成所述存储结构。
通过在通道结构表面导电层所在的位置(即去除的牺牲材料的位置)设置凹槽，可以减少单晶硅通道结构中的缺陷数量，从而降低缺陷对三维存储器的性能的影响。
结合第二方面，在一些可能的实现方式中，所述在所述通道结构表面的每个去除牺牲层的位置形成凹槽包括：在所述通道结构表面的去除牺牲材料的位置形成氧化物；去除所述氧化物以形成所述凹槽。
通道结构通常为单晶硅或多晶硅，介质层的材料通常为氧化硅。如果采用刻蚀通道结构的方式，可能对介质层的结构产生影响。
通过在所述通道结构表面的每个去除牺牲层的位置形成氧化物并去除该氧化物的方式形成凹槽，可以避免形成凹槽而影响介质层的结构。
结合第二方面，在一些可能的实现方式中，所述通道结构的材料为沿所述通道结构远离所述衬底的方向的单晶晶格方向为“001”单晶硅。
晶格方向为“001”的单晶硅生长速度较快。通过在通道结构表面导电层所在的位置设置凹槽，可以减少缺陷数量。从而，在满足对通道结构的迁移率要求的情况下，通道结构的高度可以增加。随着通道结构的高度增加，单晶硅生长需要的时间正常。通道结构采用晶格方向为“001”的单晶硅，可以获得较快的单晶硅生长速度，缩短制备三维存储器的工艺时间，降低制造成本。
结合第二方面，在一些可能的实现方式中，所述在所述通道结构表面的去除所述牺牲层的位置，形成存储结构，包括：在所述通道结构表面的去除所述牺牲层的位置，依次形成所述存储结构中堆叠的隧穿层、电荷俘获层和阻挡层。
第三方面，提供一种电子设备，包括第一方面所述的三维存储器。
附图说明
图1是一种NAND串的电路结构示意图。
图2是一种三维存储器的示意性结构图。
图3是一种三维存储器的部分区域的示意性结构图。
图4是本申请实施例提供的一种三维存储器的示意性结构图。
图5是单晶硅的晶体结构的示意图。
图6是本申请实施例提供的一种三维存储器的制备方法的示意性流程图。
图7至图19是本申请实施例提供的一种三维存储器的制备过程中的结构示意图。
图20是本申请实施例提供的一种三维存储器及控制电路的示意性结构图。
图21是本申请实施例提供的一种三维存储器的制备方法的示意性流程图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本文所使用的术语“在……之上”、“在……上方”、“至”、“在……之间”、和“在……上”等可指一层相对于其他层的相对位置。一层在另一层“之上”、“上方”或“上”，或者，连接或键合“至”另一层或者与另一层“接触”可为直接与其他层接触或可具有一个或多个居问层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
与传统的二维(2 dimension，2D)存储器相比，三维(3 dimension，3D)存储器具有较高存储容量，较低的生产成本，受到了广泛的关注。
图1是一种三维与非串的示意性电路拓扑结构图。图2是一种三维存储器的示意性结构图。
与非，是一种运算方式，当且仅当所有操作数的值都为1时，运算结果为零；否则，运算结果为1。与非运算的布尔运算符(Boolean operator)为NAND。与非串也可以称为NAND串。三维存储器可以包括多个NAND串。
每个NAND串可以包括多个串联布置的晶体管，以4个串联的晶体管Q0、Q1、Q2、Q3为例进行说明。
NAND串包括具有存储能力的晶体管。每个具有存储能力的晶体管具有控制栅极(control gate，CG)和电荷存储区(charge storage region，CSR)。CSR例如可以包括电荷俘获层(charge trapping layer)。例如，晶体管Q1和Q2具有存储能力。晶体管Q1的选择栅极连接至字线(word line，WL)0，晶体管Q2的选择栅极连接至WL1。每个晶体管可以理解为一个存储单元。
NAND串中也可以包括其他晶体管。例如，可以通过选择线SGS连接晶体管Q3的栅极以控制晶体管Q3的导通或截止，从而控制NAND串是否与位线(bit line，BL)111连接。还可以通过选择线SGD连接晶体管Q0的栅极以控制晶体管Q0的导通或截止，从而控制NAND串是否与公共源极线128连接。晶体管Q0和Q3也可以包括电荷存储区，但是，在使用过程中，不在晶体管Q0和Q3的电荷存储区存储电荷。
对于具有存储能力的晶体管，电荷存储区可以利用非导电介电材料以非易失性方式存储电荷。电荷存储区可以是被夹在控制栅极和晶体管的沟道之间的由氧化物、氮化物层、氧化物(oxide–nitride-oxide，ONO)形成的三层电介质。ONO例如可以是由氧化硅(SiO 2)-氮化硅(Si 3N 4)-氧化硅，或者，ONO也可以是氧化铝(Al 2O 3)-Si 3N 4-SiO 2等。
如图2中的(C)所示，电荷俘获层243被夹持在阻挡层244和隧穿层242之间。
从控制栅极到通道结构240中心的方向，第一层氧化物是阻挡层244，用于阻挡从电荷俘获层243到控制栅极或从控制栅极到电荷俘获层243的电子隧穿。阻挡层244可以是电介质的堆叠，例如在一个实施例中，阻挡层可以是电介质Al 2O 3-SiO 2的堆叠。
从控制栅极到通道结构240中心的方向，第二层氧化物是隧穿层242，在编程期间电子可以通过该电介质从沟道隧穿至电荷俘获层243。电子通过隧穿层242从沟道隧穿至电荷俘获层243，也可以称为电荷俘获层243的电子注入。
通过将来自通道结构240的电子注入到电荷俘获层243的氮化物中，可以对具有存储能力的晶体管进行编程，在电荷俘获层243中电子被捕获并存储在有限的区域中。
电荷俘获层243存储的电荷能够改变晶体管的阈值电压。例如，电荷俘获层243的未注入电子时晶体管的阈值电压为VT1，在电荷俘获层243的中注入电子后晶体管的阈值电压为VT2。当晶体管的控制栅极的电压在VT1与VT2之间，晶体管的导通与截止状态可以分别表示数字逻辑中的“1”和“0”，从而实现对数据的存储。
可以通过向氮化物形成的电荷俘获层243的中注入空穴，通过注入空穴与电子复合，以实现对晶体管中存储的数据的擦除。也可以通过从氮化物提取电子，例如通过施加电场使电子从氮化物形成的电荷俘获层243的隧穿到沟道来擦除晶体管中存储的数据。当然，也可以同时采用这两种机制进行数据的擦除。
如图2中的(A)所示，衬底210上设置有绝缘膜220，在绝缘膜220上设置有金属层，金属层中设置有公共源极线SL0。
在金属层上，设置有层叠结构。层叠结构包括交替堆叠的金属层和绝缘层。在层叠结构中，设置有通道结构240。图2中的(A)中所示的NAND串为直线形，两个通道结构240分别对应NAND串C0和NAND串C1。
图2中的(B)是图2中的(A)的局部区域放大的示意图。图2中的(C)是图2中的(B)的沿直线BB’的剖面图。图2中的(B)是图2中的(C)的沿直线CC’的剖面图。
通道结构240包括沿通道结构240中心向外依次排列的半导体通道241、隧穿层242、电荷俘获层243、阻挡层244。
半导体通道241可以是半导体，即指常温下导电性能介于导体与绝缘体之间的材料。阻挡层244可以氧化物，如Al 2O 3、SiO 2或者Al 2O 3-SiO 2的堆叠。电荷俘获层243可以是氮化物，如Si 3N 4。隧穿层242可以是氧化物，如SiO 2等。
应当理解，半导体通道241为实心柱体，隧穿层242、电荷俘获层243、阻挡层244均为空心柱体。柱体的水平横截面可以是圆形、椭圆形、方形或其他形状。柱体的水平横截面可能会偏离完美的圆形或椭圆形。
在三维存储器制备过程中，层叠结构可以包括交替堆叠的牺牲层和绝缘层。在层叠结构中设置贯穿堆叠结构的通孔，并在通孔中形成通道结构240。之后，将层叠结构中的牺牲层材料替换为金属材料，从而实现三维存储器中各个晶体管的栅极的电连接。如图2中的(A)所示，在形成的三维存储器中，绝缘层D0至D4与金属层SGS、WL0、WL1、SGD交替堆叠。在金属材料替换牺牲层材料之前，金属层SGS、WL0、WL1、SGD中的金属所在的位置为牺牲层材料。牺牲层材料例如可以是氮化硅。
如图2中的(B)所示，金属材料层与CSR中的阻挡层244接触的位置，可以理解为晶体管的栅极。金属材料层WL1与阻挡层244接触的位置可以理解为晶体管Q2的栅极，金属材料层WL1与阻挡层244接触的位置可以理解为晶体管Q2的控制栅极，金属材料层SGD与阻挡层244接触的位置可以理解为晶体管Q3的栅极。
图3是是图2中的(A)的局部区域放大的示意图。
将层叠结构中的牺牲层材料替换为金属材料的过程中，需要先去除层叠结构中的牺牲层。可以采用刻蚀工艺，去除牺牲层。
在刻蚀过程中，由于工艺偏差，可能导致对于一个或多个牺牲层，在水平方向存在过刻蚀，影响晶体管的性能参数，如擦写操作电压、擦写寿命(endurance)、数据保存时间(retention)等，甚至破坏电荷俘获层使得存储单元失效，即导致晶体管不具有存储数据 的能力。
一般情况下，对于远离衬底的牺牲层的刻蚀较快，对于靠近衬底的牺牲层的刻蚀较慢。
对远离衬底的金属层310所在位置的牺牲层刻蚀过量，导致金属层310延伸至通道结构240内部，导致存储单元失效。
对靠近衬底的金属层320所在位置的牺牲层刻蚀不足，金属层320与通道结构240之间存在牺牲层材料。金属层320与通道结构240的距离较远，影响晶体管的性能参数，擦写操作电压、阈值电压等，甚至可能无法有效控制晶体管的开通和关断，导致存储单元失效。
另外，随着层叠结构的层数增多，通道结构240的高度增加。当半导体通道241采用单晶半导体材料时，与衬底210的距离远离，半导体通道241单位体积中的缺陷(defect)数量越多。因此，层叠结构的层数增多使得晶体管的电子迁移率降低。
而根据三维存储器的结构，NAND串的性能是由NAND串中电子迁移率最低的晶体管的性能决定的。因此，随着层叠结构的层数增多，三维存储器的性能降低。
为了解决上述问题，本申请实施例提供了一种三维存储器。
图4是本申请实施例提供的一种三维存储器的示意性结构图。
三维存储器包括衬底210、层叠结构、通道结构440和存储结构450。
层叠结构可以位于衬底210上，层叠结构包括交替堆叠的导体层430和介质层420。一般情况下，层叠结构包括多个导体层430和多个介质层420。
在一些实施例中，三维存储器也可以不包括衬底210。可以在衬底210上制备三维存储器，之后可以将衬底去除。
通道结构440贯穿层叠结构。
所述导体层430中包括所述导电材料。
存储结构450在所述导体层中，形成于所述通道结构的表面，且处于所述通道结构440和所述导电材料之间。
每个存储结构450与该存储结构450对应位置的通道结构440构成一个晶体管。导电材料连接存储结构，导电材料的信号即为该晶体管的控制栅极CG的信号。
每个存储结构450位于通道结构440的表面，并与该存储结构450对应的导体层430中的导电材料接触。
因为存储结构位于导体层，且在通道结构的表面形成，所以存储结构是在去除牺牲层之后形成。因此，位于不同导体层的存储结构450不接触。或者说，在通道结构440的表面，位于不同导体层的存储结构450不接触。
在一个NAND串中，上下两个导体层中的存储结构450在通道结构440的表面，可以被介质层420分隔开，如图4所示。
或者，如图16所示，存储结构450包括隧穿层732、电荷俘获层733、阻挡层734。上下两个导体层中的存储结构450在通道结构440的表面被保护结构(即图16所示的保护层710)分隔。
层叠结构中的导电层430是以导体材料替换层叠结构中的牺牲层中的牺牲材料得到的。在形成贯穿层叠结构的通道结构440之后，去除牺牲层中的牺牲材料，在通道结构440的表面形成存储结构450，之后淀积导电材料以形成导电层430。避免了去除牺牲层 时，由于工艺误差，存在刻蚀过量或刻蚀不足对三维存储器的性能的影响，提高三维存储器的性能。
介质层420的材料可以是氧化硅等绝缘物质。牺牲层的材料可以是氮化硅。导电层的材料可以是金属，或者其他有导电能力的材料(比如石墨烯或高分子化合物等)。
通道结构440可以是半导体材料。例如可以是多晶半导体或单晶半导体。通道结构440采用单晶半导体，通道结构440中的缺陷较少，可以提高三维存储器的性能。
三维存储器还可以包括位于所述通道结构表面的保护层。在形成存储结构之前，可以将通道结构440表面导电层所在位置的保护层去除，从而形成多个保护结构。
也就是说，三维存储器还可以包括保护结构，保护结构在介质层420中，保护结构位于通道结构440的表面。也就是说，保护结构所在的介质层中的电解质材料接触。
为了防止牺牲层中的元素在通道结构440中的半导体生长过程中扩散至通道结构440的半导体中，影响三维存储器的性能，在贯穿层叠结构的存储孔中形成通道结构440之前，可以在存储孔的侧壁形成保护层。
去除牺牲材料时，由于工艺偏差，可能导致保护层被全部或部分刻蚀，如果将保护层作为存储结构的一部分，例如作为隧穿层或作为隧穿层的一部分，去除牺牲材料后保护层的厚度影响晶体管的性能参数。
因此，可以去除通道结构440的表面牺牲层的位置处的保护层。保护层被分为多个保护结构。保护结构与介质层420一一对应。每个保护结构位于通道结构440的表面，并与该保护结构对应的介质层420接触。
通过去除通道结构440的表面位于去除的牺牲层处的保护层，可以避免刻蚀过程的工艺偏差对晶体管的性能参数的影响。
在3D存储器的每个晶体管中，存储结构位于栅极与通道结构440之间。存储结构存在两种稳定状态，以使得提供相等的栅电压时，晶体管可以处于导通和关断两种状态。通过对两种稳定状态的调整，进行数据的存储。存储结构可以是电荷捕获结构ONO，包括隧穿层、电荷俘获层和阻挡层。存储结构也可以是铁电存储结构等。本申请实施例对此不作限定。
通道结构440的材料可以是单晶半导体。例如，通道结构440的材料为单晶硅。保护层的材料可以为非晶半导体，例如非晶硅。非晶硅(amorphous silicon)硬度明显低于晶体硅，化学性质比晶体硅活泼，因此可以将通道结构440的单晶硅作为刻蚀停止层。在去除非晶硅保护层时，可以选取对氧化硅介质层的刻蚀速率较低的刻蚀剂。采用非晶硅作为保护层，可以减小刻蚀工艺的难度。
在形成存储结构450之前，可以在通道结构440的表面去除牺牲层的位置形成凹槽。在凹槽中形成存储结构450，然后淀积导电材料，以代替牺牲层，形成导电层430。
也就是说，在每个导电层430，通道结构440的表面包括凹槽，该导电层430对应的存储结构位于凹槽中。
随着层叠结构的层数增多，通道结构440的高度增加。当半导体通道241采用单晶半导体材料时，与衬底210的距离越远，即单晶硅的生长高度越高，通道结构440单位体积中的缺陷数量越多。通过在通道结构440表面导电层430所在的位置(即去除的牺牲层的位置)设置凹槽，可以减少缺陷数量，从而降低缺陷对三维存储器的性能的影响。
通道结构440的材料，可以是单晶硅。单晶硅的晶体结构为面心立方结构，如图5所示，Si原子位于正方体6个面的面心以及正方体的8个顶点。
单晶硅的晶体结构中，A、B、C、D四个点分别为4个Si原子，分别位于正方体的四个顶点。其中，A、B、C位于正方体同一面的三个顶点，AB为正方体的一条边，BC为正方体的另一条边，AD为正方体的体对角线。沿面心立方的边长(例如沿边长AB)所在直线的方向为晶格方向“001”，沿面心立方一个面的对角线所在直线(例如沿直线AC)的方向为晶格方向“110”，沿面心立方体对角线所在直线(例如沿直线AD)的方向为晶格方向“111”。晶格方向也可以称为晶向。单晶硅可以沿晶格方向“001”、“110”或“111”生长。优选地，通道结构采用沿所述通道结构远离所述衬底的方向的单晶晶格方向为“001”的单晶硅。
晶格方向为“110”的单晶硅生长速度较慢，但缺陷较少，从而可以获得较好的电荷迁移率，提高三维存储器的性能。
晶格方向为“001”的单晶硅生长速度较快。通过在通道结构440表面导电层430所在的位置设置凹槽，可以减少缺陷数量。从而，在满足对通道结构的迁移率要求的情况下，通道结构440的高度可以增加。随着通道结构440的高度增加，单晶硅生长需要的时间正常。通道结构440采用晶格方向为“001”的单晶硅，可以获得较快的单晶硅生长速度，缩短制备三维存储器的工艺时间，降低制造成本。
图6是本申请实施例提供的一种三维存储器的制备方法的示意性流程图。
在S501之前，可以在衬底201上形成层叠结构下的一层或多层金属层。金属层可以包括图形化的金属，从而可以在衬底201上形成各种电路。例如，可以形成用于传输电源信号、三维存储器的控制信号等信号的金属层。
或者，也可以在其他芯片上形成电路，之后与三维存储器键合，以进行信号的传输。具体地，可以参见图20的说明。
衬底210的材料可以采用硅(Si)、锗(Ge)、砷化镓等半导体材料。当形成多个金属层时，该多个金属层的材料可以相同或不同。
下面，以衬底210的材料是硅为例进行说明。
S501，在衬底210上形成层叠结构。
层叠结构的包括交替堆叠的多个牺牲(sacrificial，SAC)层和多个介质层。如图7所示，多个牺牲层分别为SAC0、SAC1、SAC2、SAC3。多个介质层分别为D0、D1、D2、D3、D4。
牺牲层中的牺牲材料在后续工艺中将被导电材料替换，以形成各个晶体管的栅极信号传输线，例如可以是字线WL0、WL1等。牺牲材料例如可以是氮化硅。
介质层用于字线之间的绝缘。介质层的材料可以是氧化硅(SiO 2)等绝缘体。
层叠结构可以通过淀积工艺形成。例如，可以采用化学气相淀积工艺生成层叠结构。
化学气相淀积(chemical vapor deposition)工艺，把含有构成薄膜元素的气态反应剂引入反应室，在晶圆表面发生化学反应，从而生成所需的固态薄膜并淀积在其表面。
S502，刻蚀贯穿层叠结构的存储孔(memory hole，MH)。
存储孔穿过牺牲层中的牺牲材料。
刻蚀技术主要分为干法刻蚀与湿法刻蚀。
干法刻蚀是把硅片表面曝露于气态中产生的等离子体，等离子体通过光刻胶中开出的窗口，与硅片发生物理或化学反应(或这两种反应)，从而去掉曝露的表面材料。干法刻蚀也可以称为反应离子刻蚀(reactive ion etching，RIE)或光刻。
湿法刻蚀主要利用化学试剂与被刻蚀材料发生化学反应进行刻蚀。湿法刻蚀也用来腐蚀硅片上某些层或用来去除干法刻蚀后的残留物。
可以通过反应离子刻蚀形成存储孔。反应离子刻蚀技术具有在垂直方向刻蚀速度更快的特性。
存储孔垂直延伸穿过交替的牺牲层和绝缘层。存储孔可以向下延伸到衬底210。
应当理解，从远离衬底210的顶部到靠近衬底210的底部，存储孔的尺寸可以变化。例如，存储孔的尺寸可以从顶部到底部逐渐减小。
图7所示为S502之后形成的结构。
S503，在存储孔中淀积保护层710，以形成图8所示的结构。
优选地，可以在温度小于400℃下利用原子层沉积技术(atomic layer deposition，ALD)生成保护层710。保护层710的厚度可以为5至20埃(A)。保护层710例如可以是非晶硅。应当理解，牺牲层、介质层的厚度遵循行业标准，保护层710的厚度远小于牺牲层、介质层的厚度。
原子层沉积也可以称为单原子层沉积，是一种可以将物质以单原子膜形式一层一层的镀在基底表面的方法。原子层沉积与普通的化学沉积有相似之处。但在ALD过程中，新一层原子膜的化学反应是直接与之前一层相关联的，这种方式使每次反应只沉积一层原子。
原子层沉积的工艺温度可以小于400摄氏度(℃)。
S504，通过刻蚀，去除衬底210表面的保护层710。
反应离子刻蚀技术具有在垂直方向刻蚀速度更快的特性。可以通过氢等离子体(hydrogen plasma)去除存储孔底部的保护层710，露出衬底210的表面。
如图9所示，存储孔垂直穿过层叠结构，存储孔侧壁覆盖保护层710。
S505，在存储孔中生长单晶硅，以形成通道结构440。
可以采用选择性外延生长(selective epitaxial growth，SEG)技术，在存储孔中生长单晶硅。
选择性外延生长是指在衬底上限定的区域内进行的外延生长。
衬底210的材料为硅，可以以衬底210作为单晶种子(seed)，在存储孔中生长单晶硅。应当理解，在存储孔中生长的单晶硅的晶向与衬底210的晶向相同。晶向即晶格方向。
应当理解，S504为可选步骤。使用干净的单晶硅衬底作为SEG的单晶种子，是一种进行SEG的有效方式。当然，SEG的单晶种子还可以是其他方式，本申请实施例不作限定。
单晶硅通道结构440的晶格方向可以为“110”或“001”等。单晶硅通道结构440的晶格方向为“110”，生长的单晶硅中的缺陷较少，电荷迁移率较好，从而能够提高三维存储器的性能。单晶硅通道结构440的晶格方向为“001”，单晶硅的生长速度较快，能够缩短制备三维存储器的工艺时间，降低制造成本。
可以采用晶格方向为“001”的晶圆作为衬底210。
可以通过各种外延生长技术，在存储孔中生长单晶硅。一般情况下，SEG工艺的温度范围在400-1000℃，具体温度选择与生长的半导体材料有关。
进行SEG工艺的工程中，由于温度较高，介质层中的氮(N)等原子可能通过扩散进入单晶硅，对单晶硅的性能产生影响。在存储孔的侧壁上设置的保护层710，可以防止介质层中原子扩散至存储孔的单晶硅中。
在S505之前，可以对存储孔的底部即存储孔中衬底210表面进行预清洁处理。
应当理解，多个存储孔中，单晶硅从衬底210表面同步向上生长。图10示出了进行S505之后的结构。
S506，去除牺牲层中的牺牲材料，以及牺牲材料所在位置的通道结构表面的保护层710。
由于存储孔穿过产生材料，因此，去除牺牲材料之后，牺牲材料所在位置的通道结构表面的保护层710暴露，可以去除该位置的保护层710。
选择能够刻蚀牺牲层，而对介质层具有较低腐蚀性，且对单晶硅具有较低腐蚀性的刻蚀剂。
如果刻蚀剂对牺牲层具有较高腐蚀性，而对非晶硅腐蚀性较低，非晶硅可以作为刻蚀停止层。之后，选择对非晶硅具有较高腐蚀性，而对单晶硅具有较低腐蚀性的刻蚀剂，去除牺牲层所在位置的通道结构440表面的保护层710。
如果刻蚀剂对牺牲层和非晶硅具有较高腐蚀性，而对单晶硅腐蚀性较低，通道结构440可以作为刻蚀停止层。也就是说，该刻蚀剂对介质层和单晶硅的蚀刻性能不强，因此在蚀刻时，牺牲层的材料(如氮化物)会被刻蚀掉，且作为保护层710的非晶硅侧壁会被过刻蚀，最后刻蚀在硬度较高不易蚀刻的单晶硅的表面停止。
通过刻蚀停止层，停止刻蚀的方式，可以称为自限过刻蚀(self-limited recess)工艺。该刻蚀停止层也可以称为自限过刻蚀停止层(self-limited recess etch stop layer)。
由于刻蚀过程中，远离衬底的顶部的刻蚀速率大于靠近衬底的底部的刻蚀速率，需要控制刻蚀时间，避免将单晶硅侧壁的保护层710完全去除。
如果将保护层710完全去除，由于保护层710厚度很小，很难对去除的保护层710的空间进行填充，对三维存储器的性能造成不利的影响。
保护层710的材料以及刻蚀剂的选择，应当使得，去除牺牲层所在位置的通道结构表面的保护层710时，能够避免对层叠结构中介质层结构以及通道结构440的破坏。也就是说，通过采用自限过刻蚀(self-limited recess)工艺，将单晶硅作为刻蚀停止层，去除晶硅表面的氧化硅层731，能够避免对层叠结构中介质层结构以及通道结构440的破坏，并降低工艺难度。
图11示出了进行S506之后的结构。图12是对图11中的虚线区域的局部放大图。牺牲层被去除。保护层710被刻蚀为分离的圆环，环绕在通道结构440的柱体上。
S507，在通道结构440表面去除的牺牲层所在位置刻蚀凹槽。
具体地，在S507a之前，对去除的牺牲层所在位置的通道结构440的表面进行预清洗。
S507a，可以通过湿氧氧化、干氧氧化等氧化工艺，在去除的牺牲层所在位置的通道结构440的表面生长氧化硅层731，如图13所示。
由于保护层710的材料也是硅，在保护层710的表面也会形成生长氧化硅。也就是说， 氧化硅层731位于牺牲层所在位置的通道结构440和保护层710的表面。
在通道结构440表面生长氧化层时，通道结构440表面的硅原子发生化学反应生成氧化硅，以形成氧化层。因此，在氧化层生成时，牺牲层所在位置的通道结构440表面，即单晶硅与氧化硅的分界面，逐渐向通道结构440的中心移动。因为氧化层生长不具有方向性，在平行于衬底表面的方向，通道结构440表面向通道结构440的中心移动的同时，在垂直于衬底表面的方向，通道结构440表面向靠近介质层中心的方向移动。
S507b，通过刻蚀工艺，去除通道结构440表面的氧化硅层731。
去除通道结构440表面的氧化硅层731，可以使得通道结构440表面暴露。
可以采用湿法刻蚀。湿法刻蚀对单晶硅的晶格不会产生影响。由于湿法刻蚀工艺的刻蚀速率不具有方向性，也就是对各个方向的刻蚀速率基本相同。刻蚀通道结构440表面的氧化硅层731，也可以理解为去除氧化硅层731。氧化工艺生成氧化硅层731的过程，氧化硅层731中的硅元素全部或部分来源于通道结构440中的单晶硅。也就是说，采用氧化工艺生长氧化硅层731时，通道结构440和保护层710位于牺牲层所在位置表面的硅发生化学反应形成了氧化硅层731中的氧化硅。因此，通过S507a至S507b，在牺牲层所在位置的通道结构440表面生长氧化层，之后刻蚀氧化层，会在牺牲层所在位置的通道结构440表面形成凹槽，如图14和图15所示。图15为立体图，图14为剖面图。
由于在生长氧化层时去除牺牲材料的通道结构440表面为止的变化，使得凹槽的宽度一般略大于牺牲层的宽度(或者说牺牲层的厚度)。
在S507b之前，可以再次清洗。
应当理解，介质层的材料也可以是氧化硅。进行S507b时，也会去除介质层表面的部分。为了避免破坏介质层的绝缘作用，应当控制进行S507b的时间，以使得能够去除单晶硅表面的氧化硅，而不影响介质层的绝缘功能。
利用SEG工艺生长的单晶硅，随着生长高度的增加，单位体积单晶硅中的缺陷数量增加。也就是说，在单晶硅通道结构中，通道结构顶部(远离衬底的部分)的缺陷会比底部(靠近衬底的部分)数量多。
因此，通道结构中，随着与通道结构中心的距离的增加，单位体积单晶硅中的缺陷数量增加。也就是说，在单晶硅通道结构中，表面的缺陷比内部的缺陷数量多。
缺陷数量的增加会导致电荷迁移率降低，存储单元性能降低。
通道结构顶部的刻蚀速率大于通道结构底部的刻蚀速率。
通过S507，通过在牺牲层所在位置的通道结构440表面生长氧化层并刻蚀氧化层，形成凹槽，能够有效降低垂直通道内存储单元处的缺陷数量，减小SEG工艺对存储单元性能的影响，从而提高三维存储器的容量和性能。在相同的晶体管性能要求下，通过设置凹槽，可以增加层叠结构中牺牲层和介质层的数量，即增加单位面积的晶体管数量，有效提高三维存储器的容量。
S508，在凹槽中形成存储结构。
存储结构可以铁电存储结构。也就是说，通过图6所示的方法可以制备三维铁电存储器。
铁电存储器是一种特殊工艺的非易失性的存储器，是采用人工合成的铅锆钛(PZT)或铪锆氧化物(HfZrOx)材料形成存储器结晶体。当一个电场被施加到铁晶体管时，中心 原子顺着电场停在低能量状态I位置，反之，当电场反转被施加到同一铁晶体管时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态II。大量中心原子在晶体单胞中移动耦合形成铁电畴，铁电畴在电场作用下形成极化电荷。铁电畴在电场下反转所形成的极化电荷较高，铁电畴在电场下无反转所形成的极化电荷较低，这种铁电材料的二元稳定状态使得铁电可以作为存储器。
特别是当移去电场后，中心原子处于低能量状态保持不动，存储器的状态也得以保存不会消失，因此可利用铁电畴在电场下反转形成高极化电荷，或无反转形成低极化电荷来判别存储单元是在“1”或“0”状态。铁电畴的反转不需要高电场，仅用一般的工作电压就可以改变存储单元是在“1”或“0”的状态；也不需要电荷泵来产生高电压数据擦除，因而没有擦写延迟的现象。这种特性使铁电存储器在掉电后仍能够继续保存数据，写入速度快且具有无限次写入寿命，不容易写坏。
存储结构也可以是电荷捕获结构ONO等。电荷捕获结构ONO包括隧穿层732、电荷俘获层733、阻挡层734，如图16所示。
在凹槽内依次淀积形成隧穿层732、电荷俘获层733、阻挡层734。
可以通过化学气相淀积或原子层淀积，形成电荷捕获结构。电荷捕获结构包括隧穿层732、电荷俘获层733、阻挡层734。
原子层淀积(atomic layer deposition，ALD)是一种可以将物质以单原子膜形式一层一层的镀在基底表面的方法。原子层沉积与普通的化学沉积有相似之处。但在原子层沉积过程中，新一层原子膜的化学反应是直接与之前一层相关联的，这种方式使每次反应只沉积一层原子。
在一些实施例中，电荷捕获结构厚度可以小于50A，使得擦写电压可降低至5伏(V)，存储单元访问速度加快，擦写寿命提高，数据保存时间减少。
应当理解，进行S508时，在介质层的表面也会生长隧穿层、电荷俘获层、阻挡层的材料。由于隧穿层、电荷俘获层、阻挡层的材料均为绝缘体，介质层的表面的隧穿层、电荷俘获层、阻挡层材料也可以理解为介质层的一部分，用于替换牺牲层的金属层之间的绝缘。
S509，在去除的牺牲层的位置淀积导电材料，以形成导电层430。
可以采用标准3D NAND替代栅(3D NAND replace gate)工序，形成导电层430。
也就是说，用导电材料代替去除的牺牲层。可以通过化学气相淀积或原子层淀积，形成导电层430。导电材料可以是金属，例如镍(Ni)，钛Ti，钴(Co)或钨(W)等。
进行S509之后的结构如图17所示。图18是图17中虚线区域的局部放大图。图19是图18所示的结构的俯视图，图18是图19所示的结构沿直线AA’的剖面图。
牺牲层SAC0替换为选择线SGS、SAC1替换为字线WL0、SAC2替换为字线WL1、SAC3替换为选择线SGD。
图19示出了用于存储孔的一种可能的图案。图19所示的存储孔是交错的，但这不是唯一可能的模式。例如，存储孔不需要如图19所示交错。
图19所示的存储孔在水平方向上具有圆形横截面。存储孔还可以是其他形状，本申请实施例对此不作限定。
应当理解，在不同的层中，存储孔的大小可能不同。例如，靠近衬底210的层的存储 孔可能较小。
在S509之后，可以去除衬底，以减小三维存储器的厚度。
图20是本申请实施例提供的一种三维存储器及控制电路的示意性结构图。
可以在芯片的衬底上形成三维存储器，以形成三维存储器芯片1901。
可以在芯片的衬底上形成电路，以形成电路芯片1902。
可以将三维存储器芯片1901与电路芯片1902键合。
例如，可以采用面对面键合(face to face bonding)工艺，将三维存储器芯片1901与电路芯片1902的上表面之间形成键合接口，使得三维存储器芯片1901与电路芯片1902的上表面电连接，两个晶圆叠(stack)在一起，通过电路芯片1902传输信号，实现对三维存储器芯片1901的控制。
为了提高三维存储器芯片1901中的三维存储器生长速度，三维存储器芯片1901的衬底可以采用单晶晶格方向为“001”的单晶硅。
为了提高电路芯片1902的性能，电路芯片1902的衬底可以采用单晶晶格方向为“110”的单晶硅。
当然，也可以采用晶圆级塑封(wafer level molding)工艺等技术，实现三维存储器芯片1901与电路芯片1902的电连接。
图21是本申请实施例提供的一种三维存储器的制备方法的示意性流程图。
在S601，形成层叠结构，所述层叠结构包括交替堆叠的牺牲层和介质层。
可以在衬底上形成层叠结构。
在S602，形成通道结构，所述通道结构贯穿所述层叠结构，并穿过所述牺牲层中的牺牲材料。
在S603，去除所述牺牲层中的牺牲材料。
牺牲层包括牺牲材料，牺牲材料可以是氮化硅等。牺牲层还可以包括或不包括其他材料，本申请实施例不作限定。
在S604，在所述通道结构表面的去除所述牺牲材料的位置，形成存储结构。
在S605，沉积导电材料代替去除的所述牺牲材料。
可选地，所述通道结构为单晶半导体材料。
可选地，在S602，可以形成存储孔，所述存储孔贯穿所述层叠结构，并穿过所述牺牲材料。
在所述存储孔的侧壁形成保护层。
在所述存储孔中填充单晶半导体材料，以形成所述通道结构。
在通道结构形成的过程中，层叠结构牺牲材料中的元素(如氮)可能扩散至通道结构的单晶半导体中，影响三维存储器的性能。通过在通道结构的表面设置保护层，可以降低甚至消除层叠结构牺牲层中的元素的扩散。
在S604之前，可以去除所述通道结构表面的牺牲材料的位置的保护层，以使得所述通道结构表面的每个牺牲层的位置暴露。
因此，保护层被分割为多个保护结构，保护结构可以与层叠结构中的介质层一一对应。
在形成存储结构之前，去除通道结构的表面位于去除的牺牲层处的保护层，可以避免刻蚀过程的工艺偏差对晶体管的性能参数的影响。
可选地，存储孔中填充半导体材料可以是单晶硅，保护层的材料可以是非晶硅。
非晶硅(amorphous silicon)硬度明显低于晶体硅，化学性质比晶体硅活泼，因此可以将单晶硅作为刻蚀停止层，减小刻蚀工艺的难度。
可选地，在S603之后，在所述通道结构表面的每个去除的牺牲材料的位置形成凹槽。
通过在通道结构表面导电层所在的位置(即去除的牺牲材料的位置)设置凹槽，可以减少单晶硅通道结构中的缺陷数量，从而降低缺陷对三维存储器的性能的影响。
具体地，可以在所述通道结构表面的每个去除牺牲材料的位置形成氧化物。之后，可以去除所述氧化物以形成所述凹槽。
在S604，在所述通道结构表面的凹槽中，形成存储结构。
可选地，所述通道结构的材料为沿所述通道结构远离所述衬底的方向的单晶晶格方向为“001”单晶硅。
晶格方向为“001”的单晶硅生长速度较快。通过在通道结构440表面导电层430所在的位置设置凹槽，可以减少缺陷数量。从而，在满足对通道结构的迁移率要求的情况下，通道结构440的高度可以增加。随着通道结构440的高度增加，单晶硅生长需要的时间正常。通道结构440采用晶格方向为“001”的单晶硅，可以获得较快的单晶硅生长速度，缩短制备三维存储器的工艺时间，降低制造成本。
可选地，在所述通道结构表面的去除所述牺牲层的位置，依次形成所述存储结构中堆叠的隧穿层、电荷俘获层和阻挡层。
本申请实施例提供一种电子设备，包括前文中的三维存储器。
本申请实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示单独存在A、同时存在A和B、单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项”及其类似表达，是指的这些项中的任意组合，包括单项或复数项的任意组合。例如，a，b和c中的至少一项可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种三维存储器，其特征在于，包括：层叠结构、通道结构、存储结构；
    所述层叠结构包括交替堆叠的导体层和介质层；
    所述通道结构贯穿所述层叠结构；
    所述导体层中包括导电材料；
    所述存储结构在所述导体层中，形成于所述通道结构的表面，且处于所述通道结构和所述导电材料之间。
  2. 根据权利要求1所述的三维存储器，其特征在于，所述通道结构中包括单晶半导体材料。
  3. 根据权利要求1或2所述的三维存储器，其特征在于，所述介质层包括所述保护结构，所述保护结构位于所述通道结构的表面。
  4. 根据权利要求3所述的三维存储器，其特征在于，所述通道结构的材料为单晶硅；所述保护结构的材料为非晶硅。
  5. 根据权利要求1-4中任一项所述的三维存储器，其特征在于，
    在所述导电层，所述通道结构的表面包括凹槽，所述存储结构位于所述凹槽中。
  6. 根据权利要求5所述的三维存储器，其特征在于，所述通道结构的材料为沿所述通道结构贯穿所述层叠结构方向的单晶晶格方向为“001”的单晶硅。
  7. 根据权利要求1-6中任一项所述的三维存储器，其特征在于，所述存储结构包括沿远离所述通道结构的方向依次设置的隧穿层、电荷俘获层和阻挡层。
  8. 一种电子设备，其特征在于，包括权利要求1-7中任一项所述的三维存储器。
  9. 一种三维存储器的制备方法，其特征在于，包括：
    形成层叠结构，所述层叠结构包括交替堆叠的牺牲层和介质层；
    形成通道结构，所述通道结构贯穿所述层叠结构，并穿过所述牺牲层中的牺牲材料；
    去除所述牺牲材料；
    在所述通道结构表面的去除所述牺牲材料的位置，形成存储结构；
    沉积导电材料代替去除的所述牺牲材料。
  10. 根据权利要求9所述的方法，其特征在于，所述通道结构中包括单晶半导体材料。
  11. 根据权利要求9或10所述的方法，其特征在于，
    所述形成通道结构，包括：
    形成存储孔，所述存储孔贯穿所述层叠结构，并穿过所述牺牲材料；
    在所述存储孔的侧壁形成保护层；
    在形成有所述保护层的所述存储孔中生长半导体材料，以形成所述通道结构；
    所述方法还包括：去除位于所述通道结构表面的去除所述牺牲材料的位置的保护层。
  12. 根据权利要求11所述的方法，其特征在于，
    所述去除所述通道结构表面的所述牺牲材料的位置的保护层，包括：采用刻蚀工艺以去除所述通道结构表面的所述牺牲材料的位置的保护层，所述存储孔中生长的半导体材料为刻蚀停止层。
  13. 根据权利要求11或12所述的方法，其特征在于，所述存储孔中生长半导体材料为单晶硅；所述保护层的材料为非晶硅。
  14. 根据权利要求9-13中任一项所述的方法，其特征在于，所述通道结构包括单晶半导体材料，
    所述方法还包括：在所述通道结构表面的去除所述牺牲材料的位置形成凹槽；
    所述在所述通道结构表面的去除所述牺牲材料的位置，形成存储结构，包括：在所述凹槽中，形成所述存储结构。
  15. 根据权利要求14所述的方法，其特征在于，所述在所述通道结构表面的去除所述牺牲层的位置形成凹槽，包括：
    在所述通道结构表面的去除所述牺牲材料的位置形成氧化物；
    去除所述氧化物以形成所述凹槽。
  16. 根据权利要求14或15所述的方法，其特征在于，所述通道结构的材料为沿所述通道结构远离所述衬底的方向的单晶晶格方向为“001”单晶硅。
  17. 根据权利要求9-16中任一项所述的方法，其特征在于，所述在所述通道结构表面的去除所述牺牲层的位置，形成存储结构，包括：
    在所述通道结构表面的去除所述牺牲层的位置，依次形成所述存储结构中堆叠的隧穿层、电荷俘获层和阻挡层。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103155138A (zh) * 2010-10-14 2013-06-12 株式会社Eugene科技 制造三维结构存储元件的方法及装置
US20140308789A1 (en) * 2010-06-15 2014-10-16 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US20170025545A1 (en) * 2015-07-23 2017-01-26 Phil Ouk NAM Semiconductor device and method of fabricating the same
CN107507831A (zh) * 2017-08-31 2017-12-22 长江存储科技有限责任公司 一种3d nand存储器的存储单元结构及其形成方法
CN110800106A (zh) * 2019-09-29 2020-02-14 长江存储科技有限责任公司 具有外延生长的半导体沟道的三维存储器件及其形成方法
CN111149207A (zh) * 2017-08-11 2020-05-12 美光科技公司 包含控制栅极之间的空隙的存储器装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140308789A1 (en) * 2010-06-15 2014-10-16 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
CN103155138A (zh) * 2010-10-14 2013-06-12 株式会社Eugene科技 制造三维结构存储元件的方法及装置
US20170025545A1 (en) * 2015-07-23 2017-01-26 Phil Ouk NAM Semiconductor device and method of fabricating the same
CN111149207A (zh) * 2017-08-11 2020-05-12 美光科技公司 包含控制栅极之间的空隙的存储器装置
CN107507831A (zh) * 2017-08-31 2017-12-22 长江存储科技有限责任公司 一种3d nand存储器的存储单元结构及其形成方法
CN110800106A (zh) * 2019-09-29 2020-02-14 长江存储科技有限责任公司 具有外延生长的半导体沟道的三维存储器件及其形成方法

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