JP7270722B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7270722B2 JP7270722B2 JP2021509068A JP2021509068A JP7270722B2 JP 7270722 B2 JP7270722 B2 JP 7270722B2 JP 2021509068 A JP2021509068 A JP 2021509068A JP 2021509068 A JP2021509068 A JP 2021509068A JP 7270722 B2 JP7270722 B2 JP 7270722B2
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- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000004020 conductor Substances 0.000 claims description 61
- 239000007789 gas Substances 0.000 claims description 34
- 125000006850 spacer group Chemical group 0.000 claims description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 17
- 239000010937 tungsten Substances 0.000 claims description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- WIDQNNDDTXUPAN-UHFFFAOYSA-I tungsten(v) chloride Chemical compound Cl[W](Cl)(Cl)(Cl)Cl WIDQNNDDTXUPAN-UHFFFAOYSA-I 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910003091 WCl6 Inorganic materials 0.000 claims description 3
- KPGXUAIFQMJJFB-UHFFFAOYSA-H tungsten hexachloride Chemical compound Cl[W](Cl)(Cl)(Cl)(Cl)Cl KPGXUAIFQMJJFB-UHFFFAOYSA-H 0.000 claims description 3
- 230000000052 comparative effect Effects 0.000 description 28
- 239000013078 crystal Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 18
- 230000004888 barrier function Effects 0.000 description 17
- 238000001312 dry etching Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、本開示の一実施形態における半導体装置の製造方法の一例を示すフローチャートである。本実施形態では、図1のフローチャートに示された手順により、半導体装置の製造に用いられるウエハWが製造される。以下では、図2~図8を参照しながら、半導体装置の製造方法の一例を説明する。
ここで、比較例における半導体装置の製造手順について、図9~図12を参照しながら説明する。比較例における半導体装置の製造手順では、上記した実施形態において説明されたステップS10からS13までと同様の処理が行われる。即ち、図6Aおよび図6Bに示された状態までは、比較例における半導体装置の製造手順は、実施形態における半導体装置の製造手順と同様である。
図13は、コンタクトパッドの下部における結晶粒180の大きさの一例を説明するための模式図である。図13(a)は、比較例における結晶粒180の大きさの一例を示し、図13(b)は、本実施形態における結晶粒180の大きさの一例を示す。
10 アクティブ領域
11 コンタクト
12 電極膜
13 絶縁膜
14 スペーサ
15 絶縁膜
16 マスク膜
17 コンタクトプラグ
18 第2の導電材料
180 結晶粒
181 界面
19 コンタクトパッド
20 下地膜
21 バリア膜
30 構造物
31 溝部
32 ホール
Claims (4)
- 基板上に積層された絶縁膜の領域にホールを形成するホール形成工程と、
前記ホール内に、前記ホールを構成する側壁の高さよりも低い位置まで第1の導電材料を埋め込む第1の埋込工程と、
前記第1の導電材料が埋め込まれた前記ホール内に、選択成長により第2の導電材料をさらに埋め込む第2の埋込工程と、
前記第2の導電材料をエッチングすることにより、前記ホールの上方の位置にコンタクトパッドを形成するエッチング工程と
を含み、
前記第2の埋込工程では、タングステン含有ガスを前記基板の表面に供給する工程と、水素含有ガスのプラズマを前記基板の表面に供給する工程とが交互に繰り返される半導体装置の製造方法。 - 基板上に形成されたスペーサ間の溝部を絶縁膜で埋め込み、
前記絶縁膜の一部を除去して、前記スペーサと前記絶縁膜で囲まれたホールを形成し、
前記ホール内に、前記ホールを構成する側壁の高さよりも低い位置まで第1の導電材料を形成し、
前記第1の導電材料上に第2の導電材料を形成し、
前記第2の導電材料の一部を除去して、前記ホールの上方にコンタクトパッドを形成し、
前記第2の導電材料は、タングステン含有ガスを前記基板の表面に供給する工程と、水素含有ガスのプラズマを前記基板の表面に供給する工程とを交互に繰り返し、前記第1の導電材料の上方で前記ホールを埋め込むまでは前記絶縁膜上及び前記スペーサ上に形成されず、前記ホールが埋め込まれた後で、前記絶縁膜上及び前記スペーサ上に形成される、ことを含む半導体装置の製造方法。 - 前記第1の導電材料は、ポリシリコンであり、
前記第2の導電材料は、タングステンである請求項1または2に記載の半導体装置の製造方法。 - 前記タングステン含有ガスは、WCl5ガス、WCl6ガス、またはWF6ガスであり、
前記水素含有ガスは、H2ガスまたはSiH4ガスである請求項1または2に記載の半導体装置の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2019063800 | 2019-03-28 | ||
JP2019063800 | 2019-03-28 | ||
PCT/JP2020/011323 WO2020195992A1 (ja) | 2019-03-28 | 2020-03-16 | 半導体装置の製造方法 |
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JPWO2020195992A1 JPWO2020195992A1 (ja) | 2020-10-01 |
JP7270722B2 true JP7270722B2 (ja) | 2023-05-10 |
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ID=72608679
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JP2021509068A Active JP7270722B2 (ja) | 2019-03-28 | 2020-03-16 | 半導体装置の製造方法 |
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Country | Link |
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US (1) | US20220013404A1 (ja) |
JP (1) | JP7270722B2 (ja) |
KR (1) | KR20210144776A (ja) |
CN (1) | CN113316840A (ja) |
WO (1) | WO2020195992A1 (ja) |
Citations (4)
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JP2001118998A (ja) | 1999-10-19 | 2001-04-27 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2008047720A (ja) | 2006-08-17 | 2008-02-28 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2014216409A (ja) | 2013-04-24 | 2014-11-17 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置の製造方法 |
US20180040561A1 (en) | 2016-08-08 | 2018-02-08 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
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KR960001601B1 (ko) * | 1992-01-23 | 1996-02-02 | 삼성전자주식회사 | 반도체 장치의 접촉구 매몰방법 및 구조 |
JPH04361568A (ja) * | 1991-06-10 | 1992-12-15 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JP3219909B2 (ja) * | 1993-07-09 | 2001-10-15 | 株式会社東芝 | 半導体装置の製造方法 |
KR970007819B1 (en) * | 1993-10-21 | 1997-05-17 | Hyundai Electronics Ind | Contact forming method of semiconductor device |
JP3305211B2 (ja) * | 1996-09-10 | 2002-07-22 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
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JP6297884B2 (ja) * | 2014-03-28 | 2018-03-20 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
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JP6416679B2 (ja) * | 2015-03-27 | 2018-10-31 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
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CN110678972B (zh) * | 2017-06-05 | 2023-06-20 | 应用材料公司 | 降低字线电阻的方法 |
US10923393B2 (en) * | 2018-09-24 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contacts and interconnect structures in field-effect transistors |
-
2020
- 2020-03-16 KR KR1020217033894A patent/KR20210144776A/ko unknown
- 2020-03-16 JP JP2021509068A patent/JP7270722B2/ja active Active
- 2020-03-16 WO PCT/JP2020/011323 patent/WO2020195992A1/ja active Application Filing
- 2020-03-16 CN CN202080007254.XA patent/CN113316840A/zh active Pending
-
2021
- 2021-09-23 US US17/448,608 patent/US20220013404A1/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001118998A (ja) | 1999-10-19 | 2001-04-27 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2008047720A (ja) | 2006-08-17 | 2008-02-28 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2014216409A (ja) | 2013-04-24 | 2014-11-17 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置の製造方法 |
US20180040561A1 (en) | 2016-08-08 | 2018-02-08 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
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US20220013404A1 (en) | 2022-01-13 |
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