WO2024077703A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2024077703A1
WO2024077703A1 PCT/CN2022/131744 CN2022131744W WO2024077703A1 WO 2024077703 A1 WO2024077703 A1 WO 2024077703A1 CN 2022131744 W CN2022131744 W CN 2022131744W WO 2024077703 A1 WO2024077703 A1 WO 2024077703A1
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WIPO (PCT)
Prior art keywords
contact
semiconductor
active
height
semiconductor structure
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PCT/CN2022/131744
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English (en)
French (fr)
Inventor
邵光速
朴淳秉
邱云松
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长鑫存储技术有限公司
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Publication of WO2024077703A1 publication Critical patent/WO2024077703A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method for manufacturing the same.
  • the present disclosure provides a semiconductor structure and a method for manufacturing the same.
  • a first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:
  • a plurality of active pillars wherein an isolation layer is disposed between adjacent active pillars, and a top surface of the active pillar is lower than a top surface of the isolation layer;
  • a plurality of contact holes are disposed above the plurality of active pillars in a one-to-one correspondence, and the diameter of the contact holes is the same as the diameter of the active pillars, and the inner wall of the contact hole is aligned with the outer surface of the active pillars;
  • a plurality of contact pads are respectively disposed at the bottoms of the plurality of contact holes and cover the top surfaces of the plurality of active pillars.
  • the semiconductor structure further includes: a plurality of storage structures and a plurality of contact plugs, each of the contact plugs fills an unfilled area of each of the contact holes, and each of the storage structures is electrically connected to the active pillar via the contact plug and the contact pad.
  • the semiconductor structure further includes: an interface layer, wherein the interface layer is located between the contact pad and the contact plug, and the thickness of the interface layer is 5nm-15nm.
  • the edge height of the top of the active column is greater than the center height.
  • the isolation layer has a first height
  • the active pillar has a second height
  • the second height is lower than the first height
  • the thickness of each of the contact pads is one tenth to one half of the height difference between the first height and the second height.
  • the plurality of active pillars are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect, and the semiconductor structure further comprises:
  • a plurality of word lines each of the word lines extending along the first direction, and any one of the word lines covering the sidewalls of a row of the active pillars arranged along the first direction;
  • a top surface of the active pillar is higher than a top surface of the word line.
  • the semiconductor structure further comprises:
  • a plurality of bit lines each of which extends along the second direction, and any one of the bit lines is disposed at the bottom of a column of active pillars arranged along the second direction.
  • a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
  • a contact pad is formed in each of the contact holes, and the contact pad covers a top surface of the active pillar.
  • the isolation layer has a first height, and a portion of the structure of each semiconductor column is removed, including:
  • each semiconductor column is etched to a second height, and the contact hole is formed in the removed area of each semiconductor column, and the second height is lower than the first height.
  • the forming of the contact pad includes: forming a semiconductor layer filling each of the contact holes, etching back the semiconductor layer to form the contact pad, and the thickness of the contact pad is one tenth to one half of the height difference between the first height and the second height.
  • the method for manufacturing the semiconductor structure further includes:
  • a plurality of storage structures are formed, each of the storage structures being electrically connected to the active pillar through the contact plug and the contact pad.
  • the method further includes: depositing a metal layer, the metal layer at least covering the surface of the contact pad, and heat treating the metal layer to form an interface layer on the surface of the contact pad.
  • forming a plurality of the semiconductor pillars comprises:
  • the plurality of first trenches and the plurality of second trenches divide the substrate into a plurality of semiconductor pillars arranged in an array.
  • the method for manufacturing the semiconductor structure further includes:
  • each of the word lines extending along the first direction, and any one of the word lines covering the sidewalls of a row of the active pillars arranged along the first direction;
  • a top surface of the active pillar is higher than a top surface of the word line.
  • the method for manufacturing the semiconductor structure further includes:
  • a plurality of bit lines are formed, each of the bit lines extends along the second direction, and any one of the bit lines is disposed at the bottom of a column of the active pillars arranged along the second direction.
  • the height difference between the active column and the isolation layer is used to self-align and form a contact hole above the active column.
  • the alignment accuracy of the contact hole and the active column is high, the contact pad arranged in the contact hole has a large contact area and a small contact resistance, and the electrical performance of the semiconductor structure is better.
  • FIG. 1 is a top view of a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a cross-sectional view of a semiconductor structure taken along line a-a according to an exemplary embodiment.
  • FIG. 3 is a cross-sectional view of a semiconductor structure taken along line a-a according to an exemplary embodiment.
  • FIG. 4 is a cross-sectional view of a semiconductor structure taken along line a-a according to an exemplary embodiment.
  • FIG. 5 is a flow chart showing a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 6 is a top view of a substrate according to an exemplary embodiment.
  • FIG. 7 is a top view showing a plurality of semiconductor pillars according to an exemplary embodiment.
  • FIG8 is a cross-sectional view of the a-a section of FIG7.
  • Fig. 9 is a cross-sectional view of the b-b section of Fig. 7 .
  • Fig. 10 is a cross-sectional view of the c-c section of Fig. 7 .
  • Fig. 11 is a cross-sectional view of the d-d section of Fig. 7 .
  • FIG. 12 is a cross-sectional view showing a section a-a of forming a bit line according to an exemplary embodiment.
  • FIG. 13 is a cross-sectional view showing a b-b section of forming a bit line according to an exemplary embodiment.
  • FIG. 14 is a cross-sectional view showing a c-c section of forming a bit line according to an exemplary embodiment.
  • FIG. 15 is a cross-sectional view showing a d-d cross section of forming a bit line according to an exemplary embodiment.
  • FIG. 16 is a cross-sectional view showing a section a-a of forming an isolation layer according to an exemplary embodiment.
  • Fig. 17 is a cross-sectional view showing a b-b section of forming an isolation layer according to an exemplary embodiment.
  • FIG. 18 is a cross-sectional view of a c-c section showing formation of an isolation layer according to an exemplary embodiment.
  • FIG. 19 is a cross-sectional view showing a d-d cross section of forming an isolation layer according to an exemplary embodiment.
  • FIG. 20 is a cross-sectional view showing a cross section a-a of forming a contact hole according to an exemplary embodiment.
  • FIG. 21 is a cross-sectional view of a c-c section showing the formation of a contact hole according to an exemplary embodiment.
  • FIG. 22 is a cross-sectional view showing a-a section of forming a semiconductor layer according to an exemplary embodiment.
  • FIG. 23 is a cross-sectional view showing a cross section a-a of forming a contact pad according to an exemplary embodiment.
  • FIG. 24 is a cross-sectional view showing a-a section of forming a conductive layer according to an exemplary embodiment.
  • FIG. 25 is a cross-sectional view showing a process of forming a contact plug and a lower electrode according to an exemplary embodiment.
  • FIG. 26 is a cross-sectional view showing a-a section of forming a dielectric layer according to an exemplary embodiment.
  • FIG. 27 is a cross-sectional view of a-a section showing formation of an interface layer according to an exemplary embodiment.
  • FIG. 28 is a cross-sectional view showing a-a section of forming a lower electrode according to an exemplary embodiment.
  • FIG. 29 is a cross-sectional view showing a-a section of forming a dielectric layer according to an exemplary embodiment.
  • H1 first height; H2, second height; D1, first direction; D2, second direction.
  • an isolation layer is formed between the semiconductor columns, and the top surface of the isolation layer is flush with the top surface of the semiconductor column.
  • a dielectric layer is formed on the substrate to prevent the semiconductor column from oxidizing. Therefore, in the related art, in the process of forming the contact pad, a light-etching process is used to form a contact hole in the dielectric layer to expose the surface of the semiconductor column, and then a contact pad is formed in the contact hole.
  • the contact hole may only expose part of the top surface of the semiconductor column, resulting in a small contact area and a large contact resistance between the contact pad and the semiconductor column formed in the contact hole, resulting in a decrease in the electrical performance of the semiconductor structure, affecting the quality and yield of the semiconductor structure.
  • the present embodiment provides a semiconductor structure and a method for manufacturing the same.
  • the top surface of an active column of the semiconductor structure is lower than the top surface of an isolation layer.
  • the height difference between the active column and the isolation layer is utilized to self-align a contact hole above the active column.
  • a contact pad is disposed in the contact hole.
  • the contact pad covers the top surface of the active column and is in contact with the active column.
  • the contact pad and the active column have high alignment accuracy and a large contact area.
  • the contact resistance between the contact pad and the active column is small, and the electrical performance of the semiconductor structure is good.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, and with reference to FIG. 20 and FIG. 26, the semiconductor structure includes a plurality of active pillars 11, an isolation layer 12 is disposed between adjacent active pillars 11, and the top surface of the active pillar 11 is lower than the top surface of the isolation layer 12.
  • the semiconductor structure also includes a plurality of contact holes 13 and a plurality of contact pads 14, the plurality of contact holes 13 are disposed one-to-one above the plurality of active pillars 11, and the aperture of each contact hole 13 is the same as the diameter of the corresponding active pillar 11, the inner wall of the contact hole 13 is aligned with the outer surface of the active pillar 11, the plurality of contact pads 14 are disposed one-to-one at the bottom of the plurality of contact holes 13, and the plurality of contact pads 14 cover the top surfaces of the plurality of active pillars 11 one-to-one.
  • the active column 11 may be an independently arranged circular column or rectangular column, and the material of the active column 11 includes a semiconductor material, and the semiconductor material may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the material of the semiconductor substrate may also be silicon on insulator (SOI) or germanium on insulator (GOI), and the semiconductor material may be doped with conductive ions.
  • the semiconductor material may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC);
  • the material of the semiconductor substrate may also be silicon on insulator (SOI) or germanium on insulator (GOI), and the semiconductor material may be doped with conductive ions.
  • adjacent active pillars 11 are separated by an isolation layer 12, and the material of the isolation layer 12 includes an insulating material.
  • the material of the isolation layer 12 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • the top surface of the isolation layer 12 is higher than the top surface of the active pillar 11, and the active pillar 11 and the isolation layer 12 have a height difference.
  • the height difference between the active pillar 11 and the isolation layer 12 self-aligns to form a contact hole 13 above each active pillar 11.
  • the contact hole 13 is surrounded by the top surface of the active pillar 11 and the isolation layer 12 located on the top surface of the active pillar 11.
  • the aperture of the contact hole 13 is the same as the diameter of the active pillar 11, the inner wall of the contact hole 13 is aligned with the outer surface of the active pillar 11, and the top surface of the active pillar 11 serves as the bottom wall of the contact hole 13.
  • a contact pad 14 is provided in each contact hole 13, the contact pad 14 covers the top surface of the active pillar 11 and fills a part of the contact hole 13, and the contact pad 14 is in contact with the top surface of the active pillar 11.
  • the material of the contact pad 14 includes a semiconductor material, and the material of the contact pad 14 may include one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound, and the material of the contact pad 14 may be doped with conductive ions.
  • the materials of the contact pad 14 and the active pillar 11 both include semiconductor materials, and the contact resistance between the contact pad 14 and the active pillar 11 is small.
  • the semiconductor structure of the present embodiment utilizes the height difference between the active pillar 11 and the isolation layer 12 to self-align and form a contact hole 13 above the active pillar 11, and uses the top surface of the active pillar 11 as the bottom wall of the contact hole 13, so that the contact hole 13 and the active pillar 11 are completely aligned, ensuring that the contact pad 14 provided in the contact hole 13 and the top surface of the active pillar 11 have a large contact area, reducing the contact resistance between the contact pad 14 and the active pillar 11, ensuring that the semiconductor structure has good electrical properties, and facilitating ensuring that the semiconductor structure has a high yield.
  • the semiconductor structure also includes a plurality of storage structures 30 and a plurality of contact plugs 20, each contact plug 20 fills an unfilled area of each contact hole 13, and each storage structure 30 is electrically connected to the active pillar 11 through the contact plug 20 and the contact pad 14.
  • a plurality of contact plugs 20 are independently arranged, and a plurality of contact plugs 20 and a plurality of contact holes 13 are arranged one by one.
  • the contact plugs 20 cover the top surface of the contact pads 14 and are in contact with the contact pads 14, and are in contact with the unfilled area of the corresponding contact holes 13.
  • the top surface of the contact plugs 20 is flush with the top surface of the isolation layer 12, or the top surface of the contact plugs 20 is higher than the top surface of the isolation layer 12.
  • the contact area between the contact plugs 20 and the contact pads 14 is large and the alignment accuracy is high.
  • the material of the contact plugs 20 may include a conductive metal, and exemplarily, the material of the contact plugs 20 may include titanium nitride.
  • a plurality of storage structures 30 and a plurality of contact plugs 20 are connected one by one, and each storage structure 30 is electrically connected to the active pillar 11 through the contact plug 20 and the contact pad 14.
  • the storage structure 30 may include a capacitor, a magnetic memory, and the like.
  • the storage structure 30 includes a lower electrode 31 disposed on the contact plug 20 , a dielectric layer 32 covering the surface of the lower electrode 31 , and an upper electrode 33 covering the surface of the dielectric layer 32 .
  • the top surface of the contact plug 20 is higher than the top surface of the isolation layer 12 , a portion of the structure of each contact plug 20 is located in the contact hole 13 , and another portion of the structure of each contact plug 20 is located above the isolation layer 12 .
  • the partial structure of each contact plug 20 located above the isolation layer 12 is used as the lower electrode 31 of the storage structure 30, which simplifies the process of forming the storage structure 30 and reduces the difficulty of manufacturing the semiconductor structure.
  • the semiconductor structure of this embodiment uses the partial structure of each contact plug 20 located above the isolation layer 12 as the lower electrode 31 of the storage structure 30, which can avoid the problem of misalignment between the storage structure 30 and the contact plug 20, ensure that the storage structure 30 and the contact plug 20 are arranged opposite to each other, and the semiconductor structure has high alignment accuracy, small contact resistance and good electrical performance.
  • the semiconductor structure does not include the contact plug 20 , and the storage structure 30 and the contact pad 14 are directly connected.
  • the storage structure 30 in the present embodiment includes a lower electrode 31, a dielectric layer 32 and an upper electrode 33.
  • the lower electrode 31 covers the top surface of the contact pad 14 and the side wall of the contact hole 13 located above the contact pad 14.
  • the dielectric layer 32 covers the surface of the lower electrode 31.
  • the upper electrode 33 covers the surface of the dielectric layer 32.
  • the top surface of the upper electrode 33 of the storage structure 30 is higher than the top surface of the isolation layer 12, and the upper electrodes 33 of multiple storage structures 30 are connected as a whole.
  • the main part of the storage structure 30 is arranged in the contact hole 13, and only a part of the lower electrode 31 is arranged above the isolation layer 12.
  • the storage structure 30 is arranged more stably, and the semiconductor structure has better anti-tilting performance.
  • the height of the edge of the top of the active pillar 11 is greater than the center height of the top of the active pillar 11, so as to increase the contact area between the contact pad 14 and the active pillar 11, further reduce the contact resistance between the contact pad 14 and the active pillar 11, and improve the electrical performance of the semiconductor structure.
  • the height of the active pillar 11 gradually decreases from the edge of the top surface of the active pillar 11 toward the center, and the top surface of the active pillar 11 is an arc surface that gradually sinks downward from the edge to the center, which not only increases the contact area between the contact pad 14 and the active pillar 11, but also ensures that the contact pad 14 and the top surface of the active pillar 11 are closely fitted, thereby reducing the contact resistance between the contact pad 14 and the active pillar 11.
  • the isolation layer 12 has a first height H1
  • the active pillar 11 has a second height H2
  • the second height H2 is lower than the first height H1, wherein the first height H1 and the second height H2 can be adjusted according to factors such as the design and size of the semiconductor structure, but are not limited thereto.
  • each contact pad 14 is one tenth to one half of the height difference between the first height H1 and the second height H2, so as to ensure that the contact pad 14 is arranged between the contact plug 20 and the active pillar 11 to reduce the contact resistance between the contact plug 20 and the active pillar 11, and after the contact pad 14 is arranged in the contact hole 13, the remaining space in the contact hole 13 can be used to arrange the contact plug 20, so that the connection between the contact plug 20 and the contact pad 14 is more stable, thereby improving the stability of the semiconductor structure.
  • the thickness of the contact pad 14 may be one tenth, one eighth, one fifth, one third, one half of the height difference between the first height H1 and the second height H2, or other values between one tenth and one half of the height difference between the first height H1 and the second height H2.
  • the thickness of each contact pad 14 is one fifth to one half of the height difference between the first height H1 and the second height H2.
  • the height difference between the first height H1 and the second height H2 is 50nm-100nm, and the thickness of the contact pad 14 can be 20nm-50nm.
  • the height difference between the first height H1 and the second height H2 is 50nm, and the thickness of the contact pad 14 is 20nm; the height difference between the first height H1 and the second height H2 is 60nm, and the thickness of the contact pad 14 is 30nm; the height difference between the first height H1 and the second height H2 is 70nm, and the thickness of the contact pad 14 is 30nm; the height difference between the first height H1 and the second height H2 is 70nm, and the thickness of the contact pad 14 is 30nm; the height difference between the first height H1 and the second height H2 is 90nm, and the thickness of the contact pad 14 is 40nm; the height difference between the first height H1 and the second height H2 is 100nm, and the thickness of the contact pad 14 can be 20nm; or, the height difference between the first height difference between the
  • a semiconductor structure is shown.
  • the semiconductor structure of this embodiment includes all the structures of the above embodiments.
  • the difference between this embodiment and the above embodiments is that, as shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the semiconductor structure further includes an interface layer 15, and the interface layer 15 is located between the contact pad 14 and the contact plug 20.
  • the material of the interface layer 15 includes metal silicide, and the interface layer 15 is arranged between the contact pad 14 and the contact plug 20 to reduce the contact resistance between the contact pad 14 and the contact plug 20, thereby improving the electrical performance of the semiconductor structure.
  • the material of the interface layer 15 may include at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or tungsten silicide (WSi).
  • the material of the interface layer 15 includes cobalt silicide.
  • the thickness of the interface layer 15 is 5 nm to 15 nm.
  • the thickness of the interface layer 15 may be 5 nm, 7 nm, 9 nm, 11 nm, 13 nm or 15 nm.
  • a semiconductor structure is shown, as shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the semiconductor structure of this embodiment includes a plurality of active pillars 11, and the plurality of active pillars 11 are arranged in an array along a first direction D1 and a second direction D2, and the first direction D1 and the second direction D2 intersect.
  • An isolation layer 12 is provided between adjacent active pillars 11, and the top surface of the active pillar 11 is lower than the top surface of the isolation layer 12.
  • the semiconductor structure also includes a plurality of contact holes 13 and a plurality of contact pads 14, the plurality of contact holes 13 are provided one by one above the plurality of active pillars 11, and the aperture of the contact hole 13 is the same as the diameter of the active pillar 11, the inner wall of the contact hole 13 is aligned with the outer surface of the active pillar 11, and the plurality of contact pads 14 are respectively provided at the bottom of the plurality of contact holes 13 and cover the top surface of the plurality of active pillars 11.
  • the semiconductor structure further includes a plurality of word lines 40, each word line 40 extending along the first direction D1, and any word line 40 covering the sidewall of a row of active pillars 11 arranged along the first direction D1; the top surface of the active pillar 11 is higher than the top surface of the word line 40.
  • the top surface of the active pillar 11 may be 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm higher than the top surface of the word line 40.
  • the word line 40 is arranged below the contact hole 13, and the word line 40 and the contact hole 13 are separated by the active column 11 above the word line 40.
  • the top surface of the active column 11 is 50nm-100nm higher than the top surface of the word line 40, ensuring that the word line 40 and the contact hole 13 are separated by the sufficiently thick active column 11, avoiding the word line 40 and the contact pad 14 and the contact plug 20 in the contact hole 13 being too close to each other and causing a short circuit, thereby improving the electrical performance of the semiconductor structure and facilitating delaying the working life of the semiconductor structure.
  • the semiconductor structure also includes a plurality of bit lines 50, each bit line 50 extends along the second direction D2, and any bit line 50 is arranged at the bottom of a column of active pillars 11 arranged along the second direction D2.
  • the semiconductor structure of this embodiment can be applied to dynamic random access memory (DRAM). However, it can also be applied to static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PRAM), etc.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • PRAM phase change random access memory
  • FIG. 5 shows a flow chart of the method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure
  • Figures 6 to 29 are schematic diagrams of various stages of the method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is introduced below in combination with Figures 6 to 29 and with reference to Figures 1 to 4.
  • the present embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto.
  • DRAM dynamic random access memory
  • the semiconductor structure in the present embodiment may also be other structures.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising the following steps:
  • Step S110 providing a substrate, forming a plurality of semiconductor columns arranged at intervals on the substrate, and an isolation layer arranged between adjacent semiconductor columns, wherein the top surfaces of the semiconductor columns and the isolation layer are flush.
  • substrate 1 can be a semiconductor substrate, and the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the material of the semiconductor substrate can also be silicon on insulator (SOI), germanium on insulator (GOI), and the semiconductor substrate can be doped with conductive ions.
  • the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the material of the semiconductor substrate can also be silicon on insulator (SOI), germanium on insulator (GOI), and the semiconductor substrate can be doped with conductive ions.
  • the substrate 1 is processed to form a plurality of semiconductor columns 10. As shown in FIG. 16, FIG. 17, FIG. 18, and FIG. 19, the plurality of semiconductor columns 10 are independently arranged, and adjacent semiconductor columns 10 are separated by an isolation layer 12.
  • the material of the isolation layer 12 includes silicon oxide, silicon nitride, or silicon oxynitride.
  • the top surfaces of the semiconductor column 10 and the isolation layer 12 are flush. In this embodiment, the height of the top surfaces of the semiconductor column 10 and the isolation layer 12 is a first height H1.
  • Step S120 removing part of the structure of each semiconductor column, and forming the remaining semiconductor columns into active columns, and forming contact holes above the active columns, wherein the aperture of the formed contact holes is the same as the diameter of the active columns, and the inner wall of the contact holes is aligned with the outer surface of the active columns.
  • the semiconductor pillars 10 are etched from the top surface to the bottom surface of the substrate 1 to remove part of the structure of each semiconductor pillar 10, and the top surface of each semiconductor pillar 10 is etched to a second height H2, where the second height H2 is lower than the first height H1, and a contact hole 13 is formed in the area where each semiconductor pillar 10 is removed.
  • the retained part of the structure of each semiconductor pillar 10 forms an active pillar 11, and the height of the top surface of the active pillar 11 is the second height H2.
  • the top surface of the formed active pillar 11 is lower than the top surface of the isolation layer 12, and the active pillar 11 and the isolation layer 12 have a height difference, and the height difference between the active pillar 11 and the isolation layer 12 self-aligns to form a contact hole 13 above each active pillar 11, and the top surface of the active pillar 11 is the bottom wall of the contact hole 13, and the aperture of the contact hole 13 is the same as the diameter of the active pillar 11.
  • the semiconductor pillar 10 can be etched by a dry etching process or a wet etching process.
  • Step S130 forming a contact pad in each contact hole, wherein the contact pad covers the top surface of the active pillar.
  • a contact pad 14 is formed in each contact hole 13, and the following implementation methods may be adopted:
  • a semiconductor material is deposited by any deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering to form a semiconductor layer 16, and the semiconductor layer 16 fills each contact hole 13 and covers the top surface of the isolation layer 12.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • sputtering to form a semiconductor layer 16
  • the semiconductor layer 16 fills each contact hole 13 and covers the top surface of the isolation layer 12.
  • the material of the semiconductor layer 16 may include one or more of silicon, germanium, silicon-germanium compounds and silicon-carbon compounds, and the material of the semiconductor layer 16 may be doped with conductive ions.
  • the semiconductor layer 16 is then etched back to remove a portion of the semiconductor material in each contact hole 13 and expose the top surface of the active pillar 11.
  • the semiconductor layer 16 retained in each contact hole 13 forms a contact pad 14, which covers the top surface of the active pillar 11 and a portion of the side wall at the bottom of the contact hole 13.
  • the etching depth of the semiconductor layer 16 is controlled according to the hole depth of the contact hole 13 (i.e., the height difference between the first height H1 and the second height H2) so that the thickness of the formed contact pad 14 is one tenth to one half of the height difference between the first height H1 and the second height H2.
  • the method for manufacturing the semiconductor structure of the present embodiment etches the top surface of the semiconductor column to a level lower than the top surface of the isolation layer to form an active column, and at the same time utilizes the height difference between the active column and the isolation layer to self-align and form a contact hole above the active column, and the alignment accuracy between the contact hole and the active column is high.
  • the method for manufacturing the semiconductor structure of the present embodiment does not require the use of a photolithography process for alignment, thereby reducing the difficulty of the process, saving process cost and process time, and improving process efficiency.
  • this embodiment is an explanation of the above-mentioned embodiment.
  • the etching rate of the edge of the semiconductor column 10 is less than the etching rate of the center of the semiconductor column 10
  • the edge height of the top of the active column 11 formed is greater than the center height of the active column 11, that is, the top surface of the active column 11 is a curved surface, which increases the contact area between the contact pad 14 and the top surface of the active column 11, and can reduce the contact resistance between the contact pad 14 and the active column 11, thereby improving the electrical performance of the formed semiconductor structure.
  • the etching rate gradually increases from the edge to the center of the semiconductor pillar 10 , so that the top surface of the formed active pillar 11 is an arc surface that gradually sinks downward from the edge to the center.
  • a method for manufacturing a semiconductor structure is provided in an exemplary embodiment of the present disclosure, including all steps of step S110 to step S130 in the above embodiment.
  • the difference between this embodiment and the above embodiment is that after step S130, the method for manufacturing a semiconductor structure in this embodiment further includes the following steps:
  • Step S140 forming a plurality of contact plugs, which are respectively disposed in the plurality of contact holes, and each contact plug fills an unfilled area of each contact hole.
  • Step S150 forming a plurality of storage structures, each of which is electrically connected to an active pillar via a contact plug and a contact pad.
  • the storage structure 30 formed in this embodiment may include at least one of a capacitor and a magnetic memory.
  • the plurality of storage structures 30 formed in this embodiment and the plurality of contact plugs 20 are connected one by one, and each storage structure 30 is electrically connected to the active pillar 11 through the contact plug 20 and the contact pad 14 .
  • a plurality of contact plugs 20 may be formed by the following implementations:
  • a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or a sputtering process is selected to deposit a conductive metal, and the conductive metal fills each contact hole 13 and the unfilled area and covers the top surface of the isolation layer 12 to form a conductive layer 17.
  • the conductive metal may include titanium nitride.
  • a mask layer (not shown in the figure) is then formed on the conductive layer 17, and a portion of the conductive layer 17 is removed by etching according to the mask layer, and the retained conductive layer 17 forms a plurality of independently arranged conductive pillars 18, and the bottom structure of each conductive pillar 18 is located in the contact hole 13 to fill the unfilled area of the contact hole 13, and a contact plug 20 is formed in the contact hole 13.
  • the top structure of each conductive pillar 18 is located above the isolation layer 12 and extends in a direction away from the top surface of the isolation layer 12 to form a lower electrode 31 of the storage structure 30.
  • a dielectric layer 32 is then formed by deposition through any of the above deposition processes.
  • the dielectric layer 32 covers the outer surface of the lower electrode 31 .
  • the material of the dielectric layer 32 includes an insulating material.
  • an upper electrode 33 is deposited by any of the above deposition processes, and the upper electrode 33 covers the outer surface of the dielectric layer 32.
  • the material of the upper electrode 33 may include titanium nitride.
  • the lower electrode 31, the dielectric layer 32 and the upper electrode 33 together form a storage structure 30, and the upper electrodes 33 of multiple storage structures 30 are connected into a whole.
  • the manufacturing method of the semiconductor structure of this embodiment simplifies the manufacturing process of the semiconductor structure.
  • the contact plug and the lower electrode of the storage structure are formed by the same conductive column.
  • the formed storage structure and the contact plug do not have the problem of alignment accuracy not meeting the requirements.
  • the semiconductor structure has high alignment accuracy, low contact resistance and good electrical performance.
  • a method for manufacturing a semiconductor structure is provided in an exemplary embodiment of the present disclosure.
  • the difference between this embodiment and the above embodiments is that in this embodiment, no contact plug is formed, and after step S130, a plurality of storage structures are directly formed.
  • a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or any deposition process of sputtering is selected to deposit a conductive metal, and the conductive metal covers the top surface of each contact pad 14, the uncovered sidewall of each contact hole 13, and the top surface of the isolation layer 12. Then, the conductive metal on the top surface of the isolation layer 12 is removed by etching back, and the conductive metal retained in each contact hole 13 forms a lower electrode 31, and the lower electrode 31 covers the top surface of the contact pad 14 and the uncovered sidewall of each contact hole 13.
  • the material of the lower electrode 31 may include titanium nitride.
  • a dielectric layer 32 is then formed by deposition through any of the above deposition processes, and the dielectric layer 32 covers the lower electrode 31 and the top surface of the isolation layer 12.
  • the material of the dielectric layer 32 includes an insulating material.
  • an upper electrode 33 is deposited by any of the above-mentioned deposition processes, and the upper electrode 33 covers the dielectric layer 32 and fills the unfilled area of each contact hole 13.
  • the material of the upper electrode 33 may include titanium nitride.
  • the lower electrode 31, the dielectric layer 32 and the upper electrode 33 form a storage structure 30 in each contact hole 13, and the upper electrodes 33 of multiple storage structures 30 are connected together.
  • the method for manufacturing the semiconductor structure of the present embodiment further simplifies the process steps, and forms a storage structure in the contact hole.
  • the storage structure and the contact pad are directly contacted and connected, and the contact resistance between the storage structure and the contact pad is smaller.
  • the main part of the storage structure is arranged in the contact hole, and the architecture of the semiconductor structure is more stable, and the semiconductor structure has better anti-tilting properties.
  • this embodiment is an explanation of the above embodiment.
  • it before forming the contact pad 14, it further includes: depositing a metal layer 19, the metal layer 19 at least covers the surface of the contact pad 14, and heat treating the metal layer 19 to form an interface layer 15 on the surface of the contact pad 14.
  • the material of the interface layer 15 includes metal silicide, and the metal silicide can be selected from at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi) or tungsten silicide (WSi).
  • the material of the interface layer 15 includes cobalt silicide.
  • the temperature of the heat treatment of cobalt silicide is lower than that of other metal silicides, which is conducive to reducing the heat treatment process budget.
  • cobalt silicide can be applied to semiconductor structures with smaller sizes without generating line width effects, and can improve the leakage and short circuit problems of semiconductor structures.
  • the line width effect refers to the fact that the resistance of metal silicide increases as the line width or contact area decreases.
  • the line width becomes too narrow, the temperature and time of the metal silicide phase change will be greatly increased; and too high an annealing temperature will aggravate the diffusion of silicon atoms, causing leakage or even short circuit problems. Therefore, as the semiconductor structure continues to become smaller, the metal silicide phase change is insufficient and the contact resistance increases.
  • the line width effect will reduce the performance of the semiconductor structure.
  • the thickness of the interface layer 15 is 5 nm to 15 nm.
  • the thickness of the interface layer 15 may be 5 nm, 7 nm, 9 nm, 11 nm, 13 nm or 15 nm.
  • the interface layer 15 is disposed between the contact pad 14 and the contact plug 20, reducing the contact resistance between the contact pad 14 and the contact plug 20, thereby improving the electrical performance of the semiconductor structure.
  • this embodiment is an explanation of the above embodiment.
  • This embodiment includes all the steps of the above embodiment.
  • the difference between this embodiment and the above embodiment is that step S110 of this embodiment includes the following steps:
  • the substrate 1 is first etched to form a plurality of first trenches 101 spaced apart from each other, and the first trenches 101 extend along a first direction D1 .
  • the substrate 1 is subjected to a second etching to form a plurality of second trenches 102 arranged at intervals, the second trenches 102 extending along a second direction D2, the first direction D1 intersecting the second direction D2.
  • the depth of the second trenches 102 is greater than the depth of the first trenches 101.
  • the first direction D1 is perpendicular to the second direction D2, and a plurality of first grooves 101 are arranged in parallel along the first direction D1, and a plurality of first grooves 101 are arranged at intervals along the second direction D2.
  • a plurality of second grooves 102 are arranged in parallel along the second direction D2, and a plurality of second grooves 102 are arranged at intervals along the first direction D1.
  • a plurality of first grooves 101 and a plurality of second grooves 102 intersect vertically, dividing the substrate 1 into a plurality of semiconductor pillars 10 arranged in an array.
  • a plurality of semiconductor pillars 10 are arranged in an array along the first direction D1 and the second direction D2.
  • the semiconductor pillar 10 is a rectangular pillar, and it can be understood that in other embodiments, the semiconductor pillar 10 may be a cylindrical pillar.
  • bit lines 50 are formed, each of which extends along the second direction D2.
  • the following implementation methods can be used to form a plurality of bit lines 50: First, an oxide layer (not shown in the figure) is formed by a thermal oxidation process, and the oxide layer covers the sidewalls of the semiconductor pillar 10, the bottom wall of the first trench 101, and the bottom wall of the second trench 102. Then, the oxide layer covering the bottom wall of the first trench 101 is removed, and metal elements are doped into the substrate 1 below the first trench 101. Then, the semiconductor structure is thermally treated to form a plurality of bit lines 50 below the semiconductor pillar 10. The plurality of bit lines 50 are correspondingly arranged below the plurality of columns of semiconductor pillars 10 arranged along the second direction D2, and adjacent bit lines 50 are separated by gaps in the second trench 102.
  • an isolation material is deposited to fill the gaps in the second trenches 102 between adjacent bit lines 50 to isolate adjacent bit lines 50 and avoid leakage or short circuit caused by bridging of adjacent bit lines 50.
  • the unfilled portion of the second trench 102 has the same depth as the first trench 101.
  • Each word line extends along the first direction D1 .
  • Any word line 40 covers the sidewalls of a row of semiconductor pillars 10 arranged along the first direction D1 .
  • the following implementation method can be used to form multiple word lines: deposit a conductive material to fill the unfilled areas of the first trench 101 and the second trench 102, and then etch the conductive material into multiple independently arranged word lines 40, and the multiple word lines 40 are located above the multiple bit lines 50.
  • an isolation material is deposited to fill the unfilled portions of the first trench 101 and the second trench 102 .
  • the isolation materials in the first trench 101 and the second trench 102 together form an isolation layer 12 .
  • any word line 40 covers the side wall of a row of active pillars 11 arranged along the first direction D1
  • any bit line 50 is arranged at the bottom of a column of active pillars 11 arranged along the second direction D2.
  • the word line 40 and the contact hole 13 are separated by the sufficiently thick active pillar 11, so as to avoid the word line 40 and the contact pad 14 and the contact plug 20 in the contact hole 13 being too close to each other and causing a short circuit, which is beneficial to improving the electrical performance of the semiconductor structure.
  • first, second, etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.
  • the height difference between the active column and the isolation layer is utilized to self-align and form a contact hole above the active column.
  • the alignment accuracy of the contact hole and the active column is high, the contact pad arranged in the contact hole has a large contact area and a small contact resistance, and the electrical performance of the semiconductor structure is better.

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Abstract

本公开提供一种半导体结构及其制作方法，涉及半导体技术领域，半导体结构包括，多个有源柱，相邻的有源柱之间设置有隔离层，有源柱的顶面低于隔离层的顶面；多个接触孔，一一对应设置于多个有源柱上方，且接触孔的孔径与有源柱的直径相同，接触孔的内壁与有源柱的外表面对齐；多个接触垫，分别对应设置在多个接触孔底部，且覆盖多个有源柱的顶面。

Description

半导体结构及其制作方法
本公开基于申请号为202211258357.0、申请日为2022年10月14日、申请名称为“半导体结构及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
随着半导体技术工艺节点的不断缩小，半导体器件的集成密度更高，且半导体器件日益精细化，对半导体器件的对准精度要求更高。
目前，在形成接触垫的制程中，通常采用光刻工艺，由于光刻工艺的限制，时常出现形成的接触垫和前层图案的对准精度不能满足需求的问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构及其制作方法。
本公开的第一方面提供了一种半导体结构，所述半导体结构包括：
多个有源柱，相邻的所述有源柱之间设置有隔离层，所述有源柱的顶面低于所述隔离层的顶面；
多个接触孔，一一对应设置于多个所述有源柱上方，且所述接触孔的孔径与所述有源柱的直径相同，所述接触孔的内壁与所述有源柱的外表面对齐；
多个接触垫，分别对应设置在多个所述接触孔底部，且覆盖多个所述有源柱的顶面。
其中，所述半导体结构还包括：多个存储结构和多个接触插塞，每个所述接触插塞填充每个所述接触孔未被填充的区域，每个所述存储结构通过所述接触插塞和所述接触垫与所述有源柱电连接。
其中，所述半导体结构还包括：界面层，所述界面层位于所述接触垫和所述接触插塞之间，所述界面层的厚度为5nm-15nm。
其中，所述有源柱顶部的边缘高度大于中心高度。
其中，所述隔离层具有第一高度，所述有源柱具有第二高度，所述第二高度低于所述第一高度，每个所述接触垫的厚度为所述第一高度和所述第二高度的高度差的十分之一到二分之一。
其中，多个所述有源柱沿第一方向、第二方向呈阵列排布，所述第一方向和所述第二方向相交，所述半导体结构还包括：
多条字线，每条所述字线沿所述第一方向延伸，任意一条所述字线包覆沿所述第一方向排列的一行所述有源柱的侧壁；
所述有源柱的顶面高于所述字线的顶面。
其中，所述半导体结构还包括：
多条位线，每条所述位线沿所述第二方向延伸，任意一条所述位线设置在沿所述第二方向排列的一列所述有源柱的底部。
本公开的第二方面提供了一种半导体结构的制作方法，所述方法包括：
提供衬底，在所述衬底上形成间隔设置的多个半导体柱，以及设置在相邻所述半导体柱之间的隔离层，所述半导体柱和所述隔离层的顶面平齐；
去除每个所述半导体柱的部分结构，剩余的所述半导体柱形成有源柱，同时在所 述有源柱的上方形成接触孔，形成的所述接触孔的孔径与所述有源柱的直径相同，且所述接触孔的内壁与所述有源柱的外表面对齐；
在每个所述接触孔中形成接触垫，所述接触垫覆盖所述有源柱的顶面。
其中，所述隔离层具有第一高度，去除每个所述半导体柱的部分结构，包括：
将每个所述半导体柱的顶面刻蚀至第二高度，每个所述半导体柱被去除的区域形成所述接触孔，所述第二高度低于所述第一高度。
其中，形成所述接触垫，包括：形成填充满每个所述接触孔的半导体层，回刻所述半导体层形成所述接触垫，所述接触垫的厚度为所述第一高度和所述第二高度的高度差的十分之一到二分之一。
其中，所述半导体结构的制作方法，还包括：
形成多个接触插塞，分别对应设置在多个所述接触孔中，每个所述接触插塞填充每个所述接触孔未被填充的区域；
形成多个存储结构，每个所述存储结构通过所述接触插塞和所述接触垫与所述有源柱电连接。
其中，在形成所述接触孔之前，还包括：沉积金属层，所述金属层至少覆盖所述接触垫的表面，热处理所述金属层以在所述接触垫的表面形成界面层。
其中，形成多个所述半导体柱，包括：
对所述衬底进行第一刻蚀，以形成多条间隔设置的第一沟槽，所述第一沟槽沿第一方向延伸；
对所述衬底进行第二刻蚀，以形成多条间隔设置的第二沟槽，所述第二沟槽沿第二方向延伸，所述第一方向和所述第二方向相交；
多条所述第一沟槽和多条所述第二沟槽将所述衬底划分成阵列排布的多个所述半导体柱。
其中，所述半导体结构的制作方法，还包括：
形成多条字线，每条所述字线沿所述第一方向延伸，任意一条所述字线包覆沿所述第一方向排列的一行所述有源柱的侧壁；
所述有源柱的顶面高于所述字线的顶面。
其中，所述半导体结构的制作方法，还包括：
形成多条位线，每条所述位线沿所述第二方向延伸，任意一条所述位线设置在沿所述第二方向排列的一列所述有源柱的底部。
本公开提供的半导体结构及其制作方法中，利用有源柱和隔离层的高度差在有源柱的上方自对准形成接触孔，接触孔和有源柱的对准精度高，接触孔中设置的接触垫接触面积大、接触电阻小，半导体结构的电性能更好。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的俯视图。
图2是根据一示例性实施例示出的半导体结构的a-a截面的剖面图。
图3是根据一示例性实施例示出的半导体结构的a-a截面的剖面图。
图4是根据一示例性实施例示出的半导体结构的a-a截面的剖面图。
图5是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图6是根据一示例性实施例示出的衬底的俯视图。
图7是根据一示例性实施例示出的多个半导体柱的俯视图。
图8是图7的a-a截面的剖面图。
图9是图7的b-b截面的剖面图。
图10是图7的c-c截面的剖面图。
图11是图7的d-d截面的剖面图。
图12是根据一示例性实施例示出的形成位线的a-a截面的剖面图。
图13是根据一示例性实施例示出的形成位线的b-b截面的剖面图。
图14是根据一示例性实施例示出的形成位线的c-c截面的剖面图。
图15是根据一示例性实施例示出的形成位线的d-d截面的剖面图。
图16是根据一示例性实施例示出的形成隔离层的a-a截面的剖面图。
图17是根据一示例性实施例示出的形成隔离层的b-b截面的剖面图。
图18是根据一示例性实施例示出的形成隔离层的c-c截面的剖面图。
图19是根据一示例性实施例示出的形成隔离层的d-d截面的剖面图。
图20是根据一示例性实施例示出的形成接触孔的a-a截面的剖面图。
图21是根据一示例性实施例示出的形成接触孔的c-c截面的剖面图。
图22是根据一示例性实施例示出的形成半导体层的a-a截面的剖面图。
图23是根据一示例性实施例示出的形成接触垫的a-a截面的剖面图。
图24是根据一示例性实施例示出的形成导电层的a-a截面的剖面图。
图25是根据一示例性实施例示出的形成接触插塞和下电极的a-a截面的剖面图。
图26是根据一示例性实施例示出的形成介电层的a-a截面的剖面图。
图27是根据一示例性实施例示出的形成界面层的a-a截面的剖面图。
图28是根据一示例性实施例示出的形成下电极的a-a截面的剖面图。
图29是根据一示例性实施例示出的形成介电层的a-a截面的剖面图。
附图标记：
1、衬底；10、半导体柱；101、第一沟槽；102、第二沟槽；11、有源柱；12、隔离层；13、接触孔；14、接触垫；15、界面层；16、半导体层；17、导电层；18、导电柱；19、金属层；20、接触插塞；30、存储结构；31、下电极；32、介电层；33、上电极；40、字线；50、位线；
H1、第一高度；H2、第二高度；D1、第一方向；D2、第二方向。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
目前，刻蚀衬底形成半导体柱后，在半导体柱之间形成隔离层，隔离层的顶面和半导体柱的顶面平齐。为了避免半导体柱暴露在制程环境中自然氧化降低半导体结构的品质，在衬底上形成介质层避免半导体柱氧化。因此，在相关技术中，形成接触垫的制程中，采用光照-刻蚀工艺在介质层中形成接触孔，暴露出半导体柱的表面，然后在接触孔中形成接触垫。但是采用光照-刻蚀工艺形成接触孔的方式，在形成接触孔的过程中可能出现偏移，无法保证形成的接触孔和半导体柱完全对准，比如可能出现接触孔仅能暴露出半导体柱的部分顶面的问题，导致在接触孔中形成的接触垫和半导体柱的接触面积小、接触电阻大，造成半导体结构的电性能下降，影响半导体结构的品质和良率。
并且，随着半导体器件尺寸日益减小，单位面积上集成的半导体器件越来越多，半导体器件的密度也逐渐加大，接触孔的尺寸不断减小，这也导致在半导体柱上形成接触孔的难度日益增加。
本实施例提供了一种半导体结构及其制作方法，半导体结构的有源柱的顶面比隔离层的顶面低，利用有源柱和隔离层的高度差在有源柱的上方自对准形成接触孔，接触孔中设置有接触垫，接触垫覆盖有源柱的顶面和有源柱接触连接，接触垫和有源柱的对准精度高、接触面积大，接触垫和有源柱之间的接触电阻小，半导体结构的电性能好。
本公开示例性实施例提供了一种半导体结构，如图1、图2、图3、图4所示，参照图20、图26，半导体结构包括多个有源柱11，相邻的有源柱11之间设置有隔离层12，有源柱11的顶面低于隔离层12的顶面。半导体结构还包括多个接触孔13和多个接触垫14，多个接触孔13一一对应设置于多个有源柱11的上方，且每个接触孔13的孔径与其对应的有源柱11的直径相同，接触孔13的内壁与有源柱11的外表面对齐，多个接触垫14分别一一对应设置在多个接触孔13底部，且多个接触垫14分别一一对应覆盖多个有源柱11的顶面。
参照图2、图3、图4所示，有源柱11可以为独立设置的圆柱或矩柱，有源柱11的材料包括半导体材料，半导体材料可以包括硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；半导体衬底的材料也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)，半导体材料中可以掺杂有导电离子。
参照图2、图3、图4所示，相邻的有源柱11通过隔离层12隔开，隔离层12的材料包括绝缘材料。比如，隔离层12的材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。
如图2、图3、图4所示，参照图20、图26，隔离层12的顶面比有源柱11的顶面的高度高，有源柱11和隔离层12具有高度差，有源柱11和隔离层12的高度差在每个有源柱11的上方自对准形成接触孔13，接触孔13由有源柱11的顶面以及位于有源柱11的顶面上的隔离层12围合而成，接触孔13的孔径与有源柱11的直径相同，接触孔13的内壁与有源柱11的外表面对齐，有源柱11的顶面作为接触孔13的底壁。
如图2、图3、图4所示，参照图20、图26，每个接触孔13中设置有接触垫14，接触垫14覆盖有源柱11的顶面并填充接触孔13的部分区域，接触垫14和有源柱11的顶面接触连接。本实施例中，接触垫14的材料包括半导体材料，接触垫14的材料可以包括硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种，接触垫14的材料中可以掺杂有导电离子。接触垫14和有源柱11的材料均包括半导体材料，接触垫14和有源柱11的接触电阻小。
本实施例的半导体结构，利用有源柱11和隔离层12的高度差在有源柱11的上方自对准形成接触孔13，以有源柱11的顶面作为接触孔13的底壁，以使接触孔13和有源柱11完全对准，确保接触孔13中设置的接触垫14和有源柱11的顶面具有较大的接触面积，减小接触垫14和有源柱11之间的接触电阻，确保半导体结构具有良好的电性能，有利于确保半导体结构具有高良率。
在一些实施例中，如图3、图4所示，参照图20、图26，半导体结构还包括多个存储结构30和多个接触插塞20，每个接触插塞20填充每个接触孔13未被填充的区域，每个存储结构30通过接触插塞20和接触垫14与有源柱11电连接。
如图3、图4所示，参照图20、图26，多个接触插塞20独立设置，多个接触插塞20和多个接触孔13一一对应设置，接触插塞20覆盖接触垫14的顶面和接触垫14接触连接，并与其对应的接触孔13未被填充的区域，接触插塞20的顶面和隔离层12的顶面平齐，或，接触插塞20的顶面高于隔离层12的顶面，接触插塞20和接触垫 14的接触面积大、对准精度高。本实施例中，接触插塞20的材料可以包括导电金属，示例性的，接触插塞20的材料可以包括氮化钛。
如图3所示，参照图20，多个存储结构30和多个接触插塞20一一对应连接，每个存储结构30通过接触插塞20和接触垫14与有源柱11电连接。在本实施例中，存储结构30可以包括电容器、磁存储器等。
如图3所示，以存储结构30为电容器为示例对本实施例进行说明，存储结构30包括设置在接触插塞20上的下电极31、覆盖下电极31的表面的介电层32以及覆盖介电层32的表面的上电极33。
如图3所示，参照图20，接触插塞20的顶面高于隔离层12的顶面，每个接触插塞20的部分结构位于接触孔13中，每个接触插塞20的另一部分结构位于隔离层12的上方。
本实施例以每个接触插塞20位于隔离层12上方的部分结构作为存储结构30的下电极31，简化了形成存储结构30的工艺过程，降低了半导体结构的制作难度。并且，本实施例的半导体结构以每个接触插塞20位于隔离层12上方的部分结构作为存储结构30的下电极31，能够避免存储结构30和接触插塞20对不准的问题，确保存储结构30和接触插塞20正对设置，半导体结构具有高对准精度，半导体结构的接触电阻小、电性能好。
在另一些实施例中，参照图4所示，半导体结构不包括接触插塞20，存储结构30和接触垫14直接连接。
如图4所示，参照图26，以存储结构30为电容器为示例对本实施例进行说明，本实施例中的存储结构30包括下电极31、介电层32和上电极33，下电极31覆盖接触垫14的顶面以及位于接触垫14上方的接触孔13的侧壁，介电层32覆盖下电极31的表面，上电极33覆盖介电层32的表面。在本实施例中，存储结构30的上电极33的顶面高于隔离层12的顶面，多个存储结构30的上电极33连接成整体。
本实施例的半导体结构，存储结构30的主体部分设置在接触孔13中，仅部分下电极31设置在隔离层12上方，存储结构30设置的更加稳定，半导体结构的抗倾倒性更好。
在一些实施例中，如图2、图3、图4所示，有源柱11顶部的边缘的高度大于有源柱11顶部的中心高度，以增大接触垫14和有源柱11的接触面积，进一步减小接触垫14和有源柱11的接触电阻，提高半导体结构的电性能。
本实施例中，自有源柱11的顶面的边缘向中心的方向，有源柱11的高度逐渐减小，有源柱11的顶面为自边缘向中心方向逐渐向下凹陷的弧面，不仅能增大接触垫14和有源柱11的接触面积，还能保证接触垫14和有源柱11的顶面紧密贴合，减小接触垫14和有源柱11的接触电阻。
在一些实施例中，如图2、图3、图4所示，隔离层12具有第一高度H1，有源柱11具有第二高度H2，第二高度H2低于第一高度H1，其中，第一高度H1、第二高度H2可根据半导体结构的设计和尺寸等因素调整，但不受其限制。
每个接触垫14的厚度为第一高度H1和第二高度H2的高度差的十分之一到二分之一。以确保接触垫14设置在接触插塞20和有源柱11之间能够降低接触插塞20和有源柱11的接触电阻，且接触孔13中设置了接触垫14后，接触孔13中的剩余空间可以用于设置接触插塞20，以使接触插塞20和接触垫14连接的更加稳固，提高半导体结构的稳定性。
接触垫14的厚度可以为第一高度H1和第二高度H2的高度差的十分之一、八分之一、五分之一、三分之一、二分之一，或者接触垫14的厚度为第一高度H1和第二高度H2的高度差的十分之一到二分之一之间的其它数值。在本实施例中，每个接触 垫14的厚度为第一高度H1和第二高度H2的高度差的五分之一到二分之一。
示例性的，第一高度H1和第二高度H2的高度差为50nm-100nm，接触垫14的厚度可以为20nm-50nm。比如，第一高度H1和第二高度H2的高度差为50nm，接触垫14的厚度为20nm；第一高度H1和第二高度H2的高度差为60nm，接触垫14的厚度为30nm；第一高度H1和第二高度H2的高度差为70nm，接触垫14的厚度为30nm；第一高度H1和第二高度H2的高度差为70nm，接触垫14的厚度为30nm；第一高度H1和第二高度H2的高度差为90nm，接触垫14的厚度为40nm；第一高度H1和第二高度H2的高度差为100nm，接触垫14的厚度可以为20nm；或者，第一高度H1和第二高度H2的高度差为100nm，接触垫14的厚度可以为50nm。
根据一个示例性实施例，示出了一种半导体结构，本实施例的半导体结构包括上述实施例的全部结构，本实施例和上述实施例的区别之处在于，如图1、图2、图3、图4所示，半导体结构还包括界面层15，界面层15位于接触垫14和接触插塞20之间。其中，界面层15的材料包括金属硅化物，界面层15设置在接触垫14和接触插塞20之间，用于降低接触垫14和接触插塞20之间的接触电阻，从而提高半导体结构的电性能。示例性的，界面层15的材料可以包括钴硅化物(CoSi)、钛硅化物(TiSi)、镍硅化物(NiSi)或钨硅化物(WSi)中的至少一种。本实施例中，界面层15的材料包括钴硅化物。
在实施例中，界面层15的厚度为5nm-15nm。示例性的，界面层15的厚度可以为5nm、7nm、9nm、11nm、13nm或15nm。
根据一个示例性实施例，示出了一种半导体结构，如图1、图2、图3、图4所示，本实施例的半导体结构包括多个有源柱11，多个有源柱11沿第一方向D1、第二方向D2呈阵列排布，第一方向D1和第二方向D2相交。相邻的有源柱11之间设置有隔离层12，有源柱11的顶面低于隔离层12的顶面。半导体结构还包括多个接触孔13和多个接触垫14，多个接触孔13一一对应设置于多个有源柱11上方，且接触孔13的孔径与有源柱11的直径相同，接触孔13的内壁与有源柱11的外表面对齐，多个接触垫14分别对应设置在多个接触孔13的底部，且覆盖多个有源柱11的顶面。
如图1、图2、图3、图4所示，参照图20、图26，半导体结构还包括多条字线40，每条字线40沿第一方向D1延伸，任意一条字线40包覆沿第一方向D1排列的一行有源柱11的侧壁；有源柱11的顶面高于字线40的顶面。示例性的，有源柱11的顶面可以比字线40的顶面高50nm、60nm、70nm、80nm、90nm或100nm。
字线40设置在接触孔13的下方，字线40和接触孔13通过字线40上方的有源柱11隔开，本实施例中，有源柱11的顶面比字线40的顶面高50nm-100nm，确保字线40和接触孔13通过足够厚的有源柱11隔开，避免字线40和接触孔13中的接触垫14和接触插塞20距离过近发生短路，提高了半导体结构的电性能，有利于延迟半导体结构的工作寿命。
如图1、图2、图3、图4所示，参照图20、图26，半导体结构还包括多条位线50，每条位线50沿第二方向D2延伸，任意一条位线50设置在沿第二方向D2排列的一列有源柱11的底部。
本实施例的半导体结构可以应用于动态随机存储器(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random Access Memory，MRAM)、相变随机存储器(Phase change Random Access Memory，PRAM)等。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图5所示，图5示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图6-图29 为半导体结构的制作方法的各个阶段的示意图，下面结合图6-图29并参照图1-图4对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，方法包括以下步骤：
步骤S110：提供衬底，在衬底上形成间隔设置的多个半导体柱，以及设置在相邻半导体柱之间的隔离层，半导体柱和隔离层的顶面平齐。
如图6所示，衬底1可以是半导体衬底，半导体衬底的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；半导体衬底的材料也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)，半导体衬底可以掺杂有导电离子。
处理衬底1，形成多个半导体柱10。如图16、图17、图18、图19所示，多个半导体柱10独立设置，相邻的半导体柱10通过隔离层12隔开，隔离层12的材料包括氧化硅、氮化硅或氮氧化硅。半导体柱10和隔离层12的顶面平齐，本实施例中，半导体柱10和隔离层12的顶面的高度为第一高度H1。
步骤S120：去除每个半导体柱的部分结构，剩余的半导体柱形成有源柱，同时在有源柱的上方形成接触孔，形成的接触孔的孔径与有源柱的直径相同，且接触孔的内壁与有源柱的外表面对齐。
如图20、图21所示，参照图16、图18，自衬底1的顶面向底面的方向刻蚀半导体柱10，去除每个半导体柱10的部分结构，将每个半导体柱10的顶面刻蚀至第二高度H2，第二高度H2低于第一高度H1，在每个半导体柱10被去除的区域形成接触孔13，每个半导体柱10被保留的部分结构形成有源柱11，有源柱11的顶面的高度为第二高度H2。
如图20、图21所示，形成的有源柱11的顶面低于隔离层12的顶面，有源柱11和隔离层12具有高度差，有源柱11和隔离层12的高度差在每个有源柱11的上方自对准形成接触孔13，有源柱11的顶面为接触孔13的底壁，接触孔13的孔径和有源柱11的直径相同。本实施例中刻蚀半导体柱10可以采用干法刻蚀工艺或湿法刻蚀工艺。
步骤S130：在每个接触孔中形成接触垫，接触垫覆盖有源柱的顶面。
在本实施例中，在每个接触孔13中形成接触垫14，可以采用以下实施方式：
如图22所示，参照图20，首先，选用化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)或溅镀(sputtering)中的任一种沉积工艺沉积半导体材料形成半导体层16，半导体层16填充满每个接触孔13并覆盖隔离层12的顶面。示例性的，半导体层16的材料可以包括硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种，半导体层16的材料中可以掺杂有导电离子。
如图23所示，参照图22，然后，回刻半导体层16，去除每个接触孔13中的部分半导体材料并暴露出有源柱11的顶面，每个接触孔13中被保留的半导体层16形成接触垫14，接触垫14覆盖有源柱11的顶面以及接触孔13的底部的部分侧壁。
本实施例中，在回刻半导体层16形成接触垫14的制程中，根据接触孔13的孔深(也即第一高度H1和第二高度H2的高度差)控制半导体层16的回刻深度，以使形成的接触垫14的厚度为第一高度H1和第二高度H2的高度差的十分之一到二分之一。
本实施例的半导体结构的制作方法，将半导体柱的顶面刻蚀至低于隔离层的顶面 形成有源柱，同时利用有源柱和隔离层的高度差在有源柱的上方自对准形成接触孔，接触孔和有源柱的对准精度高；本实施例的半导体结构的制作方法，无需采用光刻工艺对准，降低了制程难度、节约了制程成本和制程时间，提高了制程效率。
根据一示例性实施例，本实施例是对上述实施例的说明，本实施例中，参照图16、图18、图20、图21所示，在步骤S120去除每个半导体柱10的部分结构的过程中，刻蚀半导体柱10的边缘的刻蚀速率小于刻蚀半导体柱10的中心的刻蚀速率，形成的有源柱11的顶部的边缘高度大于有源柱11的中心高度，也即，有源柱11的顶面为曲面，增大了接触垫14和有源柱11的顶面的接触面积，能够降低接触垫14和有源柱11的接触电阻，从而提高形成的半导体结构的电性能。
比如，在本实施例中，刻蚀半导体柱10的过程中，自半导体柱10的边缘向中心方向，刻蚀速率逐渐增大，以使形成的有源柱11的顶面为自边缘向中心方向逐渐向下凹陷的弧面。
根据一示例性实施例，本公开示例性的实施例中提供一种半导体结构的制作方法，包括上述实施例中步骤S110-步骤S130的全部步骤，本实施例和上述实施例的区别之处在于，在步骤S130之后，本实施例的半导体结构的制作方法，还包括以下步骤：
步骤S140：形成多个接触插塞，分别对应设置在多个接触孔中，每个接触插塞填充每个接触孔未被填充的区域。
步骤S150：形成多个存储结构，每个存储结构通过接触插塞和接触垫与有源柱电连接。
参照图3所示，在本实施例形成的存储结构30可以包括电容器、磁存储器中的至少一种。参照图3所示，在本实施例形成的多个存储结构30和多个接触插塞20一一对应连接，每个存储结构30通过接触插塞20和接触垫14与有源柱11电连接。
下面，以存储结构30为电容器对本实施例的制作方法进行说明。
本实施例中，形成多个接触插塞20，可以采用以下实施方式：
如图24所示，参照图23，首先，选用化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺沉积导电金属，导电金属填充每个接触孔13，未被填充的区域并覆盖隔离层12的顶面，形成导电层17。本实施例中，导电金属可以包括氮化钛。
如图25所示，参照图24，然后，在导电层17上形成掩膜层(图中未示出)，根据掩膜层刻蚀去除部分导电层17，被保留的导电层17形成多个独立设置的导电柱18，每个导电柱18的底部结构位于接触孔13中填充接触孔13中未被填充的区域，在接触孔13中形成接触插塞20。如图23所示，每个导电柱18的顶部结构位于隔离层12的上方，并沿远离隔离层12的顶面的方向延伸，形成为存储结构30的下电极31。
如图26所示，参照图25，然后，通过上述任一种沉积工艺沉积形成介电层32，介电层32覆盖下电极31的外表面，介电层32的材料包括绝缘材料。
如图3所示，参照图26，接着，通过上述任一种沉积工艺沉积形成上电极33，上电极33覆盖介电层32的外表面，上电极33的材料可以包括氮化钛。如图3所示，下电极31、介电层32和上电极33共同形成存储结构30，多个存储结构30的上电极33连接成一个整体。
本实施例的半导体结构的制作方法，简化了半导体结构的制作工艺，接触插塞和存储结构的下电极由同一导电柱形成，形成的存储结构和接触插塞不存在对准精度不符合要求的问题，半导体结构的对准精度高、接触电阻小、电性能好。
根据一示例性实施例，本公开示例性的实施例中提供一种半导体结构的制作方法，本实施例和上述实施例的区别之处在于，本实施例中不形成接触插塞，在步骤S130 之后，直接形成多个存储结构。
在本实施例中，如图28所示，参照图27，形成接触垫14之后，选用化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺沉积导电金属，导电金属覆盖每个接触垫14的顶面、每个接触孔13未被覆盖的侧壁以及隔离层12的顶面。然后回刻去除隔离层12的顶面上的导电金属，每个接触孔13中被保留的导电金属形成下电极31，下电极31覆盖接触垫14的顶面以及每个接触孔13未被覆盖的侧壁。本实施例中，下电极31的材料可以包括氮化钛。
如图29所示，参照图28，然后，通过上述任一种沉积工艺沉积形成介电层32，介电层32覆盖下电极31以及隔离层12的顶面。介电层32的材料包括包括绝缘材料。
如图4所示，参照图29，然后，通过上述任一种沉积工艺沉积形成上电极33，上电极33覆盖介电层32并填充每个接触孔13未被填充的区域。本实施例中，上电极33的材料可以包括氮化钛。如图4所示，下电极31、介电层32和上电极33在每个接触孔13中形成存储结构30，多个存储结构30的上电极33连接在一起。
本实施例的半导体结构的制作方法，进一步简化了工艺步骤，在接触孔中形成存储结构，存储结构和接触垫直接接触连接，存储结构和接触垫的接触电阻更小，并且，存储结构的主体部分设置在接触孔中，半导体结构的架构更加稳定，半导体结构的抗倾倒性更好。
根据一示例性实施例，本实施例是对上述实施例的说明，本实施例中，如图2所示，参照图23，在形成接触垫14之前，还包括：沉积金属层19，金属层19至少覆盖接触垫14的表面，热处理金属层19以在接触垫14的表面形成界面层15。界面层15的材料包括金属硅化物，金属硅化物可以选自钴硅化物(CoSi)、钛硅化物(TiSi)、镍硅化物(NiSi)或钨硅化物(WSi)中的至少一种。
参照图2所示，界面层15的材料包括钴硅化物，在热处理的步骤中，热处理钴硅化物的温度相比于热处理其它金属硅化物的温度低，有利于降低热处理工艺预算。同时钴硅化物可以应用于尺寸更小的半导体结构中而不会产生线宽效应，能够改善半导体结构的漏电和短路的问题。
其中，线宽效应是指金属硅化物的电阻会随着线宽或接触面积的减小而增加。当线宽变得过窄时，金属硅化物相变的温度和时间将大大增加；而过高的退火温度会加剧硅原子的扩散，从而造成漏电甚至短路的问题。因此随着半导体结构的不断变小，会出现金属硅化物相变不充分而使接触电阻增加的现象。线宽效应会降低半导体结构的性能。
参照图2所示，在实施例中，界面层15的厚度为5nm-15nm。比如，界面层15的厚度可以为5nm、7nm、9nm、11nm、13nm或15nm。界面层15设置在接触垫14和接触插塞20之间，降低了接触垫14和接触插塞20之间的接触电阻，从而提高了半导体结构的电性能。
根据一示例性实施例，本实施例是对上述实施例的说明，本实施例包括上述实施例的全部步骤，本实施例和上述实施例的区别之处在于，本实施例的步骤S110包括以下步骤：
如图7所示，参照图6，首先，对衬底1进行第一刻蚀，以形成多条间隔设置的第一沟槽101，第一沟槽101沿第一方向D1延伸。
然后，对衬底1进行第二刻蚀，以形成多条间隔设置的第二沟槽102，第二沟槽102沿第二方向D2延伸，第一方向D1和第二方向D2相交。本实施例中，第二沟槽102的深度大于第一沟槽101的深度。
如图7、图8、图9、图10、图11所示，第一方向D1和第二方向D2垂直，多条第一沟槽101沿第一方向D1并列设置，多条第一沟槽101沿第二方向D2间隔设 置。多条第二沟槽102沿第二方向D2并列设置，且多条第二沟槽102沿第一方向D1间隔设置。多条第一沟槽101与多条第二沟槽102垂直交叉，将衬底1划分成阵列排布的多个半导体柱10。多个半导体柱10沿第一方向D1和第二方向D2阵列。在本实施例中，半导体柱10为矩柱，可以理解的是，在其它实施例中，半导体柱10可以为圆柱。
然后，形成多条位线50，每条位线50沿第二方向D2延伸。
如图12、图13、图14、图15所示，参照图8、图9、图10、图11，形成多条位线50可以采用以下实施方式：首先，通过热氧化工艺形成氧化层(图中未示出)，氧化层覆盖半导体柱10的侧壁、第一沟槽101的底壁以及第二沟槽102的底壁。然后，去除覆盖在第一沟槽101的底壁的氧化层，向第一沟槽101的下方的衬底1中掺杂金属元素，接着热处理半导体结构，在半导体柱10下方形成多条位线50，多条位线50对应设置在沿第二方向D2排布的多列半导体柱10的下方，相邻的位线50被第二沟槽102中的间隙隔开。
如图12、图13、图14、图15所示，形成多条位线50后，沉积隔离材料填充相邻的位线50之间的第二沟槽102中的间隙，以隔离相邻的位线50，避免相邻的位线50桥接导致漏电或短路的问题。填充隔离材料后，第二沟槽102未被填充的部分和第一沟槽101的深度相同。
接着，形成多条字线40，每条字线沿第一方向D1延伸，任意一条字线40包覆沿第一方向D1排列的一行半导体柱10的侧壁。
如图16、图17、图18、图19所示，参照图12、图13、图14、图15，形成多条字线可以采用以下实施方式：沉积导电材料填充第一沟槽101和第二沟槽102未被填充的区域，然后将导电材料刻蚀成多条独立设置的字线40，多条字线40位于多条位线50的上方。
接着，沉积隔离材料填充第一沟槽101和第二沟槽102未被填充的部分，第一沟槽101和第二沟槽102中的隔离材料共同形成隔离层12。
在本实施例中，刻蚀去除每个半导体柱10的部分结构，形成有源柱11后，形成的有源柱11的顶面高于字线40的顶面。基于本实施例形成的制作方法形成的半导体结构，任意一条字线40包覆沿第一方向D1排列的一行有源柱11的侧壁，任意一条位线50设置在沿第二方向D2排列的一列有源柱11的底部。字线40和接触孔13通过足够厚的有源柱11隔开，避免字线40和接触孔13中的接触垫14和接触插塞20的距离过近发生短路，有利于提高了半导体结构的电性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描 述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法中，利用有源柱和隔离层的高度差在有源柱的上方自对准形成接触孔，接触孔和有源柱的对准精度高，接触孔中设置的接触垫接触面积大、接触电阻小，半导体结构的电性能更好。

Claims (15)

  1. 一种半导体结构，包括：
    多个有源柱，相邻的所述有源柱之间设置有隔离层，所述有源柱的顶面低于所述隔离层的顶面；
    多个接触孔，一一对应设置于多个所述有源柱上方，且所述接触孔的孔径与所述有源柱的直径相同，所述接触孔的内壁与所述有源柱的外表面对齐；
    多个接触垫，分别对应设置在多个所述接触孔底部，且覆盖多个所述有源柱的顶面。
  2. 根据权利要求1所述的半导体结构，还包括多个存储结构和多个接触插塞，每个所述接触插塞填充每个所述接触孔未被填充的区域，每个所述存储结构通过所述接触插塞和所述接触垫与所述有源柱电连接。
  3. 根据权利要求2所述的半导体结构，还包括界面层，所述界面层位于所述接触垫和所述接触插塞之间，所述界面层的厚度为5nm-15nm。
  4. 根据权利要求1所述的半导体结构，其中，所述有源柱顶部的边缘高度大于中心高度。
  5. 根据权利要求1所述的半导体结构，其中，所述隔离层具有第一高度，所述有源柱具有第二高度，所述第二高度低于所述第一高度，每个所述接触垫的厚度为所述第一高度和所述第二高度的高度差的十分之一到二分之一。
  6. 根据权利要求1所述的半导体结构，其中，多个所述有源柱沿第一方向、第二方向呈阵列排布，所述第一方向和所述第二方向相交，所述半导体结构还包括：
    多条字线，每条所述字线沿所述第一方向延伸，任意一条所述字线包覆沿所述第一方向排列的一行所述有源柱的侧壁；
    所述有源柱的顶面高于所述字线的顶面。
  7. 根据权利要求6所述的半导体结构，还包括多条位线，每条所述位线沿所述第二方向延伸，任意一条所述位线设置在沿所述第二方向排列的一列所述有源柱的底部。
  8. 一种半导体结构的制作方法，所述方法包括：
    提供衬底，在所述衬底上形成间隔设置的多个半导体柱，以及设置在相邻所述半导体柱之间的隔离层，所述半导体柱和所述隔离层的顶面平齐；
    去除每个所述半导体柱的部分结构，剩余的所述半导体柱形成有源柱，同时在所述有源柱的上方形成接触孔，形成的所述接触孔的孔径与所述有源柱的直径相同，且所述接触孔的内壁与所述有源柱的外表面对齐；
    在每个所述接触孔中形成接触垫，所述接触垫覆盖所述有源柱的顶面。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述隔离层具有第一高度，去除每个所述半导体柱的部分结构，包括：
    将每个所述半导体柱的顶面刻蚀至第二高度，每个所述半导体柱被去除的区域形成所述接触孔，所述第二高度低于所述第一高度。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，形成所述接触垫，包括： 形成填充满每个所述接触孔的半导体层，回刻所述半导体层形成所述接触垫，所述接触垫的厚度为所述第一高度和所述第二高度的高度差的十分之一到二分之一。
  11. 根据权利要求8所述的半导体结构的制作方法，所述方法，还包括：
    形成多个接触插塞，分别对应设置在多个所述接触孔中，每个所述接触插塞填充每个所述接触孔未被填充的区域；
    形成多个存储结构，每个所述存储结构通过所述接触插塞和所述接触垫与所述有源柱电连接。
  12. 根据权利要求11所述的半导体结构的制作方法，在形成所述接触孔之前，还包括：沉积金属层，所述金属层至少覆盖所述接触垫的表面，热处理所述金属层以在所述接触垫的表面形成界面层。
  13. 根据权利要求8所述的半导体结构的制作方法，其中，形成多个所述半导体柱，包括：
    对所述衬底进行第一刻蚀，以形成多条间隔设置的第一沟槽，所述第一沟槽沿第一方向延伸；
    对所述衬底进行第二刻蚀，以形成多条间隔设置的第二沟槽，所述第二沟槽沿第二方向延伸，所述第一方向和所述第二方向相交；
    多条所述第一沟槽和多条所述第二沟槽将所述衬底划分成阵列排布的多个所述半导体柱。
  14. 根据权利要求13所述的半导体结构的制作方法，所述方法，还包括：
    形成多条字线，每条所述字线沿所述第一方向延伸，任意一条所述字线包覆沿所述第一方向排列的一行所述有源柱的侧壁；
    所述有源柱的顶面高于所述字线的顶面。
  15. 根据权利要求13所述的半导体结构的制作方法，所述方法，还包括：
    形成多条位线，每条所述位线沿所述第二方向延伸，任意一条所述位线设置在沿所述第二方向排列的一列所述有源柱的底部。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120094454A1 (en) * 2010-10-15 2012-04-19 Young-Seung Cho Method of fabricating semiconductor device including vertical channel transistor
CN112736036A (zh) * 2019-10-14 2021-04-30 长鑫存储技术有限公司 半导体结构及其形成方法
CN114188306A (zh) * 2020-09-14 2022-03-15 爱思开海力士有限公司 半导体器件及其制造方法
CN114927521A (zh) * 2022-04-11 2022-08-19 长鑫存储技术有限公司 半导体结构及其制作方法
CN115148663A (zh) * 2022-06-30 2022-10-04 长鑫存储技术有限公司 半导体结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120094454A1 (en) * 2010-10-15 2012-04-19 Young-Seung Cho Method of fabricating semiconductor device including vertical channel transistor
CN112736036A (zh) * 2019-10-14 2021-04-30 长鑫存储技术有限公司 半导体结构及其形成方法
CN114188306A (zh) * 2020-09-14 2022-03-15 爱思开海力士有限公司 半导体器件及其制造方法
CN114927521A (zh) * 2022-04-11 2022-08-19 长鑫存储技术有限公司 半导体结构及其制作方法
CN115148663A (zh) * 2022-06-30 2022-10-04 长鑫存储技术有限公司 半导体结构及其制备方法

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