WO2023029405A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023029405A1
WO2023029405A1 PCT/CN2022/077900 CN2022077900W WO2023029405A1 WO 2023029405 A1 WO2023029405 A1 WO 2023029405A1 CN 2022077900 W CN2022077900 W CN 2022077900W WO 2023029405 A1 WO2023029405 A1 WO 2023029405A1
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WIPO (PCT)
Prior art keywords
layer
trench
substrate
protective layer
semiconductor structure
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PCT/CN2022/077900
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English (en)
French (fr)
Inventor
邵光速
白卫平
肖德元
邱云松
Original Assignee
长鑫存储技术有限公司
北京超弦存储器研究院
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Application filed by 长鑫存储技术有限公司, 北京超弦存储器研究院 filed Critical 长鑫存储技术有限公司
Priority to KR1020227029092A priority Critical patent/KR20230035214A/ko
Priority to JP2022551562A priority patent/JP7464736B2/ja
Priority to EP22732384.7A priority patent/EP4167276A4/en
Priority to US17/664,236 priority patent/US20230061921A1/en
Publication of WO2023029405A1 publication Critical patent/WO2023029405A1/zh

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  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
  • the integration level of semiconductor structures is continuously improved, and the distance between devices in the semiconductor structure is continuously reduced, and the distance between adjacent conductive devices (such as bit lines) in the semiconductor structure is also continuously reduced.
  • Adjacent conductive devices and the insulating material between the conductive devices form a parasitic capacitance, which is proportional to the dielectric constant of the insulating material and inversely proportional to the distance between the two conductive devices.
  • the parasitic capacitance increases continuously, which leads to delay of the resistor capacitor (RC) of the semiconductor structure and affects the working efficiency of the semiconductor structure.
  • embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are used to reduce the parasitic capacitance of the semiconductor structure and improve the working efficiency of the semiconductor structure.
  • a first aspect of an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, which includes:
  • a substrate is provided, and a plurality of first grooves arranged at intervals are formed in the substrate, and the first grooves extend along a first direction;
  • a sacrificial layer and a first protective layer on the sacrificial layer are formed in each of the first trenches, the sacrificial layer and the first protective layer fill the first trenches, and each of the first trenches is
  • the first protective layer in the first trench is provided with an etching hole penetrating through the first protective layer;
  • the sacrificial layer is removed to form an air gap between the bit lines extending along the first direction, and part of the side surface of the bit line is exposed in the air gap, and the The characteristic that the dielectric constant is about 1 reduces the dielectric constant of the structure located between the bit lines, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.
  • a second aspect of an embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate, a plurality of bit lines arranged at intervals are formed in the substrate, the bit lines extend along a first direction, two adjacent A first trench is formed between the bit lines, and each of the bit lines is provided with at least one active region, and the active region includes a source region, a channel region and a drain region stacked in sequence, so One of the source region and the drain region is electrically connected to the bit line; a protective layer is arranged in the first trench, and a protective layer is formed between the protective layer and the bottom of the first trench.
  • first insulating layers arranged at intervals on the protective layer, the first insulating layer extends along the second direction, the The first insulating layer is located between two adjacent rows of the active regions in the second direction, and is spaced from the active regions; the first insulating layer disposed between the active regions a gate structure, the gate structure extends along the second direction and surrounds the active region, the gate structure is opposite to at least part of the channel region; a second insulating layer covering the gate structure layer and a third insulating layer.
  • the bit lines extend along the first direction, and a first trench is formed between two adjacent bit lines, a protective layer is arranged in the first trench, and the protective layer and the first trench
  • An air gap is formed between the groove bottoms of the grooves, and the side surface of the bit line is partially retained in the air gap, and the dielectric constant of the air is about 1, so that the dielectric constant of the structure located between the bit lines is reduced, thereby reducing the
  • the parasitic capacitance of the semiconductor structure improves the working efficiency of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the disclosure
  • FIG. 2 is a top view of a semiconductor structure in an embodiment of the present disclosure
  • 3 to 6 are schematic cross-sectional views of A-A, B-B, C-C and D-D of the substrate in the embodiment of the present disclosure
  • FIG. 7 to 10 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after the formation of the first trench in the embodiment of the present disclosure
  • 11 to 14 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming the first protective layer in the embodiment of the present disclosure
  • 15 to 18 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming etching holes in the embodiments of the present disclosure
  • FIG. 19 is a top view after forming an etching hole in an embodiment of the present disclosure.
  • 20 to 23 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after air gaps are formed in embodiments of the present disclosure
  • 24 to 27 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming the second trench in the embodiment of the present disclosure
  • 32 to 35 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming the third protective layer in the embodiments of the present disclosure;
  • 36 to 39 are respectively another schematic cross-sectional view of A-A, B-B, C-C and D-D after forming the second protective layer in the embodiment of the present disclosure
  • 40 to 43 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after bit lines are formed in an embodiment of the present disclosure
  • 44 to 47 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after the first insulating layer is formed in the embodiments of the present disclosure;
  • 48 to 51 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming a filled trench in an embodiment of the present disclosure
  • 52 to 55 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after the second insulating layer is formed in the embodiments of the present disclosure;
  • 56 to 59 are schematic cross-sectional views of A-A, B-B, C-C and D-D after the filling space is formed in the embodiments of the present disclosure
  • 60 to 63 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D where a conductive layer is formed in an embodiment of the present disclosure
  • 64 to 67 are respectively schematic cross-sectional views of A-A, B-B, C-C and D-D after forming the third insulating layer in the embodiment of the present disclosure
  • FIG. 68 and FIG. 69 are respectively schematic cross-sectional views at A-A and C-C in an embodiment of the present disclosure after capacitors are formed.
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor structure.
  • the side surface of the bit line is partially exposed in the air gap, and the dielectric constant of air is 1 to reduce the gap between the two bit lines.
  • the dielectric constant of the structures between them is reduced, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method includes the following steps:
  • Step S101 providing a substrate, in which a plurality of first trenches arranged at intervals are formed, and the first trenches extend along a first direction.
  • FIG. 2 is a top view of a semiconductor structure in an embodiment of the present disclosure, in which a word line 83 (Word Line, WL for short) and a bit line 52 (Bit Line, BL for short) are formed.
  • the bit line 52 extends along a first direction
  • the word line 83 extends along a second direction, and there is an angle between the first direction and the second direction, for example, the first direction and the second direction may be perpendicular to each other.
  • the bit line 52 extends in the vertical direction (Y direction)
  • the word line 83 extends in the horizontal direction (X direction)
  • the gate structure is formed in the word line 83 .
  • the word line 83 or the bit line 52 may be a straight line or a zigzag line.
  • Figure 2 has cross-sections at different positions. Specifically, the section at A-A is parallel to the extending direction of the bit lines 52 and located on the bit lines 52 , and the section at B-B is parallel to the extending direction of the bit lines 52 and located between adjacent bit lines 52 . The section at C-C is parallel to the extending direction of the word lines 83 and located on the word lines 83 , and the section at D-D is parallel to the extending direction of the word lines 83 and located between adjacent word lines 83 .
  • substrate 10 can be semiconductor substrate, and silicon element can be contained in this semiconductor substrate, for example, substrate can be silicon substrate, silicon germanium substrate or silicon on insulator (Silicon on Insulator, be called for short SOI) substrate, etc.
  • substrate can be silicon substrate, silicon germanium substrate or silicon on insulator (Silicon on Insulator, be called for short SOI) substrate, etc.
  • SOI silicon on Insulator
  • a plurality of first trenches 11 are formed in the substrate 10 , the plurality of first trenches 11 extend along a first direction, and the plurality of first trenches 11 are arranged at intervals.
  • the substrate 10 is etched to form a plurality of first trenches 11 in the substrate 10 .
  • the plurality of first trenches 11 are formed through a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process, In order to increase the density of the first trenches 11 .
  • SADP self-aligned Double Patterning
  • SAQP Self-Aligned Quadruple Patterning
  • Step S102 forming a sacrificial layer in each first trench and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer fill the first trenches, and the first protective layer in each first trench
  • the protective layer is provided with an etching hole penetrating through the first protective layer.
  • each first trench 11 is filled with a sacrificial layer 20
  • the rest of each first trench 11 is filled with a first protection layer 30 .
  • the material of the sacrificial layer 20 is different from that of the first protective layer 30.
  • the sacrificial layer 20 and the first protective layer 30 have a larger selection ratio, and when the sacrificial layer 20 is subsequently removed, the engraving of the first protective layer 30 is reduced. eclipse.
  • the material of the first protection layer 30 may be silicon oxide
  • the material of the sacrificial layer 20 may be silicon nitride.
  • each first protective layer 30 separated by the first trench 11 is provided with an etching hole 31 , the etching hole 31 penetrates the first protective layer 30 , and the etching hole 31 exposes the sacrificial layer 20 .
  • the cross-sectional shape of the etching hole 31 may be a circle, an ellipse, a square, a rectangle or other polygons.
  • part of the hole wall of the etching hole 31 may also be the side wall of the first trench 11 .
  • the etch hole 31 may be disposed at the edge of the first trench 11 away from the area for forming the word line 83 .
  • the number of etching holes 31 in each first trench 11 may be single or multiple, for example, one etching hole 31 is respectively formed at both ends of the first trench 11 .
  • the etching hole 31 may extend into the sacrificial layer 20 .
  • the bottom of the etching hole 31 is located in the sacrificial layer 20 , or the etching hole 31 penetrates the sacrificial layer 20 .
  • first protective layer 30 in each first trench 11 is provided with an etching hole 31 penetrating through the first protective layer 30, which may include:
  • Step S1021 depositing a sacrificial layer in each first trench, and filling the bottom of the first trench with the sacrificial layer.
  • a sacrificial layer 20 is formed in the trench 11 .
  • the thickness direction of the sacrificial layer 20 is the same as the depth direction of the first trench 11 , both of which are perpendicular to the substrate 10 (direction Z shown in FIG. 12 ).
  • Step S1022 depositing a first protective layer on the sacrificial layer, and filling up the first trench with the first protective layer.
  • a first protective layer 30 is deposited on the sacrificial layer 20 and the substrate 10, the first protective layer 30 is filled in the first trench 11 and covers the top surface of the substrate 10, as shown in FIGS.
  • the top surface of the substrate 10 refers to the upper surface of the substrate 10 .
  • the first protective layer 30 on the top surface of the substrate 10 is then removed to expose the substrate 10 .
  • the first protective layer 30 located on the top surface of the substrate 10 is removed by chemical mechanical polishing (CMP). After removing the first protective layer 30, the top surface of the substrate 10 is exposed.
  • Step S1023 etching the first protective layer at the edge of each first trench to form an etching hole.
  • a mask is deposited on the substrate 10 and the first protective layer 30 ; using the mask as a mask, dry etching or wet etching The first protection layer 30 to form the etching hole 31 shown in FIG. 16 ; and then remove the mask plate.
  • Step S103 using the etching hole to remove the sacrificial layer to form an air gap.
  • the sacrificial layer 20 is removed in the etching hole 31 by using an etching gas or etching solution. After removing the sacrificial layer 20 in each first trench, an air gap 21 is formed in each first trench. As shown in FIG. 21 , the air gap 21 is located below the etching hole 31 and communicates with the etching hole 31 .
  • Step S104 performing a silicidation reaction on the substrate located between adjacent first trenches and close to the bottom of the first trenches, so as to form bit lines extending along the first direction in the substrate, and the side surface portion of the bit lines exposed to air gaps.
  • a bit line 52 is formed in the substrate 10, and the bit line 52 extends in a first direction.
  • the bit line 52 is located between adjacent first trenches, and the bit line 52 is close to the bottom of the first trench.
  • the width of the bit line 52 is equal to the width of the substrate 10 between the adjacent first trenches, so that the side surface of the bit line 52 is partially exposed in the air gap 21 . As shown in FIGS. 40 to 43 , the lower portion of the side surface of the bit line 52 is exposed in the air gap 21 , and the upper portion of the side surface of the bit line 52 is in contact with the first protection layer 30 .
  • the bit line 52 can be formed by a silicide reaction.
  • the material of the bit line 52 includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide, or nickel silicide, to reduce the resistance of the bit line 52 .
  • metal silicide such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide, or nickel silicide, to reduce the resistance of the bit line 52 .
  • the substrate 10 located between adjacent first trenches 11 and close to the bottom of the first trenches 11 undergoes a silicidation reaction, so as to form an edge in the substrate 10 .
  • the bit line 52 extending in the first direction, the step of partially exposing the side surface of the bit line 52 in the air gap 21 includes:
  • Step S1041 etching the substrate and the first protection layer to form a plurality of second grooves arranged at intervals, the second grooves extend along the second direction and are not connected to the air gap.
  • the substrate 10 and the first protection layer 30 are etched to form a plurality of second trenches 12 , and the second trenches 12 are arranged at intervals and extend along the second direction.
  • the second trench 12 does not communicate with the air gap 21 , that is, the bottom of the second trench 12 is located in the substrate 10 and the first protection layer 30 , and does not penetrate the first protection layer 30 .
  • the remaining first protective layer 30 seals the top of the air gap 21 to prevent other materials from falling into the air gap 21 in subsequent manufacturing processes, so as to ensure the effect of the air gap 21 on reducing parasitic capacitance.
  • Step S1042 forming a second protective layer on the sidewall of the second trench, and forming a third trench by the second protective layer located in the second trench.
  • a second protection layer 50 is formed on the sidewall of the second trench 12 , and the second protection layer 50 covers the sidewall of the second trench 12 .
  • the second protective layer 50 inside the second trench 12 forms a third trench 51 , and the third trench 51 exposes part of the bottom of the second trench 12 .
  • the material of the first protection layer 30 can be the same as that of the second protection layer 50 , so that the first protection layer 30 and the second protection layer 50 form a whole.
  • a second initial protective layer is deposited on the sidewall and bottom of the second trench 12, the substrate 10, and the first protective layer 30, and the second initial protective layer located in the second trench 12
  • the initial protective layer surrounds the third trench 51; then etches the second initial protective layer along the third trench 51, removes part of the second initial protective layer at the bottom of the second trench 12, and retains the second initial protective layer
  • a second protective layer 50 is formed.
  • a third protective layer 40 is also deposited on the substrate 10 and the first protective layer 30 , that is, the top surface of the substrate 10 is covered with the third protective layer 40 .
  • the material of the third protection layer 40 , the material of the second protection layer 50 and the material of the first protection layer 30 can be the same, so that these three can form a whole.
  • a second initial protective layer is deposited on the sidewalls and bottom of the second trench 12, and the third protective layer 40; The protective layer, and a part of the second initial protective layer at the bottom of the second trench 12 to expose the bottom of the second trench 12 , and the remaining second initial protective layer forms the second protective layer 50 .
  • the upper part of the substrate 10 forms a plurality of pillars, the outer peripheral surface of the pillars is covered with the second protective layer 50, and the top surface of the pillars is covered with the third protective layer 40, which is located at the first The substrate 10 at the bottom of the triple trench 51 is exposed.
  • the third protection layer 40 formed on the substrate 10 is taken as an example for detailed description.
  • the step of depositing and forming the third protective layer 40 on the substrate 10 and the first protective layer 30 may be performed by etching the substrate 10 and the first protective layer 30 to form a plurality of second grooves arranged at intervals. 12.
  • this step is before the step S104 . Specifically, this step may be located after step S1022, or after step S1023, or after step S103.
  • the first protection layer 30 is deposited on the sacrificial layer 20 in the step, and after the first protection layer 30 fills up the first trench 11 (step S1023), the third protection layer 30 is deposited on the substrate 10 and the first protection layer 30 to form a protective layer 40 .
  • Such arrangement on the one hand, is easy to manufacture and reduces the difficulty of manufacturing the third protective layer 40; on the other hand, it can reduce the third protective layer 40 from falling into the etching hole 31 or the air gap 21, and improve the performance of the semiconductor structure.
  • etching the substrate 10 and the first protection layer 30 to form a plurality of second trenches 12 arranged at intervals, the second trenches 12 extending along the second direction and not communicating with the air gap 21 includes: The substrate 10 , the first protective layer 30 and the third protective layer 40 are etched to form a plurality of second trenches 12 arranged at intervals, and the third protective layer 40 between adjacent second trenches 12 is reserved.
  • Step S1043 depositing metal on the bottom of the third trench, and annealing for silicidation to form a bit line.
  • the metal can be one of cobalt, titanium, tantalum, nickel, and tungsten, or a refractory metal.
  • the metal reacts with the substrate 10 to form a metal silicide, and completely silicides a portion of the substrate 10 located between adjacent first trenches, and the metal silicide is connected along a first direction to form a bit line 52 .
  • the top surface portion of the bit line 52 is exposed in the third trench 51 , and the side surface portion of the bit line 52 is exposed in the air gap 21 .
  • the annealing treatment includes rapid thermal annealing (RTA for short), and the annealing temperature matches the material of the metal and the material of the substrate 10 .
  • RTA rapid thermal annealing
  • the annealing temperature may be 400°C-800°C.
  • the sacrificial layer 20 is removed to form the air gap 21 between the bit lines 52 extending along the first direction, and part of the side surface of the bit line 52 is exposed on In the air gap 21.
  • the dielectric constant of air is about 1
  • the dielectric constant of the structure located between the bit lines 52 is reduced, thereby reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.
  • the fabrication of the semiconductor structure also includes: forming an active region 13 in the substrate 10 away from the groove bottom of the first trench 11, the active region 13 includes a source region, a drain region and a channel region, and the source region, the channel region and the drain region The pole regions are sequentially arranged along a direction perpendicular to the bottom of the first trench 11 .
  • each active region includes a source region, a drain region and a channel region, and the channel region is located between the source region and the drain region. between polar regions.
  • the source region, the channel region and the drain region are vertically arranged, that is, arranged sequentially along a direction perpendicular to the bottom of the first trench 11 to form a vertical transistor.
  • the source region or the drain region is close to the groove bottom of the first trench 11, and the source region or the drain region close to the groove bottom of the first trench 11 is electrically connected to the subsequently formed bit line 52, that is, the source region or the drain region
  • the polar region is electrically connected to the bit line 52 .
  • the substrate 10 and the first protective layer 30 are etched to form a plurality of second grooves 12 arranged at intervals, and the second grooves 12 extend along the second direction and are not separated from the air gap 21.
  • the first trench 11 and the second trench 12 separate the substrate 10 into a plurality of columnar structures arranged at intervals; each columnar structure is then doped to form a source in the columnar structure region and drain region, so that an active region is formed in the substrate 10 away from the bottom of the first trench 11 .
  • a substrate 10 is provided, and a plurality of first trenches 11 arranged at intervals are formed in the substrate 10. After the first trenches 11 extend along the first direction (step S101), the The substrate 10 between adjacent first trenches 11 is doped to form an active region, that is, the active region is strip-shaped and extends along the first direction. After the second trench 12 is formed, the second trench 12 cuts off the active region to form a plurality of columnar active regions arranged at intervals.
  • the manufacturing method of the semiconductor structure further includes:
  • Step a forming a first insulating layer in the third trench, and filling the third trench with the first insulating layer.
  • a first insulating layer 61 is formed in the third trench 51 by a deposition process, the first insulating layer 61 extends along the second direction, and the first insulating layer 61 fills the third trench 51, for example, The first insulating layer 61 fills up the third trench 51 .
  • the third protective layer 40 on the substrate 10 is removed, the substrate 10 is exposed, and the surface of the first insulating layer 61 away from the air gap 21 is flush with the substrate 10, or in other words, the first The top surface of the insulating layer 61 is flush with the top surface of the substrate 10, so that the first insulating layer 61 and the substrate 10 form a relatively flat surface, which facilitates the fabrication of other structures.
  • the material of the first insulating layer 61 is different from that of the second protective layer 50, and the material of the first insulating layer 61 is also different from that of the first protective layer 30, so that the second protective layer 50 or the first protective layer can be removed separately later.
  • Layer 30 the material of the first insulating layer 61 may be silicon nitride, and the material of the first protection layer 30 and/or the second protection layer 50 may be silicon oxide.
  • Step b removing the first protective layer and the second protective layer to a predetermined depth along a direction perpendicular to the substrate to form a filling space, and the filling space exposes the side surface of the active region.
  • part of the first protection layer 30 and part of the second protection layer 50 are removed by an etching process, so as to remove part of the first protection layer 30 and part of the second protection layer 50 along a direction perpendicular to the substrate 10, and the substrate A recess having a predetermined depth is formed in the bottom 10, and the recess includes a filling space 72 in which a side surface of the active region is exposed. Specifically, at least part of the channel region is exposed in the filling space 72 .
  • the first protection layer 30 and the second protection layer 50 are removed to a preset depth along a direction perpendicular to the substrate 10 to form a filling space 72 , and the filling space 72 Exposing the side surfaces of the active region 13 includes the following processes:
  • the second protection layer 50 and the first protection layer 30 are etched to the initial depth to form a filled trench 71 .
  • the first protection layer 30 and the second protection layer 50 are etched along a direction perpendicular to the substrate 10 to form a filled channel 71 with an initial depth, and the upper one of the source region and the drain region is The one is opposite to the filled trench 71 .
  • There are multiple filled channels 71 and the multiple filled channels 71 are separated by the first insulating layer 61 .
  • a second insulating layer 62 is deposited in the filled trench 71 , and the second insulating layer 62 fills the filled trench 71 between the substrate 10 and the first insulating layer 61 .
  • the second insulating layer 62 is deposited in the filled trench 71 , and the second insulating layer 62 fills the filled trench 71 between the substrate 10 and the first insulating layer 61 .
  • the second insulating layer 62 is formed on the sidewall of the filled trench 71 , and the second insulating layer 62 blocks the filled trench 71 between the active region and the first insulating layer 61 .
  • the filled trench 71 is isolated into a plurality of openings arranged at intervals.
  • a gate structure 80 is formed in the filling space 72 , the gate structure 80 extends along the second direction, and surrounds the active region including:
  • Oxide layer 81 is formed on the inner surface of filling space 72 . 56 to 63, an oxide layer 81 is deposited on the inner surface of the filling space 72, and the oxide layer 81 covers the exposed peripheral surface of the active region, part of the side surface of the first insulating layer 61 and the bottom surface of the second insulating layer 62. . An oxide layer 81 is provided around the outer peripheral surface of the active region to form a gate oxide layer of the vertical transistor, and the oxide layer 81 may be a silicon oxide layer.
  • a conductive layer 82 is then formed in the filled space 72 after the oxide layer 81 is formed, and the conductive layer 82 is opposite to at least part of the channel region.
  • a conductive layer 82 is deposited in the filling space 72 and etched back, the conductive layer 82 fills at least part of the filling space 72 .
  • the oxide layer 81 and the conductive layer 82 form a gate structure 80, the gate structure 80 extends along the second direction and surrounds the active region, and the gate structure 80 is formed in the word line 83, that is, the gate structure 80 is a part of the word line 83. part.
  • the gate structure 80 extends along the second direction and surrounds the active region, further includes: depositing a third insulating layer 63 on the gate structure 80 , the third insulating layer 63 covers the gate structure 80 and fills the remaining filled trench 71 .
  • a third insulating layer 63 is deposited in the remaining filled trench 71 , and the third insulating layer 63 fills the filled trench 71 .
  • the gate structure 80 is covered by the third insulating layer 63 to insulate the gate structure 80 .
  • the materials of the third insulating layer 63 , the second insulating layer 62 and the first insulating layer 61 may be the same, so that the three are integrated to electrically isolate the gate structure 80 .
  • FIG. 68 and FIG. 69 after the third insulating layer 63 is formed, a contact node 91 and a capacitor 92 are formed on the substrate 10 , and the vertical transistor is electrically connected to the capacitor 92 through the contact node 91 .
  • an embodiment of the present disclosure also provides a semiconductor structure, which includes a substrate 10, which may be a silicon-containing substrate, for example, a silicon substrate, a silicon germanium substrate, or an insulator. silicon substrate, etc.
  • a substrate 10 which may be a silicon-containing substrate, for example, a silicon substrate, a silicon germanium substrate, or an insulator. silicon substrate, etc.
  • a plurality of bit lines 52 arranged at intervals are formed in the substrate 10, and the bit lines 52 extend along the first direction, and a first trench is formed between two adjacent bit lines 52, that is, the first trench also extends along the first direction. extend.
  • a substrate 10 which may be a silicon-containing substrate, for example, a silicon substrate, a silicon germanium substrate, or an insulator. silicon substrate, etc.
  • a plurality of bit lines 52 arranged at intervals are formed in the substrate 10, and the bit lines 52 extend along the first direction, and a first trench is formed between two adjacent bit lines 52, that is, the first trench also extends
  • the first direction is the Y direction
  • the material of the bit line 52 includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide, or nickel silicide, to reduce the resistance of the bit line 52 .
  • At least one active region 13 is disposed on each bit line 52, and the active region 13 includes a source region, a channel region and a drain region that are stacked in sequence, that is, the source region, the channel region and the drain region are arranged vertically. cloth.
  • One of the source region and the drain region is electrically connected to the bit line 52 , for example, the source region is located above the channel region, the drain region is located below the channel region, and the drain region is electrically connected to the bit line 52 .
  • the protection layer is also filled between adjacent active regions. As shown in FIG. 66, the top surface of the protection layer is higher than the top surface of the bit line 52, wherein the top surface refers to the surface away from the bottom of the first trench .
  • a plurality of first insulating layers 61 arranged at intervals are disposed on the protection layer, and the first insulating layers 61 extend along the second direction (direction X shown in FIG. 2 ).
  • the active regions 13 located in the second direction form a row
  • the first insulating layer 61 is disposed between the active regions 13 in two adjacent rows, and there is a space between the first insulating layer 61 and the active regions 13 .
  • the first insulating layer 61 separates two adjacent rows of active regions 13 so that one row of active regions 13 along the second direction is connected to one gate structure 80 .
  • the gate structure 80 is disposed between the first insulating layer 61 and the active region 13 .
  • the gate structure 80 extends along the second direction and surrounds the active region 13 .
  • the gate structure 80 corresponds to at least part of the channel region.
  • the gate structure 80 includes an oxide layer and a conductive layer 82. The oxide layer covers the outer surface of the conductive layer 82. As shown in FIG.
  • a contact node 91 is further arranged on the active region 13 , and a capacitor 92 is arranged on the contact node 91 , and the capacitor 92 is electrically connected to the active region 13 through the contact node 91 .
  • One of the source region and the drain region is in contact with a contact node 91 , eg, a source region contact structure.
  • the contact node 91 may be polysilicon, and the capacitor 92 is used for storing data information.
  • the bit lines 52 extend along the first direction, and a first trench 11 is formed between two adjacent bit lines 52, and a protective layer is disposed in the first trench 11, and the protective layer An air gap 21 is formed between the groove bottom of the first trench 11, and the side surface portion of the bit line 52 is kept in the air gap 21.
  • the dielectric constant of air is about 1, so that the bit line 52 The dielectric constant of the structure is reduced, thereby reducing the parasitic capacitance 92 of the semiconductor structure, and improving the working efficiency of the semiconductor structure.

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Abstract

本公开提供一种半导体结构及其制作方法，涉及半导体技术领域，用于解决半导体结构寄生电容较高的技术问题，该半导体结构的制作方法包括：提供衬底，衬底中形成有间隔设置的多个第一沟槽；在每个第一沟槽内形成牺牲层，以及位于牺牲层上的第一保护层，牺牲层和第一保护层填充满第一沟槽，每个第一沟槽内的第一保护层设置有贯穿第一保护层的刻蚀孔；利用刻蚀孔去除牺牲层，形成空气隙；位于相邻的第一沟槽之间且靠近第一沟槽的槽底的衬底进行硅化反应，以在衬底内形成位线，位线的侧表面部分暴露在空气隙内。通过形成空气隙，且位线的部分侧表面暴露在空气隙内，降低了位线之间的结构的介电常数降低，从而降低半导体结构的寄生电容。

Description

半导体结构及其制作方法
本公开要求于2021年08月30日提交中国专利局、申请号为202111007675.5、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
随着半导体技术的发展，半导体结构(例如存储器)的集成度不断提高，半导体结构中各器件的间距不断缩小，进而使得半导体结构中相邻的导电器件(例如位线)的间距也不断缩小。相邻的导电器件以及位于导电器件之间的绝缘材料形成寄生电容，寄生电容与绝缘材料的介电常数成正比，与两导电器件之间的距离成反比。随着位线的间距的缩小，寄生电容不断增大，导致半导体结构的电阻电容(Resistor Capacitor，简称RC)延迟，影响半导体结构的工作效率。
发明内容
鉴于上述问题，本公开实施例提供一种半导体结构及其制作方法，用于降低半导体结构的寄生电容，提高半导体结构的工作效率。
本公开实施例的第一方面提供一种半导体结构的制作方法，其包括：
提供衬底，衬底中形成有间隔设置的多个第一沟槽，所述第一沟槽沿第一方向延伸；
在每个所述第一沟槽内形成牺牲层，以及位于所述牺牲层上的第一保护层，所述牺牲层和所述第一保护层填充满所述第一沟槽，每个所述第一沟槽内的所述第一保护层设置有贯穿所述第一保护层的刻蚀孔；
利用所述刻蚀孔去除所述牺牲层，形成空气隙；
位于相邻的所述第一沟槽之间且靠近所述第一沟槽的槽底的所述衬底进行硅化反应，以在所述衬底内形成沿所述第一方向延伸的位线，所述位线的侧表面部分暴露在所述空气隙内。
本公开实施例提供的半导体结构的制作方法至少具有如下优点：
本公开实施例提供的半导体结构的制作方法中，通过去除牺牲层，以在沿第一方向延伸的位线之间形成空气隙，且位线的部分侧表面暴露在空气隙内，利用空气的介电常数约为1的特性，使得位于位线之间的结构的介电常数降低，从而降低半导体结构的寄生电容，提高半导体结构的工作效率。
本公开实施例的第二方面提供一种半导体结构，其包括：衬底，所述衬底内形成有多条间隔设置的位线，所述位线沿第一方向延伸，相邻的两条所述位线之间形成第一沟槽，每条所述位线上至少设置有一个有源区，所述有源区包括依次层叠设置的源极区、沟道区和漏极区，所述源极区和所述漏极区中的一个与所述位线电连接；设置在所述第一沟槽内的保护层，所述保护层与第一沟槽的槽底之间形成有空气隙，所述位线的侧表面部分暴露在所述空气隙内；设置在所述保护层上的多个间隔设置的第一绝缘层，所述第一绝缘层沿第二方向延伸，所述第一绝缘层位于第二方向上相邻的两行所述有源区之间，且与所述有源区具有间隔；设置在所述第一绝缘层与所述有源区之间的栅极结构，所述栅极结构沿所述第二方向延伸，且环绕所述有源区，所述栅极结构与 至少部分所述沟道区相对；覆盖所述栅极结构的第二绝缘层和第三绝缘层。
本公开实施例中的半导体结构至少具有下述优点：
本公开实施例中的半导体结构中，位线沿第一方向延伸，且相邻的两条位线之间形成第一沟槽，第一沟槽内设置有保护层，保护层与第一沟槽的槽底之间形成空气隙，位线的侧表面部分保留在空气隙内，利用空气的介电常数约为1的特性，使得位于位线之间的结构的介电常数降低，从而降低半导体结构的寄生电容，提高半导体结构的工作效率。
附图说明
图1为本公开实施例中的半导体结构的制作方法的流程图；
图2为本公开实施例中的半导体结构的俯视图；
图3至图6分别为本公开实施例中的衬底的A-A处、B-B处、C-C处和D-D处的截面示意图；
图7至图10分别为本公开实施例中的形成第一沟槽后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图11至图14分别为本公开实施例中的形成第一保护层后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图15至图18分别为本公开实施例中的形成刻蚀孔后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图19为本公开实施例中的形成刻蚀孔后的俯视图；
图20至图23分别为本公开实施例中的形成空气隙后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图24至图27分别为本公开实施例中的形成第二沟槽后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图28至图31分别为本公开实施例中的形成第二保护层后的A-A处、B-B处、C-C处和D-D处的一种截面示意图；
图32至图35分别为本公开实施例中的形成第三保护层后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图36至图39分别为本公开实施例中的形成第二保护层后的A-A处、B-B处、C-C处和D-D处的另一种截面示意图；
图40至图43分别为本公开实施例中的形成位线后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图44至图47分别为本公开实施例中的形成第一绝缘层后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图48至图51分别为本公开实施例中的形成填充沟道后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图52至图55分别为本公开实施例中的形成第二绝缘层后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图56至图59分别为本公开实施例中的形成填充空间后的A-A处、B-B处、C-C处和D-D处的截面示意图；
图60至图63分别为本公开实施例中的形成导电层的A-A处、B-B处、C-C处和D-D处的截面示意图；
图64至图67分别为本公开实施例中的形成第三绝缘层后的A-A处、B-B处、C-C处和D-D 处的截面示意图；
图68和图69分别为本公开实施例中的形成电容后的A-A处和C-C处的截面示意图。
具体实施方式
本公开实施例提供一种半导体结构的制作方法，通过在位线之间形成空气隙，位线的侧表面部分暴露在空气隙内，利用空气的介电常数为1，降低位于两个位线之间的结构的介电常数，从而降低半导体结构的寄生电容，提高半导体结构的工作效率。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
参考图1，本公开实施例提供一种半导体结构的制作方法，该制作方法包括以下步骤：
步骤S101、提供衬底，衬底中形成有间隔设置的多个第一沟槽，第一沟槽沿第一方向延伸。
参考图2，图2为本公开实施例中的半导体结构的俯视图，该半导体结构中形成有字线83(Word Line，简称WL)和位线52(Bit Line，简称BL)。其中，位线52沿第一方向延伸，字线83沿第二方向延伸，第一方向和第二方向之间具有夹角，例如第一方向和第二方向可以相垂直。具体的，如图2所示，位线52沿竖直方向(Y方向)延伸，字线83沿水平方向(X方向)延伸，栅极结构形成于字线83中。字线83或者位线52可以为直线，也可以为折线。
图2中具有不同位置的截面。具体的，A-A处的截面为平行于位线52延伸方向，且位于位线52上的截面，B-B处截面为平行于位线52延伸方向，且位于相邻位线52之间的截面。C-C处的截面为平行于字线83延伸方向，且位于字线83上的截面，D-D处的截面为平行于字线83延伸方向，且位于相邻字线83之间的截面。
参考图3至图6，衬底10可以为半导体衬底，该半导体衬底内可以含有硅元素，例如，衬底可以为硅衬底、硅锗衬底或者绝缘体上硅(Silicon on Insulator，简称SOI)衬底等。为方便描述，本公开实施例及以下各实施例中，以衬底10为硅衬底为例进行详述。
参考图7至图10，衬底10内形成有多个第一沟槽11，多个第一沟槽11沿第一方向延伸，且多个第一沟槽11之间间隔设置。示例性的，刻蚀衬底10以在衬底10内形成多个第一沟槽11。具体的，通过自对准双图形化(Self-Aligned Double Patterning，简称SADP)工艺或者自对准四重图形化(Self-Aligned Quadruple Patterning，简称SAQP)工艺形成上述多个第一沟槽11，以增大第一沟槽11的密度。
步骤S102、在每个第一沟槽内形成牺牲层，以及位于牺牲层上的第一保护层，牺牲层和第一保护层填充满第一沟槽，每个第一沟槽内的第一保护层设置有贯穿第一保护层的刻蚀孔。
参考图7至图14，每个第一沟槽11的底部填充有牺牲层20，每个第一沟槽11的其余部分填充有第一保护层30。牺牲层20的材质与第一保护层30的材质不同，例如，牺牲层20与第一保护层30具有较大的选择比，在后续去除牺牲层20时，减少对第一保护层30的刻蚀。示例性的，第一保护层30的材质可以为氧化硅，牺牲层20的材质可以为氮化硅。
参考图15至图19，由第一沟槽11隔开的各第一保护层30均设置有刻蚀孔31，刻蚀孔31贯穿第一保护层30，刻蚀孔31暴露牺牲层20。以平行于衬底10的平面为截面，刻蚀孔31的截面形状可以为圆形、椭圆形、正方形、矩形或者其他多边形。如图19所示，刻蚀孔31的部分孔壁还可为第一沟槽11的侧壁。刻蚀孔31可以设置在第一沟槽11的边缘，其远离用于形成字线83的区域。每个第一沟槽11内的刻蚀孔31的数量可以为单个，也可以为多个，例如，第一沟槽11 的两端分别形成有一个刻蚀孔31。
为了增加暴露在刻蚀孔31内的牺牲层20的表面积，以便于后续去除刻蚀层，如图16所示，刻蚀孔31可以延伸至牺牲层20中。示例性的，刻蚀孔31的孔底位于牺牲层20中，或者刻蚀孔31贯穿牺牲层20。
在一种可能的示例中，参考图7至图18，在每个第一沟槽11内形成牺牲层20，以及位于牺牲层20上的第一保护层30，牺牲层20和第一保护层30填充满第一沟槽11，每个第一沟槽11内的第一保护层30设置有贯穿第一保护层30的刻蚀孔31可以包括：
步骤S1021、在每个第一沟槽内沉积牺牲层，牺牲层填充在第一沟槽的底部。
参考图7至图14，通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等工艺，在第一沟槽11内形成牺牲层20。牺牲层20的厚度方向与第一沟槽11的深度方向相同，均为垂直于衬底10的方向(图12所示Z方向)。
步骤S1022、在牺牲层上沉积第一保护层，第一保护层填平第一沟槽。
参考图11至图14，在牺牲层20和衬底10上沉积第一保护层30，第一保护层30填充在第一沟槽11内且覆盖衬底10的顶面，如图11至图14所示，衬底10的顶面是指衬底10的上表面。再去除位于衬底10的顶面上的第一保护层30，以暴露衬底10。示例性的，通过化学机械研磨(Chemical Mechanical Polishing，简称CMP)去除位于衬底10的顶面上的第一保护层30，去除该第一保护层30后，衬底10的顶面暴露出来。
步骤S1023、刻蚀每个第一沟槽边缘的第一保护层，以形成刻蚀孔。
如图15至图18所示，在一些可能的示例中，在衬底10和第一保护层30上沉积形成掩膜板；以掩膜板为掩膜，干法刻蚀或者湿法刻蚀第一保护层30，以形成图16所示的刻蚀孔31；再去除掩膜板。
步骤S103、利用刻蚀孔去除牺牲层，形成空气隙。
参考图20至图23，在刻蚀孔31内利用刻蚀气体或者刻蚀液去除牺牲层20。去除每个第一沟槽内的牺牲层20后，每个第一沟槽内均形成空气隙21。如图21所示，空气隙21位于刻蚀孔31的下方，且与刻蚀孔31相连通。
步骤S104、位于相邻的第一沟槽之间且靠近第一沟槽的槽底的衬底进行硅化反应，以在衬底内形成沿第一方向延伸的位线，位线的侧表面部分暴露在空气隙内。
参考图24至图43，衬底10内形成位线52，位线52沿第一方向延伸。位线52位于相邻的第一沟槽之间，且位线52靠近第一沟槽的槽底。位线52的宽度与位于相邻的第一沟槽之间衬底10的宽度相等，以使位线52的侧表面部分暴露在空气隙21内。如图40至图43所示，位线52的侧表面的下部分暴露在空气隙21内，位线52的侧表面的上部分与第一保护层30相接触。
位线52可以通过硅化反应形成，位线52的材质包括金属硅化物，例如硅化钴、硅化钨、硅化钛、硅化铂或硅化镍等，以降低位线52的电阻。示例性的，如图24至图43所示，位于相邻的第一沟槽11之间且靠近第一沟槽11的槽底的衬底10进行硅化反应，以在衬底10内形成沿第一方向延伸的位线52，位线52的侧表面部分暴露在空气隙21内的步骤包括：
步骤S1041、刻蚀衬底和第一保护层，形成多个间隔设置的第二沟槽，第二沟槽沿第二方向延伸且与空气隙不连通。
参考图24至图27，刻蚀衬底10和第一保护层30，形成多个第二沟槽12，第二沟槽12间隔设置且沿第二方向延伸。第二沟槽12与空气隙21不连通，即第二沟槽12的槽底位于衬底10和第一保护层30内，未贯穿第一保护层30。如此设置，剩余的第一保护层30将空气隙21的顶部密封，以防止后续制程中其他材料落入空气隙21内，以保证空气隙21降低寄生电容的效果。
步骤S1042、在第二沟槽的侧壁上形成第二保护层，位于第二沟槽内的第二保护层围合成第三沟槽。
参考图24至图31，第二沟槽12的侧壁上形成第二保护层50，第二保护层50覆盖第二沟槽12的侧壁。位于第二沟槽12内的第二保护层50围合成第三沟槽51，第三沟槽51暴露第二沟槽12的部分槽底。第一保护层30的材质可以与第二保护层50的材质相同，以使第一保护层30与第二保护层50形成一个整体。
在一种可能的实施例中，在第二沟槽12的侧壁和槽底、衬底10，以及第一保护层30上沉积第二初始保护层，位于第二沟槽12内的第二初始保护层围合成第三沟槽51；再沿第三沟槽51刻蚀第二初始保护层，去除第二沟槽12的槽底的部分第二初始保护层，保留的第二初始保护层形成第二保护层50。
在另一种可能的实施例中，参考图32至图35，衬底10和第一保护层30上还沉积有第三保护层40，即衬底10的顶面覆盖有第三保护层40。第三保护层40的材质、第二保护层50的材质以及第一保护层30的材质可以相同，以使这三者可以形成一个整体。
参考图32至图39，在第二沟槽12的侧壁和槽底，以及第三保护层40上沉积第二初始保护层；再去除刻蚀去除位于第三保护层40上的第二初始保护层，以及位于第二沟槽12的槽底的部分第二初始保护层，以暴露第二沟槽12的槽底，保留的第二初始保护层形成第二保护层50。
可以理解的是，在利用各向异性刻蚀沿第三沟槽51刻蚀第二初始保护层，以去除第二沟槽12的槽底的部分第二初始保护层时，必然会刻蚀到第三保护层40上的第二初始保护层。通过设置第三保护层40，可以防止衬底10的顶面暴露，使得只有位于第二沟槽12的衬底10暴露出来，从而保证位线52的形成位置。
如图36至图37所示，衬底10的上部分形成多个立柱，该立柱的外周面上覆盖有第二保护层50，该立柱的顶面上覆盖有第三保护层40，位于第三沟槽51的槽底的衬底10暴露。为方便描述，本公开实施例及以下各实施例中，以衬底10上形成有第三保护层40为例进行详述。
需要说明的是，在衬底10和第一保护层30上沉积形成第三保护层40这一步骤可以位于刻蚀衬底10和第一保护层30，形成多个间隔设置的第二沟槽12，第二沟槽12沿第二方向延伸且与空气隙21不连通的步骤(步骤S1041)之前，即该步骤位于步骤S104之前。具体的，该步骤可以位于在步骤S1022之后，也可以位于步骤S1023之后，还可以位于步骤S103之后。
优选地，在步骤牺牲层20上沉积第一保护层30，第一保护层30填平第一沟槽11(步骤S1023)之后，再在衬底10和第一保护层30上沉积形成第三保护层40。如此设置，一方面易于制作，降低第三保护层40的制作难度；另一方面可以减少第三保护层40掉落到刻蚀孔31或者空气隙21内，提高半导体结构的性能。
相应的，刻蚀衬底10和第一保护层30，形成多个间隔设置的第二沟槽12，第二沟槽12沿第二方向延伸且与空气隙21不连通(步骤S1041)包括：刻蚀衬底10、第一保护层30和第三保护层40，形成多个间隔设置的第二沟槽12，保留位于相邻的第二沟槽12之间的第三保护层40。
步骤S1043、在第三沟槽的槽底沉积金属，退火处理进行硅化反应，以形成位线。
参考图40至图43，金属可以为钴、钛、钽、镍、钨中的一种，也可以为难熔金属。金属与衬底10反应形成金属硅化物，并使位于相邻的第一沟槽之间的部分衬底10完全硅化，且金属硅化物沿第一方向相连接形成位线52。位线52的顶面部分暴露在第三沟槽51内，位线52的侧表面部分暴露在空气隙21内。
退火处理包括快速热退火(Rapid Thermal Annealing，简称RTA)，退火的温度与金属的材质、衬底10的材质相匹配。例如，当衬底10的材质为硅，金属为钴时，退火的温度可以为400℃-800℃。
综上，本公开实施例提供的半导体结构的制作方法中，通过去除牺牲层20，以在沿第一方向 延伸的位线52之间形成空气隙21，且位线52的部分侧表面暴露在空气隙21内。利用空气的介电常数约为1的特性，使得位于位线52之间的结构的介电常数降低，从而降低半导体结构的寄生电容，提高半导体结构的工作效率。
需要说明的是，在第二沟槽12的侧壁上形成第二保护层50，位于第二沟槽12内的第二保护层50围合成第三沟槽51的步骤之前，半导体结构的制作方法还包括：远离第一沟槽11的槽底的衬底10中形成有源区13，有源区13包括源极区、漏极区和沟道区，源极区、沟道区和漏极区沿垂直于第一沟槽11的槽底的方向依次排布。
在形成位线52之前，在衬底10中形成多个间隔设置的有源区，每个有源区均包括源极区、漏极区和沟道区，沟道区位于源极区和漏极区之间。本公开实施例中，源极区、沟道区和漏极区垂直排布，即沿垂直于第一沟槽11的槽底的方向依次排布，以形成垂直晶体管。源极区或者漏极区靠近第一沟槽11的槽底，靠近第一沟槽11的槽底的源极区或者漏极区与后续形成的位线52电连接，即源极区或者漏极区与位线52电连接。如此设置，在占用相同衬底10面积的前提下，可以通过增加有源区的高度而增加沟道区的有效长度，减少或者避免短沟道效应，提高半导体结构的性能。
在本公开一些可能的实施例中，刻蚀衬底10和第一保护层30，形成多个间隔设置的第二沟槽12，第二沟槽12沿第二方向延伸且与空气隙21不连通(步骤S1041)之后，第一沟槽11和第二沟槽12将衬底10分隔成多个间隔设置的柱状结构；再对每个柱状结构进行掺杂，以在柱状结构中形成源极区和漏极区，从而在远离第一沟槽11的槽底的衬底10中形成有源区。
在本公开另一些可能的实施例中，提供衬底10，衬底10中形成有间隔设置的多个第一沟槽11，第一沟槽11沿第一方向延伸(步骤S101)之后，在相邻的第一沟槽11之间的衬底10进行掺杂，以形成有源区，即有源区为条状，且沿第一方向延伸。再形成第二沟槽12后，第二沟槽12将有源区切断，形成多个间隔设置的柱状有源区。
需要说明的是，参考图44至图67，在第三沟槽51的槽底沉积金属，退火处理进行硅化反应，以形成位线52的步骤之后，半导体结构的制作方法还包括：
步骤a：在第三沟槽内形成第一绝缘层，第一绝缘层填充在第三沟槽内。
参考图40至图47，通过沉积工艺在第三沟槽51内形成第一绝缘层61，第一绝缘层61沿第二方向延伸，第一绝缘层61填充满第三沟槽51，例如，第一绝缘层61填平第三沟槽51。如图40至图47所示，衬底10上的第三保护层40去除，衬底10暴露出来，第一绝缘层61远离空气隙21的表面与衬底10齐平，或者说，第一绝缘层61的顶面与衬底10的顶面齐平，以使第一绝缘层61和衬底10形成较为平整的表面，便于其他结构的制作。
第一绝缘层61的材质与第二保护层50的材质不同，第一绝缘层61的材质与第一保护层30的材质也不同，以使后续可以单独去除第二保护层50或者第一保护层30。示例性的，第一绝缘层61的材质可以为氮化硅，第一保护层30和/或第二保护层50的材质可以为氧化硅。
步骤b：沿垂直于衬底的方向去除第一保护层和第二保护层至预设深度，形成填充空间，填充空间暴露有源区的侧表面。
参考图48至图59，通过刻蚀工艺去除部分第一保护层30和部分第二保护层50，以沿垂直于衬底10的方向去除部分第一保护层30和第二保护层50，衬底10中形成具有预设深度的凹陷，凹陷包括填充空间72，填充空间72中暴露有源区的侧表面。具体的，填充空间72中暴露至少部分沟道区。
在一些可能的实施例中，如图48至图59所示，沿垂直于衬底10的方向去除第一保护层30和第二保护层50至预设深度，形成填充空间72，填充空间72暴露有源区13的侧表面包括以下过程：
刻蚀第二保护层50和第一保护层30至初始深度，形成填充沟道71。参考图48至图51，沿垂直于衬底10方向刻蚀第一保护层30和第二保护层50，形成具有初始深度的填充沟道71，源极区和漏极区中位于上方的一者与填充沟道71相对。填充沟道71的数量为多个，多个填充沟道71由第一绝缘层61隔开。
形成填充沟道71后，在填充沟道71中沉积第二绝缘层62，第二绝缘层62填满位于衬底10和第一绝缘层61之间的填充沟道71。参考图52至图55，在填充沟道71内沉积第二绝缘层62，第二绝缘层62填充满衬底10和第一绝缘层61之间的填充沟道71。具体的，在填充沟道71的侧壁上形成第二绝缘层62，第二绝缘层62将有源区和第一绝缘层61之间的填充沟道71封堵。形成第二绝缘层62后，填充沟道71被隔离成多个间隔设置的开口。
沉积第二绝缘层62后，刻蚀剩余的第一保护层30和第二保护层50至预设深度，形成填充空间72。参考图56至图59，通过剩余的填充沟道71继续刻蚀第一保护层30和第二保护层50至预设深度，去除剩余的部分第一保护层30和第二保护层50后形成填充空间72，填充空间72位于填充沟道71的下方且与填充沟道71相连通。
步骤c：在填充空间内形成栅极结构，栅极结构沿第二方向延伸，且环绕有源区。
示例性的，参考图60至图67，在填充空间72内形成栅极结构80，栅极结构80沿第二方向延伸，且环绕有源区包括：
在填充空间72的内表面形成氧化物层81。参考图56至图63，在填充空间72的内表面沉积氧化物层81，氧化物层81覆盖有源区暴露的外周面、第一绝缘层61的部分侧表面以及第二绝缘层62的底面。环设在有源区的外周面上氧化物层81形成垂直晶体管的栅氧层，氧化物层81可以为氧化硅层。
再在形成氧化物层81后的填充空间72内形成导电层82，导电层82与至少部分沟道区相对。参考图60至图63，在填充空间72内沉积导电层82并回刻，导电层82填充至少部分填充空间72。氧化物层81和导电层82形成栅极结构80，栅极结构80沿第二方向延伸且环绕有源区，栅极结构80形成于字线83中，即栅极结构80为字线83的一部分。
需要说明的是，在填充空间72内形成栅极结构80，栅极结构80沿第二方向延伸，且环绕有源区的步骤之后，还包括：在栅极结构80上沉积第三绝缘层63，第三绝缘层63覆盖栅极结构80，且填充满剩余的填充沟道71。
参考图64至图67，在剩余的填充沟道71内沉积第三绝缘层63，第三绝缘层63填充满填充沟道71。通过第三绝缘层63将栅极结构80覆盖，以使栅极结构80绝缘。第三绝缘层63、第二绝缘层62和第一绝缘层61的材质可以相同，以使这三者形成一个整体，从而将栅极结构80电气隔离。参考图68和图69，形成第三绝缘层63后，在衬底10上再形成接触节点91和电容92，通过接触节点91将垂直晶体管与电容92电连接。
参考图2、以及图64至图67，本公开实施例还提供一种半导体结构，其包括衬底10，衬底10可以为含硅衬底，例如，硅衬底、硅锗衬底或者绝缘体上硅衬底等。衬底10内形成有多条间隔设置的位线52，位线52沿第一方向延伸，相邻的两条位线52之间形成第一沟槽，即第一沟槽也沿第一方向延伸。如图2所示，第一方向为Y方向，位线52的材质包括金属硅化物，例如硅化钴、硅化钨、硅化钛、硅化铂或硅化镍等，以降低位线52的电阻。
每条位线52上至少设置有一个有源区13，有源区13包括依次层叠设置的源极区、沟道区和漏极区，即源极区、沟道区和漏极区垂直排布。源极区和漏极区中的一个与位线52电连接，例如，源极区位于沟道区的上方，漏极区位于沟道区的下方，漏极区与位线52电连接。
第一沟槽内设置有保护层(包括第一保护层30和第二保护层50)，保护层与第一沟槽的槽底之间形成空气隙21，位线52的侧表面部分暴露在空气隙21内。如图66所示，位线52的侧表 面的下部分暴露在空气隙21内，位线52的侧表面的上部分与保护层相接触。
保护层还填充在相邻的有源区之间，如图66所示，保护层的顶面高于位线52的顶面，其中，顶面是指远离第一沟槽的槽底的表面。保护层上设置有多个间隔设置的第一绝缘层61，第一绝缘层61沿第二方向(图2所示X方向)延伸。位于第二方向的有源区13形成一行，相邻两行的有源区13之间设置有第一绝缘层61，且第一绝缘层61与有源区13之间具有间隔。第一绝缘层61将相邻两行的有源区13分隔开，以使沿第二方向的一行有源区13连接一条栅极结构80。
栅极结构80设置在第一绝缘层61和有源区13之间，栅极结构80沿第二方向延伸，且环绕有源区13，栅极结构80与至少部分沟道区相对应。栅极结构80包括氧化物层和导电层82，氧化物层覆盖导电层82的外表面，如图66所示，导电层82的侧表面、底面以及部分顶面覆盖有氧化物层81。
栅极结构80上还覆盖有第二绝缘层62和第三绝缘层63，如图66所示，第二绝缘层62与栅极结构80的边缘区域相对，第三绝缘层63与栅极结构80的中间区域相对，第二绝缘层62和第三绝缘层63形成一整层，从而覆盖栅极结构80。第一绝缘层61、第二绝缘层62和第三绝缘层63的材质可以相同，例如为氮化硅，以使这三者形成一个整体，对栅极结构80进行电气绝缘。
参考图68和图69，有源区13上还设置有接触节点91，接触节点91上设置有电容92，电容92通过接触节点91与有源区13电连接。源极区和漏极区中一个与接触节点91相接触，例如，源极区域接触结构相接触。接触节点91可以为多晶硅，电容92用于存储数据信息。
本公开实施例中的半导体结构中，位线52沿第一方向延伸，且相邻的两条位线52之间形成第一沟槽11，第一沟槽11内设置有保护层，保护层与第一沟槽11的槽底之间形成空气隙21，位线52的侧表面部分保留在空气隙21内，利用空气的介电常数约为1的特性，使得位于位线52之间的结构的介电常数降低，从而降低半导体结构的寄生电容92，提高半导体结构的工作效率。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (18)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，衬底中形成有间隔设置的多个第一沟槽，所述第一沟槽沿第一方向延伸；
    在每个所述第一沟槽内形成牺牲层，以及位于所述牺牲层上的第一保护层，所述牺牲层和所述第一保护层填充满所述第一沟槽，每个所述第一沟槽内的所述第一保护层设置有贯穿所述第一保护层的刻蚀孔；
    利用所述刻蚀孔去除所述牺牲层，形成空气隙；
    位于相邻的所述第一沟槽之间且靠近所述第一沟槽的槽底的所述衬底进行硅化反应，以在所述衬底内形成沿所述第一方向延伸的位线，所述位线的侧表面部分暴露在所述空气隙内。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在每个所述第一沟槽内形成牺牲层，以及位于所述牺牲层上的第一保护层，所述牺牲层和所述第一保护层填充满所述第一沟槽，每个所述第一沟槽内的所述第一保护层设置有贯穿所述第一保护层的刻蚀孔的步骤包括：
    在每个所述第一沟槽内沉积所述牺牲层，所述牺牲层填充在所述第一沟槽的底部；
    在所述牺牲层上沉积所述第一保护层，所述第一保护层填平所述第一沟槽；
    刻蚀每个所述第一沟槽边缘的所述第一保护层，以形成所述刻蚀孔。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，在所述牺牲层和所述衬底上沉积所述第一保护层，所述第一保护层填平所述第一沟槽的步骤包括：
    在所述牺牲层和所述衬底上沉积所述第一保护层，所述第一保护层填充在所述第一沟槽内且覆盖所述衬底的顶面；
    去除位于所述衬底的顶面上的所述第一保护层，以暴露所述衬底。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，所述刻蚀孔延伸至所述牺牲层中。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，所述位线的材质包括金属硅化物。
  6. 根据权利要求1-5任一项所述的半导体结构的制作方法，其中，位于相邻的所述第一沟槽之间且靠近所述第一沟槽的槽底的所述衬底进行硅化反应，以在所述衬底内形成沿所述第一方向延伸的位线，所述位线的侧表面部分暴露在所述空气隙内的步骤包括：
    刻蚀所述衬底和所述第一保护层，形成多个间隔设置的第二沟槽，所述第二沟槽沿第二方向延伸且与所述空气隙不连通；
    在所述第二沟槽的侧壁上形成第二保护层，位于所述第二沟槽内的所述第二保护层围合成第三沟槽；
    在所述第三沟槽的槽底沉积金属，退火处理进行硅化反应，以形成所述位线。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，刻蚀所述衬底和所述第一保护层，形成多个间隔设置的第二沟槽，所述第二沟槽沿第二方向延伸且与所述空气隙不连通的步骤之前，还包括：
    在所述衬底和所述第一保护层上沉积形成第三保护层；
    刻蚀所述衬底和所述第一保护层，形成多个间隔设置的第二沟槽的步骤包括：刻蚀所述衬底、所述第一保护层和所述第三保护层，形成多个间隔设置的所述第二沟槽，保留位于相邻的所述第二沟槽之间的所述第三保护层。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，在所述第二沟槽的侧壁上形成第二 保护层，位于所述第二沟槽内的所述第二保护层围合成第三沟槽的步骤包括：
    在所述第二沟槽的侧壁和槽底，以及所述第三保护层上沉积形成第二初始保护层；
    刻蚀去除位于所述第三保护层上和所述第二沟槽的槽底的所述第二初始保护层，以暴露所述第二沟槽的槽底，保留的所述第二初始保护层形成所述第二保护层。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，所述第一保护层、所述第二保护层和所述第三保护层的材料相同。
  10. 根据权利要求6所述的半导体结构的制作方法，其中，在所述第二沟槽的侧壁上形成第二保护层，位于所述第二沟槽内的所述第二保护层围合成第三沟槽的步骤之前，还包括：
    远离所述第一沟槽的槽底的所述衬底中形成有源区，所述有源区包括源极区、漏极区和沟道区，所述源极区、所述沟道区和所述漏极区沿垂直于所述第一沟槽的槽底的方向依次排布。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，在所述第三沟槽的槽底沉积金属，退火处理进行硅化反应，以形成所述位线的步骤之后，还包括：
    在所述第三沟槽内形成第一绝缘层，所述第一绝缘层填充在所述第三沟槽内；
    沿垂直于所述衬底的方向去除所述第一保护层和所述第二保护层至预设深度，形成填充空间，所述填充空间暴露所述有源区的侧表面；
    在所述填充空间内形成栅极结构，所述栅极结构沿第二方向延伸，且环绕所述有源区。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述第一保护层和所述第一绝缘层的材料不同。
  13. 根据权利要求11所述的半导体结构的制作方法，其中，沿垂直于所述衬底的方向去除所述第一保护层和所述第二保护层至预设深度，形成填充空间，所述填充空间暴露所述有源区的侧表面的步骤包括：
    刻蚀所述第二保护层和所述第一保护层至初始深度，形成填充沟道；
    在所述填充沟道中沉积第二绝缘层，所述第二绝缘层填满位于所述衬底和所述第一绝缘层之间的所述填充沟道；
    刻蚀剩余的所述第一保护层和所述第二保护层至预设深度，形成所述填充空间。
  14. 根据权利要求11所述的半导体结构的制作方法，其中，在所述填充空间内形成栅极结构，所述栅极结构沿第二方向延伸，且环绕所述有源区的步骤包括：
    在所述填充空间的内表面形成氧化物层；
    在形成所述氧化物层后的所述填充空间内形成导电层，所述导电层与至少部分所述沟道区相对。
  15. 根据权利要求13所述的半导体结构的制作方法，其中，在所述填充空间内形成栅极结构，所述栅极结构沿第二方向延伸，且环绕所述有源区的步骤之后，还包括：
    在所述栅极结构上沉积第三绝缘层，所述第三绝缘层覆盖所述栅极结构，且填充满剩余的所述填充沟道。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的材料相同。
  17. 一种半导体结构，包括：
    衬底，所述衬底内形成有多条间隔设置的位线，所述位线沿第一方向延伸，相邻的两条所述位线之间形成第一沟槽，每条所述位线上至少设置有一个有源区，所述有源区包括依次层叠设置 的源极区、沟道区和漏极区，所述源极区和所述漏极区中的一个与所述位线电连接；
    设置在所述第一沟槽内的保护层，所述保护层与第一沟槽的槽底之间形成有空气隙，所述位线的侧表面部分暴露在所述空气隙内；
    设置在所述保护层上的多个间隔设置的第一绝缘层，所述第一绝缘层沿第二方向延伸，所述第一绝缘层位于第二方向上相邻的两行所述有源区之间，且与所述有源区具有间隔；
    设置在所述第一绝缘层与所述有源区之间的栅极结构，所述栅极结构沿所述第二方向延伸，且环绕所述有源区，所述栅极结构与至少部分所述沟道区相对；
    覆盖所述栅极结构的第二绝缘层和第三绝缘层。
  18. 根据权利要求17所述的半导体结构，其中，还包括：
    位于所述源极区和所述漏极区中的另一个上的接触节点，以及位于所述接触节点上的电容。
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