WO2023206743A1 - 半导体器件的制备方法及半导体器件 - Google Patents

半导体器件的制备方法及半导体器件 Download PDF

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Publication number
WO2023206743A1
WO2023206743A1 PCT/CN2022/098253 CN2022098253W WO2023206743A1 WO 2023206743 A1 WO2023206743 A1 WO 2023206743A1 CN 2022098253 W CN2022098253 W CN 2022098253W WO 2023206743 A1 WO2023206743 A1 WO 2023206743A1
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Prior art keywords
layer
top surface
substrate
insulating layer
pillar
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PCT/CN2022/098253
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English (en)
French (fr)
Inventor
张世明
文浚硕
肖德元
金若兰
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长鑫存储技术有限公司
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Priority to US17/893,058 priority Critical patent/US20230345697A1/en
Publication of WO2023206743A1 publication Critical patent/WO2023206743A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure, a manufacturing method thereof, and a semiconductor device.
  • DRAM Dynamic Random Access Memory
  • a DRAM with a 4F 2 cell structure and a vertical channel transistor has been developed.
  • the contact between the source/drain of the transistor and the memory cell is a silicon-containing active pillar that directly contacts the metal layer of the memory cell. Due to the The greater the resistance, the greater the contact resistance between the two, reducing the operating speed of the semiconductor device and reducing the performance of the semiconductor device.
  • Embodiments of the present disclosure provide a semiconductor structure and a semiconductor device, the metal silicide layer of which has smaller contact resistance, which can increase operating speed and reduce energy consumption.
  • Embodiments of the present disclosure also provide a method for preparing a semiconductor structure, which can reduce the contact resistance of the active pillar and increase the operating speed of the semiconductor structure.
  • a semiconductor structure including: a substrate, an active pillar, a gate structure, a metal suicide layer and an isolation layer.
  • active pillars are located on the substrate and are arranged in an array, and the active pillars extend in a direction perpendicular to the substrate; gate structures are located on the substrate and are arranged at intervals along the first direction, and is provided around a part of the active pillar; the metal silicide layer is located on the top surface of the active pillar, and the projection of the metal silicide layer on the substrate is in contact with the top surface of the active pillar.
  • the projections of the surfaces on the substrate coincide with each other; the isolation layer is located between the adjacent gate structures and the adjacent active pillars, and the height of the isolation layer is higher than the top of the metal silicide layer. The height of the surface.
  • the metal element in the metal silicide layer includes at least one of Co, Ni, Pt, Ti, Ta, Mo and W.
  • the gate structure includes: a gate insulating layer surrounding the side of the active pillar, and in a direction perpendicular to the substrate, the gate The top surface of the insulating layer is lower than the top surface of the metal silicide layer; the word line layer surrounds a portion of the side surface of the gate insulating layer.
  • a top surface of the gate insulating layer is lower than a top surface of the metal silicide layer by a distance of 5 ⁇ 40 nm.
  • the semiconductor structure further includes: a connection layer located on the metal silicide layer, and a projection of the connection layer on the substrate covers the metal silicide layer. projection on the substrate.
  • the isolation layer extends in a direction perpendicular to the substrate, and a top surface of the isolation layer is flush with a top surface of the connection layer.
  • a method for manufacturing a semiconductor structure including: providing a substrate having active pillars arranged in an array, the active pillars being arranged along a direction perpendicular to the substrate. extending in the direction; forming a gate structure, located on the substrate, arranged at intervals along the first direction, and surrounding a part of the active pillar; forming an isolation layer, the isolation layer is formed on the adjacent Between the gate structure and the adjacent active pillars, the height of the isolation layer is higher than the height of the top surface of the active pillars; a metal silicide layer is formed on the top surface of the active pillars. , and the projection of the metal silicide layer on the substrate coincides with the projection of the top surface of the active pillar on the substrate.
  • forming the gate structure includes: forming a gate insulating layer on a surface of the active pillar; and forming a word line layer around a portion of a side surface of the gate insulating layer.
  • forming a gate insulating layer on the surface of the active pillar includes: forming a first insulating layer on the surface of the active pillar; and filling a first isolation layer between the first insulating layer. layer; etching back the first insulating layer to a first preset depth to expose the first part of the active pillar; etching the sidewall of the first part to form a first pillar; on the first pillar A second insulating layer is formed on the surface, and the second insulating layer and the first insulating layer form the gate insulating layer.
  • forming a word line layer around a portion of the side surface of the gate insulating layer includes: filling a word line metal layer between adjacent second insulating layers; etching back the word line The metal layer reaches a second predetermined depth to form a word line layer.
  • forming an isolation layer includes: forming a second isolation layer between adjacent gate insulating layers and on the word line layer; the first isolation layer and the third isolation layer. Two isolation layers form the isolation layer.
  • a chemical mechanical polishing process is used to make the top surfaces of the first isolation layer, the second isolation layer and the second insulation layer flush .
  • the method further includes: removing the second insulating layer on a top surface of the first column to expose the top surface of the first column.
  • removing the second insulating layer on the top surface of the first pillar includes: etching back the second insulating layer, removing the second insulating layer on the top surface of the first pillar. a second insulating layer, and etching back the second insulating layer located on the side of the first pillar to a third preset depth.
  • the third preset depth is 5 ⁇ 40 nm.
  • removing the second insulating layer on the top surface of the first pillar includes etching and removing only the second insulating layer located on the top surface of the first pillar.
  • the forming the metal silicide layer includes: forming a first metal layer on a top surface of the active pillar; performing heat treatment on the active pillar, and forming a first metal layer on the top surface of the active pillar. A metal suicide layer is formed; the remaining first metal layer is removed.
  • the method further includes: forming a connection material layer on a top surface of the metal silicide layer, a top surface of the gate structure, and a top surface of the isolation layer; removing a portion of the The connection material layer exposes the isolation layer, and the remaining connection material layer forms a connection layer, and the top surface of the connection layer is flush with the top surface of the isolation layer.
  • a semiconductor device including: a semiconductor structure as described in any of the above embodiments and a memory unit; wherein the memory unit is electrically connected to the semiconductor structure through a connection layer.
  • the top surface of the active pillar of the semiconductor structure of the embodiment of the present disclosure has a metal silicide layer, and the metal silicide layer has a small resistance. Therefore, the active pillar of the present disclosure contacts the metal pad through the metal silicide layer, reducing The contact resistance is reduced, energy consumption is reduced, and the operating speed of the semiconductor structure is improved.
  • FIG. 1 is a top view of a semiconductor structure according to an exemplary embodiment of the present disclosure
  • Figure 2 is a cross-sectional view of the semiconductor structure along lines X-X and Y-Y of Figure 1;
  • FIG. 3 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure
  • FIGS. 4 to 17 are schematic diagrams of a semiconductor structure during a preparation process according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • plural means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.
  • “Above” and “below” are technical terms indicating orientation. These technical terms are only used to make the description clearer and do not have a limiting effect.
  • a semiconductor substrate has an active area and a bonding pad.
  • a transistor is disposed in the active area.
  • the bonding pad is electrically connected to the source/drain electrode of the transistor to provide a circuit for the semiconductor structure and connect the transistor to the memory unit. Electrical connection.
  • the source/drain electrode in the related art is generally an active area material containing silicon and has a large resistance, so the contact resistance with the pad is large.
  • FIG. 1 shows a top view of a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 2 shows a cross-sectional view of the semiconductor structure along lines X-X and Y-Y in FIG. 1 respectively.
  • the semiconductor structure of the embodiment of the present disclosure includes: a substrate 1 , an active pillar 3 , a gate structure 4 , a metal silicide layer 5 and an isolation layer 6 .
  • the active pillars 3 are located on the substrate 1 and arranged in an array, and the active pillars 3 extend in a direction perpendicular to the substrate 1 .
  • the gate structures 4 are located on the substrate 1 , are arranged at intervals along the first direction F1 , and surround a part of the active pillar 3 .
  • the metal silicide layer 5 is located on the top surface of the active pillar 3 , and the projection of the metal silicide layer 5 on the substrate 1 coincides with the projection of the top surface of the active pillar 3 on the substrate 1 .
  • the isolation layer 6 is located between the adjacent gate structures 4 and the adjacent active pillars 3 , and the height of the isolation layer 6 is higher than the height of the top surface of the metal silicide layer 5 .
  • the top surface of the active pillar 3 of the semiconductor structure in the embodiment of the present disclosure has a metal silicide layer 5.
  • the metal silicide layer 5 has a small resistance. Therefore, the active pillar 3 of the present disclosure communicates with the metal through the metal silicide layer 5.
  • the pad contact reduces the contact resistance, reduces energy consumption, and increases the operating speed of the semiconductor structure.
  • the material of the substrate 1 in the embodiment of the present disclosure can be silicon, silicon carbide, silicon nitride, silicon on insulator, silicon on insulator, silicon germanium on insulator, germanium on insulator. Silicon or insulator upper layer germanium, etc.
  • shallow trench isolations are formed in the substrate 1 and active areas are disposed between the shallow trench isolations.
  • Bit line 2 is connected to the active area.
  • the active pillar 3 in the embodiment of the present disclosure is formed by etching the substrate 1 , that is, the active pillar 3 and the substrate 1 may be integrated, and the active pillar 3 is located in the active area of the substrate 1 . To make the description clearer, the portion of the substrate located below the active pillar 3 may be named substrate 1 .
  • the metal elements of the metal silicide layer 5 include at least one of Co, Ni, Pt, Ti, Ta, Mo and W. These metal elements can combine with the silicon in the substrate 1 to form a stable Metal silicide, lowering resistance.
  • the gate structure 4 includes a gate insulating layer 41 surrounding the side of the active pillar 3 .
  • the gate insulating layer 41 The top surface of is lower than the top surface of the metal suicide layer 5 .
  • the gate insulating layer 41 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the gate structure 4 also includes a word line layer 42 surrounding a portion of the side surface of the gate insulating layer 41 . As shown in FIG. 1 , the word line layers 42 are spaced apart in the first direction F1, and each word line layer 42 extends along the second direction F2.
  • the word line layer 42 surrounding the surface of the gate insulating layer 41 can serve as a gate electrode, that is, the gate electrode can be a part of the word line layer 42.
  • the material of the word line layer 42 can include TiN, W , at least one of Al, Cu and Au.
  • the top surface of the gate insulating layer 41 is lower than the top surface of the metal silicide layer 5 , that is, the gate insulating layer 41 forms a concave surface on the periphery of the metal silicide layer 5 . groove. At least part of the connection layer 7 can be located in the groove, making the connection between the connection layer 7 and the active pillar 3 more stable.
  • the distance between the top surface of the gate insulating layer 41 and the top surface of the metal silicide layer 5 is 5-40 nm, that is, the depth of the above-mentioned groove is 5-40 nm.
  • the value of the distance may also be 25 nm or 30 nm or 35 nm or 38 nm, or the top surface of each gate insulating layer 41 is lower than the top surface of the metal silicide layer 5 .
  • the distance can also vary in the range of 5 to 40 nm depending on the position, that is, each groove does not have a uniform depth, and each groove can have different depths at different positions. Those skilled in the art can determine the distance according to actual conditions.
  • the bottom surface of the groove is higher than the bottom surface of the metal silicide layer 5 (the bottom surface of the metal silicide layer 5 close to the substrate 1 ) to avoid partial contact between the connection layer 7 and the active pillar 3 to achieve complete contact with the active pillar 3 .
  • the metal silicide layer 5 is in contact, reducing the contact resistance, and at the same time increasing the contact area between the connection layer 7 and the metal silicide layer 5, thereby increasing the operating speed of the semiconductor structure.
  • the semiconductor structure further includes a connection layer 7 . It is located on the metal silicide layer 5 , and the projection of the connection layer 7 on the substrate 1 covers the projection of the metal silicide layer 5 on the substrate 1 .
  • the connection layer 7 may be a pad metal and is electrically connected to the metal silicide layer 5 on the active pillar 3. Through the connection layer 7, the metal silicide layer 5 is electrically connected to the memory cell.
  • the material of the connection layer 7 may be at least one of TiN, W, Al, Cu and Au.
  • the isolation layer 6 extends in a direction perpendicular to the substrate 1 , and the top surface of the isolation layer 6 is flush with the top surface of the connection layer 7 to facilitate the placement of memory in subsequent processes. unit.
  • the semiconductor structure further includes bit lines 2.
  • the bit lines 2 are located in the substrate 1 and are spaced apart along the second direction F2.
  • the first direction F1 and the second direction F2 are not parallel.
  • the first direction F1 and the second direction F2 are perpendicular.
  • the material of the bit line 2 includes metal silicide, as shown in FIG. 2 , in which the area represented by the dotted ellipse is the metal silicide area 21 , that is, the area where the metal silicide is distributed in the bit line 2 .
  • the bit line 2 in the embodiment of the present disclosure is a buried bit line, which is formed by implanting impurity ions into the substrate 1 .
  • the bit line 2 formed only by impurity ion implantation is not made of metal, but is a silicon wiring doped with impurity ions, the bit line 2 has a high resistance.
  • the bit line 2 in the embodiment of the present disclosure includes metal silicide. Metal silicide has low resistance, which can reduce the resistance of the bit line 2 and reduce the energy consumption of the semiconductor structure during operation.
  • the active pillar 3 of the semiconductor structure in the embodiment of the present disclosure has a metal silicide layer 5 on the top surface.
  • the metal silicide layer 5 has a small resistance. Therefore, the active pillar 3 of the present disclosure passes through the metal silicide layer. 5 is in contact with the metal pad (connection layer 7), which reduces the contact resistance, reduces energy consumption, and increases the operating speed of the semiconductor structure.
  • FIG. 3 is a flow chart of a method for preparing a semiconductor structure
  • FIGS. 4 to 17 are schematic structural diagrams of a semiconductor structure during the preparation process.
  • the method for preparing a semiconductor structure according to an embodiment of the present disclosure includes:
  • Step S200 Provide a substrate 1 with active pillars 3 arranged in an array, and the active pillars 3 extend in a direction perpendicular to the substrate 1.
  • Step S400 Form gate structures 4, located on the substrate 1, arranged at intervals along the first direction F1, and surrounding a part of the active pillar 3.
  • Step S600 Form an isolation layer 6.
  • the isolation layer 6 is formed between the adjacent gate structures 4 and the adjacent active pillars 3.
  • the height of the isolation layer 6 is higher than the height of the top surface of the active pillar 3.
  • Step S800 Form a metal silicide layer 5 located on the top surface of the active pillar 3, and the projection of the metal silicide layer 5 on the substrate 1 coincides with the projection of the top surface of the active pillar 3 on the substrate 1.
  • the method for preparing a semiconductor structure according to the embodiment of the present disclosure can reduce the contact resistance of the active pillar 3 and increase the operating speed of the semiconductor structure by forming the metal silicide layer 5 on the top surface of the active pillar 3 .
  • Step S200 Provide a substrate 1 with active pillars 3 arranged in an array, and the active pillars 3 extend in a direction perpendicular to the substrate 1.
  • a substrate 1 is provided, a mask layer (not shown in the figure) is formed on the substrate 1 , and an array-arranged active pillar pattern is formed on the mask layer.
  • the substrate 1 is etched using an etching process to form active pillars 3 arranged in an array.
  • the etching process may be a wet etching process.
  • the wet etching may use concentrated sulfuric acid and hydrogen peroxide as etchants.
  • the etching depth is adjusted to control the active pillar 3 the height of.
  • the etching process may be a dry etching process. Dry etching has good shape retention and can form vertical active pillars.
  • the substrate 1 is a silicon substrate
  • the active pillar 3 is a silicon pillar
  • Step S400 Form gate structures 4.
  • the gate structures 4 are located on the substrate 1, are arranged at intervals along the first direction F1, and surround a part of the active pillar 3. Specifically, it may include steps S401 to S402.
  • Step S401 Form a gate insulating layer 41 on the surface of the active pillar 3.
  • a first insulating layer 411 is formed on the surface of the active pillar 3 .
  • the first insulating layer 411 can be formed through a deposition process, such as chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD) or physical vapor deposition (Physical Vapor Deposition, PVD).
  • the first insulating layer 411 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the first isolation layer 61 is filled between the first insulation layers 411 .
  • the first isolation layer 61 may be silicon nitride or silicon oxynitride.
  • the first isolation layer 61 is used to insulate and isolate adjacent active pillars 3 .
  • the height of the first isolation layer 61 is higher than the height of the top surface of the active pillar 3 .
  • the first insulating layer 411 is etched back to a first preset depth to expose the first part of the active pillar 3 .
  • the first insulating layer 411 can be etched back using a wet etching process or a dry etching process.
  • the dry etching process can be a plasma etching process.
  • the etching gas used in the plasma etching process can be chlorine.
  • the degree of etching By controlling the amount of etching gas, it can Control the degree of etching; wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the degree of etching can also be controlled, thereby regulating the value of the first preset depth.
  • the first preset depth can be set according to the actual situation of the semiconductor structure, and is not specifically limited here. As shown in Figure 8, the sidewall of the first part of the active pillar 3 is etched to form the first pillar 31, so that the critical dimensions of the first pillar 31 are reduced compared to the critical dimensions of other parts of the active pillar 3, Afterwards, the first column 31 is cleaned. As shown in FIG.
  • a second insulating layer 412 is formed on the surface of the first pillar 31 , and the second insulating layer 412 and the first insulating layer 411 form a gate insulating layer 41 .
  • the second insulating layer 412 may be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
  • the second insulating layer 412 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the first insulating layer 411 and the second insulating layer 412 are formed using the same deposition process, and the first insulating layer 411 and the second insulating layer 412 are made of the same material, which can simplify the process and make the first insulating layer The connection between layer 411 and second insulating layer 412 is more stable.
  • Step S402 Form a word line layer 42 around a part of the side surface of the gate insulating layer 41.
  • word line metal layer 421 is filled between adjacent second insulating layers 412 .
  • the word line metal layer 421 can be filled using a deposition process, and the material of the word line metal layer 421 can include at least one of TiN, W, Al, Cu, and Au.
  • the word line metal layer 421 is etched back to a second predetermined depth to form the word line layer 42 .
  • the word line layer 42 can serve as a gate electrode of the gate structure 4 .
  • the second preset depth can be set according to the required height of the gate electrode, which is not specifically limited here.
  • Step S600 Form an isolation layer 6.
  • the isolation layer 6 is formed between the adjacent gate structures 4 and the adjacent active pillars 3.
  • the height of the isolation layer 6 is higher than the height of the top surface of the metal silicide layer 5.
  • the isolation layer 6 is formed between two adjacent active pillars 3 in which the gate insulating layer 41 and the word line layer 42 are formed.
  • a second isolation layer 62 is formed between adjacent gate insulating layers 41 and on the word line layer 42 , so that the second isolation layer 62 and the above-mentioned first isolation layer 61 form the isolation layer 6 . That is, the second isolation layer 62 is filled between the adjacent active pillars 3 formed with the gate insulating layer 41 and the word line layer 42, so that the adjacent active pillars 3 are completely insulated and isolated.
  • the second isolation layer 62 may be silicon nitride or silicon oxynitride.
  • the top surfaces of the first isolation layer 61 and the second isolation layer 62 are flush, so that the top surface of the isolation layer 6 formed by the two is higher than the top surface of the active pillar 3, which provides the basis for the subsequent formation of the connection layer 7.
  • the first isolation layer 61 and the second isolation layer 62 may be formed using the same process, for example, at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process may be used.
  • the layer 61 and the second isolation layer 62 are made of the same material, so that the process can be simplified and the stability of the connection between the first isolation layer 61 and the second isolation layer 62 can be improved.
  • a chemical mechanical polishing process may be used to make the top surfaces of the second isolation layer 62 , the first isolation layer 61 and the second insulating layer 412 flush, This further flattens the top surface of the semiconductor structure in this step, which facilitates subsequent processing.
  • the method further includes: removing the second insulating layer 412 on the top surface of the first pillar 31 to expose the top surface of the first pillar 31 .
  • removing the second insulating layer 412 on the top surface of the first pillar 31 includes: etching back the second insulating layer 412 and removing the second insulation layer on the top surface of the first pillar 31 . layer 412, and etch back the second insulating layer 412 located on the side of the first pillar 31 to a third preset depth, so that the top surface of the gate insulating layer 41 is lower than the first pillar in the direction perpendicular to the substrate 1 31 on top. That is, the groove G is formed on the periphery of the top of the active pillar 3 .
  • the depth of the groove G is the third preset depth.
  • the third preset depth can be set according to actual conditions, and is not specifically limited here.
  • the first metal layer 51 will be formed on the active pillar 3. The provision of the groove G improves the stability of the first metal layer 51.
  • the third preset depth is 5 ⁇ 40nm. Specifically, in addition to the two end values of the above range, the value of the third preset depth can also be 25nm or 30nm or 35nm or 38nm. The third preset depth ranges from 5 to 40nm depending on the location. Change, that is, each groove G does not have a uniform depth, and each groove G can have different depths at different positions. Those skilled in the art can make a choice according to actual needs, and there is no special limitation here.
  • removing the second insulating layer 412 on the top surface of the first pillar 31 includes: only etching and removing the second insulating layer 412 on the top surface of the first pillar 31 without etching down the second insulating layer 412 .
  • the second insulating layer 412 does not need to form the groove G in the above embodiment. In this way, the process can be simplified and time can be saved.
  • Step S800 Form a metal silicide layer 5 located on the top surface of the active pillar 3, and the projection of the metal silicide layer 5 on the substrate 1 coincides with the projection of the top surface of the active pillar 3 on the substrate 1.
  • step S800 may include steps S801 to S803.
  • Step S801 As shown in FIG. 14 , a first metal layer 51 is formed on the top surface of the active pillar 3 .
  • the first metal layer 51 may be formed on the top surface of the active pillar 3 using a deposition process.
  • the first metal layer may be at least one of Co, Ni, Pt, Ti, Ta, Mo and W.
  • the deposition process may be Physical vapor deposition.
  • Step S802 As shown in FIG. 14 and FIG. 15 , heat treatment is performed on the active pillar 3 to form a metal silicide layer 5 on the top of the active pillar 3 .
  • the heat treatment may be annealing to react the metal of the first metal layer 51 with the active pillar 3 , and the top of the active pillar 3 is doped with metal silicide, such as CoSix, NiSix or TiSix, to form the metal silicide layer 5 . Since the top of the active pillar 3 is metal silicide, the resistance of the top of the active pillar 3 is reduced, and the contact resistance between the active pillar 3 and the pad metal is reduced.
  • the annealing temperature can be 400°C ⁇ 1000°C.
  • the annealing temperature can also be 500°C, 600°C, 700°C, 800°C or 900°C, or the annealing temperature can be between It changes within the range of 400°C ⁇ 1000°C, and there is no special limit here.
  • Steps S801 and S802 are a salicide process, which does not require a photolithography patterning process to form metal silicide, thus simplifying the preparation process.
  • Step S803 As shown in Figure 15, remove the remaining first metal layer 51. Specifically, the remaining first metal layer 51 may be removed through an etching process.
  • the etching process can be wet etching or dry etching, and those skilled in the art can choose according to the actual situation, and there is no special limitation here.
  • the method for preparing a semiconductor structure of the present disclosure also includes: forming a connection material on the top surface of the metal silicide layer 5 , the top surface of the gate structure 4 and the top surface of the isolation layer 6 Layer 71.
  • step 604 since a groove G is formed on the periphery of the top of the active pillar 3 , the bottom of the connection material layer 71 is formed in the groove G. Therefore, increasing The stability of the connecting material layer 71 is improved.
  • the method for preparing a semiconductor structure according to an embodiment of the present disclosure also includes: removing part of the connection material layer 71 to expose the isolation layer 6 , and the remaining connection material layer 71 forms the connection layer 7 .
  • the top surface of layer 7 is flush with the top surface of isolation layer 6 .
  • connection layer 7 above the adjacent active pillar 3 can be insulated and isolated, and the surface of the semiconductor structure can be planarized, which is beneficial to the arrangement of memory cells.
  • connection layer 7 on the substrate 1 covers the projection of the metal silicide layer 5 on the substrate 1 , so that the connection layer 7 and the metal silicide layer 5 are in full contact.
  • the connection layer 7 can be understood as a metal pad, which is electrically connected to the metal silicide layer 5 to realize the electrical connection between the active pillar 3 and the memory cell (not shown in the figure) located above the metal pad.
  • the material of the connection layer 7 is at least one of TiN, W, Al, Cu and Au.
  • the bottom surface of the groove G is higher than the bottom surface of the metal silicide layer 5, preventing the connection layer 7 from partially contacting the active pillar 3, realizing complete contact with the metal silicide layer 5, reducing the contact resistance, and at the same time increasing The contact area between the connection layer 7 and the metal silicide layer 5 is increased, thereby increasing the operating speed of the semiconductor structure.
  • step S300 may also be included: forming bit lines 2, which are located in the substrate 1 and arranged at intervals along the second direction F2. As shown in FIG. 1 , the second direction F2 is not parallel to the first direction F1. For example, the second direction F2 is perpendicular to the first direction F1.
  • forming the bit line 2 may include steps S301 to S304.
  • Step S301 Form bit lines 2 in the substrate 1 between the active pillars 3 along the second direction F2.
  • an ion implantation process can be used to dope impurity ions into the substrate 1 located between the active pillars 3 along the second direction F2 to form the bit lines 2 , or the substrate 1 located below the active pillars 3 can be doped with impurity ions.
  • the above-mentioned impurity ions are doped into bottom 1 to form bit line 2.
  • Step S302 Form a second metal layer on the bit line 2.
  • a deposition process can be used to form a metal layer above the bit line 2.
  • the second metal layer is deposited on the surface of the area corresponding to the dotted ellipse.
  • the second metal layer may be at least one of Co, Ni, Pt, Ti, Ta, Mo and W, and the deposition process may be physical vapor deposition (Physical Vapor Deposition, PVD).
  • Step S303 Heat treatment is performed on the substrate 1 to form a bit line 2 doped with metal silicide.
  • the heat treatment may be annealing to react the metal of the second metal layer with the silicon of the bit line 2 to form the bit line 2 doped with metal silicide, the metal silicide being located on the metal silicide shown in FIG. 4 Within area 21. Since bit line 2 has metal silicide, such as CoSix, NiSix or TiSix, the resistance of bit line 2 is reduced.
  • the annealing temperature can be 400°C ⁇ 1000°C.
  • the annealing temperature can also be 500°C, 600°C, 700°C, 800°C or 900°C, or the annealing temperature can be between It changes within the range of 400°C ⁇ 1000°C, and there is no special limit here.
  • Steps S402 and S403 are a salicide process, which does not require a photolithography patterning process to form metal silicide, thus simplifying the preparation process.
  • Step S304 Remove the remaining second metal layer.
  • the remaining second metal layer may be removed through an etching process.
  • the etching process can be wet etching or dry etching, and those skilled in the art can choose according to the actual situation, and there is no special limitation here.
  • the metal silicide in the bit line 2 and the metal silicide layer 5 have the same metal element, which can simplify the process and save energy consumption.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure forms the metal silicide layer 5 on the top surface of the active pillar 3, so that the top surface of the active pillar 3 has a smaller resistance, thus reducing the resistance of the active pillar 3.
  • the disclosed contact resistance between the active pillar 3 and the metal pad reduces energy consumption and increases the operating speed of the semiconductor structure.
  • a semiconductor device including the semiconductor structure described in any of the above embodiments and a memory unit.
  • the memory unit is electrically connected to the semiconductor structure through the connection layer 7 .
  • the semiconductor structure and connection layer 7 are the same as in the above embodiment, and will not be described again here.
  • the semiconductor device of the embodiment of the present disclosure has a metal silicide layer 5 on the active pillar 3 in the semiconductor structure and has a smaller contact resistance, which can increase the operating speed of the semiconductor device and reduce energy consumption.

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Abstract

一种半导体结构及其制备方法、半导体装置。该半导体结构包括衬底、有源柱、栅极结构、金属硅化物层和隔离层。其中，有源柱位于衬底上并且阵列排布，有源柱沿垂直于衬底的方向延伸；栅极结构位于衬底上，沿第一方向间隔排布，并环绕设于有源柱的一部分；金属硅化物层位于有源柱的顶面上，且金属硅化物层在衬底上的投影和有源柱的顶面在衬底的投影重合；隔离层位于相邻的所述栅极结构以及相邻的所述有源柱之间，所述隔离层的高度高于所述金属硅化物层的顶面的高度。

Description

半导体器件的制备方法及半导体器件
交叉引用
本公开要求于2022年4月26日提交的申请号为202210451603.8、名称为“半导体结构及其制备方法、半导体装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其制备方法、半导体装置。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。目前已经开发出具有4F 2单元结构和垂直沟道晶体管的DRAM，其中晶体管的源极/漏极与存储单元的接触为含硅有源柱直接与存储单元的金属层接触，而由于硅柱的电阻较大，使二者的接触电阻较大，半导体器件的运行速度减小，降低半导体器件的性能。
发明内容
本公开实施例提供一种半导体结构和半导体装置，其金属硅化物层具有较小的接触电阻，能够提高运行速度，减少能耗。
本公开实施例还提供了一种半导体结构的制备方法，能够减小有源柱的接触电阻，提高半导体结构的运行速度。
根据本公开的一方面，提供一种半导体结构，包括：衬底、有源柱、栅极结构、金属硅化物层和隔离层。其中，有源柱位于所述衬底上并且阵列排布，所述有源柱沿垂直于所述衬底的方向延伸；栅极结构位于所述衬底上，沿第一方向间隔排布，并环绕设于所述有源柱的一部分；金属硅化物层位于所述有源柱的顶面上，且所述金属硅化物层在所述衬底上的投影和所述有源柱的顶面在所述衬底上的投影重合；隔离层位于相邻的所述栅极结构以及相邻的所述有源柱之间，所述隔离层的高度高于所述金属硅化物层的顶面的高度。
根据本公开的示例性实施方式，所述金属硅化物层中的金属元素包括Co、Ni、Pt、Ti、Ta、Mo和W中的至少一种。
根据本公开的示例性实施方式，所述栅极结构包括：栅绝缘层，所述栅绝缘层环绕设 于所述有源柱的侧面，在垂直于所述衬底的方向上，所述栅绝缘层的顶面低于所述金属硅化物层的顶面；字线层，环绕设于所述栅绝缘层侧面的一部分。
根据本公开的示例性实施方式，所述栅绝缘层的顶面低于所述金属硅化物层的顶面的距离为5～40nm。
根据本公开的示例性实施方式，所述半导体结构还包括：连接层，位于所述金属硅化物层上，且所述连接层在所述衬底上的投影覆盖所述金属硅化物层在所述衬底上的投影。
根据本公开的示例性实施方式，所述隔离层沿垂直于所述衬底的方向延伸，且所述隔离层的顶面与所述连接层的顶面平齐。
根据本公开的另一方面，提供一种半导体结构的制备方法，包括：提供衬底，所述衬底上具有阵列排布的有源柱，所述有源柱沿垂直于所述衬底的方向延伸；形成栅极结构，位于所述衬底上，沿第一方向间隔排布，并环绕设于所述有源柱的一部分；形成隔离层，所述隔离层形成于相邻的所述栅极结构以及相邻的所述有源柱之间，所述隔离层的高度高于所述有源柱的顶面的高度；形成金属硅化物层，位于所述有源柱的顶面上，且所述金属硅化物层在所述衬底上的投影和所述有源柱的顶面在所述衬底的投影重合。
根据本公开的示例性实施方式，形成栅极结构包括：在所述有源柱的表面形成栅绝缘层；在所述栅绝缘层的侧面的一部分环绕形成字线层。
根据本公开的示例性实施方式，在所述有源柱的表面形成栅绝缘层包括：在所述有源柱的表面形成第一绝缘层；在所述第一绝缘层之间填充第一隔离层；回蚀刻所述第一绝缘层至第一预设深度，露出所述有源柱的第一部分；蚀刻所述第一部分的侧壁，形成第一柱体；在所述第一柱体的表面形成第二绝缘层，所述第二绝缘层和所述第一绝缘层形成所述栅绝缘层。
根据本公开的示例性实施方式，在所述栅绝缘层的侧面的一部分环绕形成字线层包括：在相邻的所述第二绝缘层之间填充字线金属层；回蚀刻所述字线金属层至第二预设深度，形成字线层。
根据本公开的示例性实施方式，形成隔离层包括：在相邻的所述栅绝缘层之间，且在所述字线层上形成第二隔离层；所述第一隔离层和所述第二隔离层形成所述隔离层。
根据本公开的示例性实施方式，在形成所述第二隔离层后，利用化学机械研磨工艺使所述第一隔离层、所述第二隔离层和所述第二绝缘层的顶面平齐。
根据本公开的示例性实施方式，所述方法还包括：去除所述第一柱体的顶面的所述第二绝缘层，露出所述第一柱体的顶面。
根据本公开的示例性实施方式，去除所述第一柱体的顶面的所述第二绝缘层包括：回蚀刻所述第二绝缘层，去除所述第一柱体的顶面的所述第二绝缘层，并将位于所述第一柱体侧面的所述第二绝缘层回蚀刻至第三预设深度。
根据本公开的示例性实施方式，所述第三预设深度为5～40nm。
根据本公开的示例性实施方式，去除所述第一柱体的顶面的所述第二绝缘层包括：仅蚀刻去除位于所述第一柱体顶面的所述第二绝缘层。
根据本公开的示例性实施方式，所述形成金属硅化物层包括：在所述有源柱的顶面形成第一金属层；对所述有源柱进行热处理，在所述有源柱的顶部形成金属硅化物层；去除剩余的所述第一金属层。
根据本公开的示例性实施方式，所述方法还包括：在所述金属硅化物层的顶面、所述栅极结构的顶面以及所述隔离层的顶面形成连接材料层；去除部分所述连接材料层，露出所述隔离层，剩余的所述连接材料层形成连接层，所述连接层的顶面与所述隔离层的顶面平齐。
根据本公开的另一方面，提供一种半导体装置，包括：如上述任一实施方式所述的半导体结构和存储单元；其中，存储单元，通过一连接层与所述半导体结构电连接。
由上述技术方案可知，本公开具备以下优点和积极效果中的至少之一：
本公开实施例的半导体结构的有源柱的顶面具有金属硅化物层，金属硅化物层具有较小的电阻，因此，本公开的有源柱通过金属硅化物层与金属焊盘接触，减小了接触电阻，降低能耗，提高了半导体结构的运行速度。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1为本公开示例性实施例的半导体结构的俯视图；
图2为沿图1的X-X和Y-Y线的半导体结构的剖面图；
图3为本公开示例性实施方式的半导体结构的制备方法的流程图；
图4至图17为本公开示例性实施方式的半导体结构在制备过程中的示意图。
附图标记说明：
1、衬底；2、位线；21、金属硅化物区域；3、有源柱；31、第一柱体；4、栅极结构；41、栅绝缘层；411、第一绝缘层；412、第二绝缘层；42、字线层；421、字线金属层；5、金属硅化物层；51、第一金属层；6、隔离层；61、第一隔离层；62、第二隔离层；7、连 接层；71、连接材料层；F1、第一方向；F2、第二方向；G、凹槽。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在对本公开的不同示例性实施方式的下面描述中，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。此外，权利要求书中的术语“第一”、“第二”等仅作为标记使用，不是对其对象的数字限制。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解，而有的操作/步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
另外，在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。“上方”和“下方”是表示方位的技术术语，该技术术语仅仅是为了使描述更加清楚，不具有限定作用。
在相关技术中，半导体衬底具有有源区和焊盘，有源区中设有晶体管，焊盘与晶体管中的源/漏极电性连接，为半导体结构提供电路，并将晶体管与存储单元电性连接。相关技术中的源/漏极一般为含硅的有源区材料，电阻较大，因此与焊盘的接触电阻较大。
根据本公开的一方面，提供一种半导体结构。如图1和图2所示，其中，图1示出了本公开实施例的半导体结构的俯视图，图2示出了分别沿着图1中的X-X和Y-Y线的半导体结构的剖面图。如图1和图2所示，本公开实施例的半导体结构包括：衬底1、有源柱3、栅极结构4、金属硅化物层5和隔离层6。其中，有源柱3位于衬底1上并且阵列排布，有源柱3沿垂直于衬底1的方向延伸。栅极结构4位于衬底1上，沿第一方向F1间隔排布，并环绕设于有源柱3的一部分。金属硅化物层5位于有源柱3的顶面上，且金属硅化物层5在衬底1上的投影和有源柱3的顶面在衬底1的投影重合。隔离层6位于相邻的栅极结构4以及相邻的有源柱3之间，隔离层6的高度高于金属硅化物层5的顶面的高度。
本公开实施例的半导体结构的有源柱3的顶面具有金属硅化物层5，金属硅化物层5 具有较小的电阻，因此，本公开的有源柱3通过金属硅化物层5与金属焊盘接触，减小了接触电阻，降低能耗，提高了半导体结构的运行速度。
下面对本公开实施例的半导体结构进行详细的说明。
本公开实施例中的“上”、“下”是表示相对位置的方位词，如在图2中，有源柱3位于衬底1上，则衬底1位于有源柱3下，该方位词仅为了表达清楚，不具有限定意义。
如图1和图2所示，本公开实施例的衬底1的材料可以为硅、碳化硅、氮化硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上层锗化硅或绝缘体上层锗等。
在一些实施例中，在衬底1中形成有浅沟槽隔离(图中未示出)，浅沟槽隔离之间设有有源区。位线2与有源区连接。本公开实施例中的有源柱3通过蚀刻衬底1而形成，即有源柱3与衬底1可以是一体的，有源柱3位于衬底1的有源区。为了使描述更加清楚，可将位于有源柱3下方的衬底部分命名为衬底1。
在一些实施例中，金属硅化物层5的金属元素均包括Co、Ni、Pt、Ti、Ta、Mo和W中的至少一种，这些金属元素能够与衬底1中的硅结合形成稳定的金属硅化物，降低电阻。
在一些实施例中，如图2所示，栅极结构4包括栅绝缘层41，栅绝缘层41环绕设于有源柱3的侧面，在垂直于衬底1的方向上，栅绝缘层41的顶面低于金属硅化物层5的顶面。其中，栅绝缘层41可以包括氧化硅、氮化硅和氮氧化硅中的至少一种。
栅极结构4还包括字线层42，环绕设于栅绝缘层41的侧面的一部分。如图1所示，字线层42在第一方向F1上间隔设置，每个字线层42沿第二方向F2延伸。其中，环绕设于栅绝缘层41的表面的字线层42可以作为栅电极，即栅电极可以是字线层42的一部分，在一些实施例中，字线层42的材料可以包括TiN、W、Al、Cu和Au中的至少一种。
如图2所示，在垂直于衬底1的方向上，栅绝缘层41的顶面低于金属硅化物层5的顶面，即该栅绝缘层41在金属硅化物层5的外围形成凹槽。至少部分连接层7可以位于该凹槽中，使连接层7与有源柱3的连接更加稳定。
在一些实施例中，栅绝缘层41的顶面低于金属硅化物层5的顶面的距离为5～40nm，即上述的凹槽的深度为5～40nm。具体地，除了上述范围的两个端值外，该距离的值还可以为25nm或30nm或35nm或38nm，或者每个栅绝缘层41的顶面低于金属硅化物层5的顶面的该距离也可以随着位置的不同而在5～40nm的范围内变化，即每个凹槽并非具有均匀的深度，每个凹槽的不同位置处可以具有不同的深度，本领域技术人员可以根据实际需求进行选择，此处不做特殊限定。在一些实施例中，凹槽的底面高于金属硅化物层5的底面(金属硅化物层5的靠近衬底1的底面)，避免连接层7与有源柱3部分接触，实现其完全与金属硅化物层5接触，减小接触电阻，同时增加了连接层7与金属硅化物层5的接触面积，提高半导体结构的运行速度。
在一些实施例中，如图2所示，半导体结构还包括连接层7。位于金属硅化物层5上，且连接层7在衬底1上的投影覆盖金属硅化物层5在衬底1上的投影。该连接层7可以是 焊盘金属，与有源柱3上的金属硅化物层5电性连接，通过该连接层7，实现金属硅化物层5与存储单元的电连接。在一些实施例中，该连接层7的材料可以是TiN、W、Al、Cu和Au中的至少一种。
在一些实施例中，如图2所示，隔离层6沿垂直于衬底1的方向延伸，且隔离层6的顶面与连接层7的顶面平齐，以便于在后续工艺中设置存储单元。
在一些实施例中，半导体结构还包括位线2，如图1所示，位线2位于衬底1中，并沿第二方向F2间隔排布。其中，第一方向F1和第二方向F2不平行，如图1所示，第一方向F1和第二方向F2垂直。位线2的材料包括金属硅化物，如图2所示，其中虚线椭圆表示的区域为金属硅化物区域21，即位线2中的金属硅化物分布的区域。本公开实施例中的位线2为埋入式位线，通过将杂质离子注入衬底1中形成。由于仅通过杂质离子注入形成的位线2并非为金属，而是掺杂有杂质离子的硅布线，使得位线2具有较高的电阻。为了降低位线2的电阻，本公开实施例中的位线2包括金属硅化物。金属硅化物具有较低的电阻，能够使位线2的电阻降低，减少半导体结构在运行中的能耗。
综上，本公开实施例的半导体结构的有源柱3的顶面具有金属硅化物层5，金属硅化物层5具有较小的电阻，因此，本公开的有源柱3通过金属硅化物层5与金属焊盘(连接层7)接触，减小了接触电阻，降低能耗，提高了半导体结构的运行速度。
根据本公开的另一方面，提供了一种半导体结构的制备方法。如图3至图17所示，其中图3为半导体结构的制备方法的流程图，图4至图17为半导体结构在制备过程中的结构示意图。如图3所示，本公开实施例的半导体结构的制备方法包括：
步骤S200：提供衬底1，衬底1上具有阵列排布的有源柱3，有源柱3沿垂直于衬底1的方向延伸。
步骤S400：形成栅极结构4，位于衬底1上，沿第一方向F1间隔排布，并环绕设于有源柱3的一部分。
步骤S600：形成隔离层6，隔离层6形成于相邻的栅极结构4以及相邻的有源柱3之间，隔离层6的高度高于有源柱3的顶面的高度。
步骤S800：形成金属硅化物层5，位于有源柱3的顶面上，且金属硅化物层5在衬底1上的投影和有源柱3的顶面在衬底1的投影重合。
本公开实施例的半导体结构的制备方法，通过在有源柱3的顶面上形成金属硅化物层5，能够减小有源柱3的接触电阻，提高半导体结构的运行速度。
下面对本公开实施例的半导体结构的制备方法进行详细的描述。
步骤S200：提供衬底1，衬底1上具有阵列排布的有源柱3，有源柱3沿垂直于衬底1的方向延伸。
如图4所示，提供衬底1，在衬底1上形成掩膜层(图中未示出)，并在掩膜层上形成阵列排布的有源柱图案。根据有源柱图案，利用蚀刻工艺蚀刻该衬底1，形成阵列排布 的有源柱3。在一些实施例中，该蚀刻工艺可以是湿法蚀刻工艺，湿法蚀刻可以利用浓硫酸和双氧水作为蚀刻剂，通过调控蚀刻剂的浓度与配比，来调节蚀刻深度，以调控有源柱3的高度。在一些实施例中，该蚀刻工艺可以是干法蚀刻工艺，干法刻蚀具有良好的保型性，可以形成竖直的有源柱。
在一些实施例中，衬底1为硅衬底，有源柱3为硅柱。
步骤S400：形成栅极结构4，该栅极结构4位于衬底1上，沿第一方向F1间隔排布，并环绕设于有源柱3的一部分。具体地，可以包括步骤S401至步骤S402。
步骤S401：在有源柱3的表面形成栅绝缘层41。如图5所示，在有源柱3的表面形成第一绝缘层411。其中，第一绝缘层411可以通过沉积工艺形成，如化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic Layer Deposition,ALD)或物理气相沉积((Physical Vapor Deposition，PVD))。第一绝缘层411可以包括氧化硅、氮化硅和氮氧化硅中的至少一种。如图6所示，在第一绝缘层411之间填充第一隔离层61。第一隔离层61可以是氮化硅或氮氧化硅，第一隔离层61用于绝缘隔离相邻的有源柱3。继续参考图6，在一些实施例中，第一隔离层61的高度高于有源柱3的顶面的高度。如图7所示，回蚀刻第一绝缘层411至第一预设深度，露出有源柱3的第一部分。回蚀刻第一绝缘层411可以采用湿法蚀刻工艺或干法蚀刻工艺，干法蚀刻工艺可以是等离子体蚀刻工艺，等离子体蚀刻工艺采用的蚀刻气体可以为氯气，通过控制蚀刻气体的用量，可以控制蚀刻程度；湿法蚀刻可以利用浓硫酸和双氧水作为蚀刻剂，通过调整蚀刻剂的浓度，也可以控制蚀刻程度，进而调控第一预设深度的值。该第一预设深度可以根据半导体结构的实际情况设置，此处不做特殊限定。如图8所示，蚀刻有源柱3的第一部分的侧壁，形成第一柱体31，使得第一柱体31的关键尺寸相较于有源柱3的其他部分的关键尺寸减小，之后对第一柱体31进行清洗。如图9所示，在第一柱体31的表面形成第二绝缘层412，第二绝缘层412和第一绝缘层411形成栅绝缘层41。第二绝缘层412可以通过沉积工艺形成，如化学气相沉积、原子层沉积或物理气相沉积。第二绝缘层412可以包括氧化硅、氮化硅和氮氧化硅中的至少一种。在一些实施例中，第一绝缘层411与第二绝缘层412采用相同的沉积工艺形成，且第一绝缘层411与第二绝缘层412的材质相同，如此可以简化工艺，并且使得第一绝缘层411和第二绝缘层412的连接更加稳定。
步骤S402：在栅绝缘层41的侧面的一部分环绕形成字线层42。如图10所示，在相邻的第二绝缘层412之间填充字线金属层421。可以利用沉积工艺填充该字线金属层421，字线金属层421的材料可以包括TiN、W、Al、Cu和Au中的至少一种。如图11所示，回蚀刻字线金属层421至第二预设深度，形成字线层42。该字线层42可以作为栅极结构4的栅电极。可以根据所需栅电极的高度来设置第二预设深度，此处不做特殊限定。
步骤S600：形成隔离层6，隔离层6形成于相邻的栅极结构4以及相邻的有源柱3之间，隔离层6的高度高于金属硅化物层5的顶面的高度。
具体地，在相邻的两个形成有栅绝缘层41和字线层42的有源柱3之间形成隔离层6。如图12所示，在相邻的栅绝缘层41之间，且在字线层42上形成第二隔离层62，使第二隔离层62和上述的第一隔离层61形成隔离层6。即在相邻的形成有栅绝缘层41和字线层42的有源柱3之间填充第二隔离层62，使得上述相邻的有源柱3完全绝缘隔离。其中，第二隔离层62可以是氮化硅或氮氧化硅。在一些实施例中，第一隔离层61和第二隔离层62的顶面平齐，使得二者形成的隔离层6的顶面高于有源柱3的顶面，为后续形成连接层7提供空间。在一些实施例中，第一隔离层61和第二隔离层62可以采用相同的工艺形成，例如可以采用化学气相沉积工艺、物理气相沉积工艺和原子层沉积工艺中的至少一种，第一隔离层61和第二隔离层62的材料相同，如此，能够简化工艺，并且提高第一隔离层61和第二隔离层62连接的稳定性。
在一些实施例中，继续参考图12，在形成第二隔离层62后，可以利用化学机械研磨工艺使第二隔离层62、第一隔离层61和第二绝缘层412的顶面平齐，进而使得该步骤中的半导体结构的顶面平坦化，利于后续加工。
在一些实施例中，如图13所示，该方法还包括：去除第一柱体31的顶面的第二绝缘层412，露出第一柱体31的顶面。
在一些实施例中，如图13所示，去除第一柱体31的顶面的第二绝缘层412包括：回蚀刻第二绝缘层412，去除第一柱体31的顶面的第二绝缘层412，并将位于第一柱体31侧面的第二绝缘层412回蚀刻至第三预设深度，使栅绝缘层41的顶面在垂直于衬底1的方向上低于第一柱体31的顶面。即在有源柱3的顶部的外围形成凹槽G。该凹槽G的深度即为第三预设深度。该第三预设深度可以根据实际情况设置，此处不做特殊限定。在后续的工艺中，会在有源柱3上形成第一金属层51，该凹槽G的设置，提高了第一金属层51的稳定性。
该第三预设深度为5～40nm。具体地，除了上述范围的两个端值外，该第三预设深度的值还可以为25nm或30nm或35nm或38nm，第三预设深度随着位置的不同而在5～40nm的范围内变化，即每个凹槽G并非具有均匀的深度，每个凹槽G的不同位置处可以具有不同的深度，本领域技术人员可以根据实际需求进行选择，此处不做特殊限定。
在另一些实施例中，去除第一柱体31的顶面的第二绝缘层412包括：仅蚀刻去除位于第一柱体31顶面的第二绝缘层412，而无需再向下蚀刻该第二绝缘层412，即无需形成上述实施例中的凹槽G。如此，可以简化工艺过程，节省时间。
步骤S800：形成金属硅化物层5，位于有源柱3的顶面上，且金属硅化物层5在衬底1上的投影和有源柱3的顶面在衬底1的投影重合。
具体地，在一些实施例中，步骤S800可以包括步骤S801至步骤S803。
步骤S801：如图14所示，在有源柱3的顶面形成第一金属层51。可以利用沉积工艺在有源柱3的顶面形成第一金属层51，该第一金属层可以是Co、Ni、Pt、Ti、Ta、Mo和 W中的至少一种，该沉积工艺可以是物理气相沉积。
步骤S802：如图14和图15所示，对有源柱3进行热处理，在有源柱3的顶部形成金属硅化物层5。该热处理可以是退火，使第一金属层51的金属与有源柱3反应，在有源柱3顶部掺杂有金属硅化物，如CoSix、NiSix或TiSix，进而形成金属硅化物层5。由于有源柱3的顶部为金属硅化物，因此有源柱3的顶部的电阻降低，使其与焊盘金属的接触电阻降低。其中，退火温度可以为400℃～1000℃，具体地，除了上述温度范围的两个端值外，退火温度还可以是500℃、600℃、700℃、800℃或900℃，或者退火温度在400℃～1000℃范围内变化，此处不做特殊限定。步骤S801和步骤S802为自对准硅化工艺(Salicide process)，其形成金属硅化物不需要使用光刻图案化工艺，使制备工艺简化。
步骤S803：如图15所示，去除剩余的第一金属层51。具体地，可以通过蚀刻工艺去除剩余的第一金属层51。该蚀刻工艺可以是湿法蚀刻或干法蚀刻，本领域技术人员可以根据实际情况进行选择，此处不做特殊限定。
在一些实施例中，如图16所示，本公开的半导体结构的制备方法还包括：在金属硅化物层5的顶面、栅极结构4的顶面以及隔离层6的顶面形成连接材料层71。
在一些实施例中，如图16所示，在步骤604中，由于在有源柱3的顶部的外围形成了凹槽G，连接材料层71的底部形成于该凹槽G中，因此，增加了连接材料层71的稳定性。
在一些实施例中，如图17所示，本公开实施例的半导体结构的制备方法还包括：去除部分连接材料层71，露出隔离层6，剩余的连接材料层71形成连接层7，该连接层7的顶面与隔离层6的顶面平齐。
具体地，利用化学机械研磨工艺去除部分连接材料层71，形成连接层7，使连接层7的顶面与隔离层6的顶面平齐。如此，能够将相邻的有源柱3上方的连接层7绝缘隔离，且使得半导体结构的表面平坦化，有利于存储单元的设置。
连接层7在衬底1上的投影覆盖金属硅化物层5在衬底1上的投影，使连接层7与金属硅化物层5充分接触。连接层7可以理解为金属焊盘，与金属硅化物层5电性连接，实现有源柱3与位于金属焊盘上方的存储单元(图中未示出)电性连接。该连接层7的材料是TiN、W、Al、Cu和Au中的至少一种。继续参考图17，凹槽G的底面高于金属硅化物层5的底面，避免连接层7与有源柱3部分接触，实现其完全与金属硅化物层5接触，减小接触电阻，同时增加了连接层7与金属硅化物层5的接触面积，提高半导体结构的运行速度。
在一些实施例中，在步骤S400之前，还可以包括步骤S300：形成位线2，位线2位于衬底1内，并沿第二方向F2间隔排布。如图1所示，第二方向F2与第一方向F1不平行，例如，第二方向F2与第一方向F1垂直。
在一些实施例中，形成位线2可以包括步骤S301至步骤S304。
步骤S301：沿第二方向F2，在有源柱3之间的衬底1中形成位线2。具体地，可以利用离子注入工艺，沿第二方向F2向位于有源柱3之间的衬底1中掺杂杂质离子，以形成位线2，也可以在位于有源柱3的下方的衬底1中掺杂上述杂质离子，形成位线2。
步骤S302：在位线2上形成第二金属层。具体地，可以利用沉积工艺在位线2上方形成一层金属层，如图4所示，第二金属层沉积于虚线椭圆所对应的区域的表面。该第二金属层可以是Co、Ni、Pt、Ti、Ta、Mo和W中的至少一种，该沉积工艺可以是物理气相沉积((Physical Vapor Deposition，PVD))。
步骤S303：对衬底1进行热处理，形成掺杂有金属硅化物的位线2。具体地，该热处理可以是退火，使第二金属层的金属与位线2的硅反应，形成掺杂有金属硅化物的位线2，该金属硅化物位于图4中示出的金属硅化物区域21内。由于位线2中具有金属硅化物，如CoSix、NiSix或TiSix，因此位线2的电阻降低。其中，退火温度可以为400℃～1000℃，具体地，除了上述温度范围的两个端值外，退火温度还可以是500℃、600℃、700℃、800℃或900℃，或者退火温度在400℃～1000℃范围内变化，此处不做特殊限定。步骤S402和步骤S403为自对准硅化工艺(Salicide process)，其形成金属硅化物不需要使用光刻图案化工艺，使制备工艺简化。
步骤S304：去除剩余的第二金属层。具体地，可以通过蚀刻工艺去除剩余的第二金属层。该蚀刻工艺可以是湿法蚀刻或干法蚀刻，本领域技术人员可以根据实际情况进行选择，此处不做特殊限定。
在一些实施例中，位线2中的金属硅化物与金属硅化物层5具有相同的金属元素，如此可以简化工艺，节省能耗。
综上，本公开实施例中的半导体结构的制备方法，通过在有源柱3的顶面形成金属硅化物层5，使有源柱3的顶部具有较小的电阻，因此，减小了本公开的有源柱3与金属焊盘的接触电阻，降低能耗，提高了半导体结构的运行速度。
根据本公开的另一方面，提供一种半导体装置，包括上述任一实施例所述的半导体结构以及存储单元，该存储单元通过连接层7与半导体结构电连接。半导体结构以及连接层7同上述实施例，此处不再赘述。
本公开实施例的半导体装置，由于半导体结构中的有源柱3上具有金属硅化物层5，具有较小的接触电阻，能够提高半导体装置的运行速度，减少能耗。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (19)

  1. 一种半导体结构，包括：
    衬底；
    有源柱，位于所述衬底上并且阵列排布，所述有源柱沿垂直于所述衬底的方向延伸；
    栅极结构，位于所述衬底上，沿第一方向间隔排布，并环绕设于所述有源柱的一部分；
    金属硅化物层，位于所述有源柱的顶面上，且所述金属硅化物层在所述衬底上的投影和所述有源柱的顶面在所述衬底上的投影重合；
    隔离层，位于相邻的所述栅极结构以及相邻的所述有源柱之间，所述隔离层的高度高于所述金属硅化物层的顶面的高度。
  2. 根据权利要求1所述的半导体结构，其中，所述金属硅化物层中的金属元素包括Co、Ni、Pt、Ti、Ta、Mo和W中的至少一种。
  3. 根据权利要求1所述的半导体结构，其中，所述栅极结构包括：
    栅绝缘层，所述栅绝缘层环绕设于所述有源柱的侧面，在垂直于所述衬底的方向上，所述栅绝缘层的顶面低于所述金属硅化物层的顶面；
    字线层，环绕设于所述栅绝缘层侧面的一部分。
  4. 根据权利要求3所述的半导体结构，其中，所述栅绝缘层的顶面低于所述金属硅化物层的顶面的距离为5～40nm。
  5. 根据权利要求1所述的半导体结构，还包括：
    连接层，位于所述金属硅化物层上，且所述连接层在所述衬底上的投影覆盖所述金属硅化物层在所述衬底上的投影。
  6. 根据权利要求5所述的半导体结构，其中，所述隔离层沿垂直于所述衬底的方向延伸，且所述隔离层的顶面与所述连接层的顶面平齐。
  7. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底上具有阵列排布的有源柱，所述有源柱沿垂直于所述衬底的方向延伸；
    形成栅极结构，位于所述衬底上，沿第一方向间隔排布，并环绕设于所述有源柱的一部分；
    形成隔离层，所述隔离层形成于相邻的所述栅极结构以及相邻的所述有源柱之间，所述隔离层的高度高于所述有源柱的顶面的高度；
    形成金属硅化物层，位于所述有源柱的顶面上，且所述金属硅化物层在所述衬底上的投影和所述有源柱的顶面在所述衬底的投影重合。
  8. 根据权利要求7所述的方法，其中，形成栅极结构包括：
    在所述有源柱的表面形成栅绝缘层；
    在所述栅绝缘层的侧面的一部分环绕形成字线层。
  9. 根据权利要求8所述的方法，其中，在所述有源柱的表面形成栅绝缘层包括：
    在所述有源柱的表面形成第一绝缘层；
    在所述第一绝缘层之间填充第一隔离层；
    回蚀刻所述第一绝缘层至第一预设深度，露出所述有源柱的第一部分；
    蚀刻所述第一部分的侧壁，形成第一柱体；
    在所述第一柱体的表面形成第二绝缘层，所述第二绝缘层和所述第一绝缘层形成所述栅绝缘层。
  10. 根据权利要求9所述的方法，其中，在所述栅绝缘层的侧面的一部分环绕形成字线层包括：
    在相邻的所述第二绝缘层之间填充字线金属层；
    回蚀刻所述字线金属层至第二预设深度，形成字线层。
  11. 根据权利要求10所述的方法，其中，形成隔离层包括：
    在相邻的所述栅绝缘层之间，且在所述字线层上形成第二隔离层；所述第一隔离层和所述第二隔离层形成所述隔离层。
  12. 根据权利要求11所述的方法，其中，在形成所述第二隔离层后，利用化学机械研磨工艺使所述第一隔离层、所述第二隔离层和所述第二绝缘层的顶面平齐。
  13. 根据权利要求12所述的方法，其中，还包括：去除所述第一柱体的顶面的所述第二绝缘层，露出所述第一柱体的顶面。
  14. 根据权利要求13所述的方法，其中，去除所述第一柱体的顶面的所述第二绝缘层包括：
    回蚀刻所述第二绝缘层，去除所述第一柱体的顶面的所述第二绝缘层，并将位于所述第一柱体侧面的所述第二绝缘层回蚀刻至第三预设深度。
  15. 根据权利要求14所述的方法，其中，所述第三预设深度为5～40nm。
  16. 根据权利要求13所述的方法，其中，去除所述第一柱体的顶面的所述第二绝缘层包括：仅蚀刻去除位于所述第一柱体顶面的所述第二绝缘层。
  17. 根据权利要求7至16中任一项所述的方法，其中，所述形成金属硅化物层包括：
    在所述有源柱的顶面形成第一金属层；
    对所述有源柱进行热处理，在所述有源柱的顶部形成金属硅化物层；
    去除剩余的所述第一金属层。
  18. 根据权利要求7所述的方法，还包括：
    在所述金属硅化物层的顶面、所述栅极结构的顶面以及所述隔离层的顶面形成连接材料层；
    去除部分所述连接材料层，露出所述隔离层，剩余的所述连接材料层形成连接层，所述连接层的顶面与所述隔离层的顶面平齐。
  19. 一种半导体装置，包括：
    如权利要求1至6中任一项所述的半导体结构；
    存储单元，通过一连接层与所述半导体结构电连接。
PCT/CN2022/098253 2022-04-26 2022-06-10 半导体器件的制备方法及半导体器件 WO2023206743A1 (zh)

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CN101897008A (zh) * 2007-12-12 2010-11-24 日本优尼山帝斯电子株式会社 半导体器件
CN102779828A (zh) * 2011-05-12 2012-11-14 海力士半导体有限公司 半导体存储器件
US20130234240A1 (en) * 2012-03-12 2013-09-12 Korea Advanced Institute Of Science And Technology Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
CN103904115A (zh) * 2012-12-24 2014-07-02 爱思开海力士有限公司 具有埋设的金属硅化物层的半导体器件及其制造方法
CN109216278A (zh) * 2017-07-03 2019-01-15 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN114141712A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

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CN101897008A (zh) * 2007-12-12 2010-11-24 日本优尼山帝斯电子株式会社 半导体器件
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US20130234240A1 (en) * 2012-03-12 2013-09-12 Korea Advanced Institute Of Science And Technology Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
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