TW201203368A - Thin film formation method - Google Patents

Thin film formation method Download PDF

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Publication number
TW201203368A
TW201203368A TW100108843A TW100108843A TW201203368A TW 201203368 A TW201203368 A TW 201203368A TW 100108843 A TW100108843 A TW 100108843A TW 100108843 A TW100108843 A TW 100108843A TW 201203368 A TW201203368 A TW 201203368A
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TW
Taiwan
Prior art keywords
forming
film
metal film
landfill
layer
Prior art date
Application number
TW100108843A
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English (en)
Inventor
Tadahiro Ishizaka
Jonathan Rullan
Osamu Yokoyama
Atsushi Gomi
Chiaki Yasumuro
Takara Kato
Tatsuo Hatano
Hiroaki Kawasaki
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Tokyo Electron Ltd
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Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201203368A publication Critical patent/TW201203368A/zh

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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C23C14/025—Metallic sublayers
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
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  • Chemical Kinetics & Catalysis (AREA)
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  • Metallurgy (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thermal Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

201203368
【發明所屬之技術領域】 本务明係關於一種薄膜之形成方法，用以填埋在半 導體晶圓等處理體所形成之凹部。 、 【先前技術】 般’於製造半導體元件時，係於半導體晶圓反覆 地進行成膜處理、圖案蝕刻處理等备種處理來製造所希 元件’但伴隨半導體元件之進〆爹的高集積化以及 高微細化之需求，線寬、孔#日益微細化。再者，作為 配、、泉材料、填埋材料以往主要係使用鋁合金，然最近線 寬、孔徑日益微細化，且希望作動速度之高速化，故傾 向於也使用鎢（w)、銅（Cu)等。 此7卜’將上述A1、W、 ---- ” 寻资 /到 nI ^ τρ 料或是接觸用孔之填埋材料來使用之情況，基於防止例 如於矽氧化膜（Si〇2)等絕緣材料與上述金屬材料之間 產生例如矽擴散、或是提高膜密接性之目的，或者是提 升於孔底部所接觸之下層電極、配線層等導電層之間的 密接性等之目的，係於上述絕緣層、下層導電層之門' 交界部分介設轉層。此外，上述阻障層已廣為人2 有Ta膜、TaN膜、Ti膜、TiN膜等（專利文獻丨〜4 )考 此外最近，基於提升和填埋金屬之密接性的目。 而於上述阻障層之上層設置薄的襯褢層。 、， 述般係基於提升與填埋金狀密紐 ’ ^ D上 使用和填埋金屬層之晶格間隔接近之材料，例如當 201203368 金屬為銅之情況，在襯裏層之材料方面主要以使用Ru (釕）受到矚目（例如專利文獻5)。 於上述專利文獻5，具體而言，係記載了於包含有 被稱為雙金屬鑲嵌(Dual Damascene)構造之開口部的部 分形成例如由TaN所構成之阻障膜之後，以cvd (Chemical Vapor Deposition)形成 Ru 膜作為襯裏層， 之後再填埋Cu。 胃 習知技術文獻 專利文獻1日本特開2〇〇3_ 142425號公報 專利文獻2日本特開2006— 148074號公報 專利文獻3日本特開2004—335998號公報 專利文獻4日本特開2006—303062號公報 【發日本特開2007 一 _4號公報 之二：吏:寬由一 ^ 為填埋金狀=朝向微細化’仍可謀求和作 在使用由RU_ 性:_CU之填埋特性的改善，但 用Ta膜作為襯裏層，襯義層之情況，相較於例如使 之新的問題。 月况，會發生電子轉移耐性降低 基於提升電子轉 中係記載了於形成谊之規點於上返專利文獻3 來去除填埋部以外、，用銅膜之後藉由化學機械研磨 此銅金屬配線切埋f餘的峨而形成銅金屬配線，於 擇性地鈦、釕讀進行退火處理 4 201203368 了退火處理，旬2獻3所不成膜方法’即使進行 法充:，=:;:粒徑仍相對小，而有無 埋之r外=專利文獻4係揭示了將凹部以鋼導電膜填 禮m薄絲多餘的導f膜而直接形錢、釕等所 η與’進而進行熱處理。但是，此專利文獻私 膜電膜中之結晶缺陷朝上述導電膜與被覆 ==軸“料叫除，並非以提升電子轉二 本發明係提供一種薄膜之形成方法， =;和填埋金屬之密接性以及填埋特性之改盖不：在 楗升電子轉移耐性。 。，亦可 ，發明者等為了達成上述目的經過努力研 果务現藉由在填埋用金屬膜上 九之結 金屬犋之全屬材料成有間隔與此 、之金屬材枓接近的金屬膜之狀態下匕 ::高效率地進行填埋用金屬膜中之結晶的成= 升電子轉移雜，從而完成了本發明。战長而提 依據本發明係提供一種薄膜之形成方法，係對 具有凹部之被處理體表面形成薄犋以填埋凹部；、具 '"面 述製裡：於包含該凹部之該被處理體表面形成填下 屬膜來填埋該凹部之製程；以被覆該金屬膜之方式在金 被處理體表面之全面形成擴散防止用金屬膜之製"程.°亥 及對形成有該擴散防止用金屬膜之該被處理體，以 火之製程。 仃退 5 201203368 【實施方式】 以下參照所附圖式，針對本發明之實施形態做詳細 說明。此處所說明之例子係使用銅（Cu)作為填埋用金 屬膜，使用釕（RU)作為襯裏層。 圖1係顯示本發明之一實施形態之薄膜之形成方 法之各製程中被處理體之半導體晶圓狀態之製程截面 圖’圖2係顯示本發明之一實施形態之薄膜之形成方法 之流程圖。 此處作為被處理體係如圖1 (A)所示般，係準備 半導體晶圓（於矽基板表面依序形成絕緣層1、2，於絕 緣層2中形成作為配線層等之導電層4,以被覆此導電 層4之方式於絕緣層2表面全體使得例如Si02膜等所 構成之絕緣層6以既定厚度形成，並於絕緣層形成有配 線用以及/或是接觸用凹部8)，一開始對此半導體晶圓 進行脫氣處理（S1)。在此脫氣處理，係吹走附著於半 導體晶圓表面之水分、有機物等來加以去除。 半導體晶圓之導電層4有時係對應於電晶體、電容 器之電極等。此外位於絕緣層2與絕緣層6之界面的阻 钱層、被覆導電層4之側面或底面之阻障層等係省略圖 7J> 〇 凹部8係由用以對導電層4謀求電氣接觸之接觸用 貫通孔或通孔、以及/或是配線用溝渠（溝槽）所構成。 此處顯示了於細長溝渠之底部形成了接觸用通孔之戴 面為2段構造之所謂的雙金屬鑲叙(Dual Damascene)構 S: 201203368 造。此構造係於通孔底部使得下層導電層4露出，取得 形成於溝渠之配線與下層之導電層4間的接觸。 於此種構造之半導體晶圓，表面之凹部8以外表面 之部分稱為場域(field)部9。亦即，此場域部9於此處 係指形成於絕緣層6之凹部8以外之上面的平坦部侧。 進行脫氣處理之後，如圖i (B)所示般，於包含 此凹部8内之底面以及側面的半導體晶圓表面全體、亦 即絕緣層6上面全體以所希望之厚度來形成阻障層1〇 (S2) $成阻障層1Q之目的在於防止發從絕緣層6 朝填埋金屬進行擴散、或是提升填埋金屬與絕緣層6以 及導電層4之間的密接性。 阻障層10可適用各種之物。例如依序積層Ti膜以 及TiN膜所得之2層構造的阻障層；依序積層膜 以及Ta膜所得之2層構造的阻障層；再者，也存在有 僅使用Ti膜、TiN膜、Ta膜以及TaN膜當中j層之阻 障層。+此外，亦可使用W膜之1層構造、或是w膜與 WN膜之2層構造之阻障層。不論為何者，阻障層 之材質以及構造係由形成於此阻障層1〇上層之作為導 電層的觀裏層之種類來決定。此阻障層1G之厚度為例 如1〜20nm程度。 寞屏11如圖1 (C)所示般，於阻障層1〇上形成襯 表:(S3)。此襯裏層12係於後續製程所進行之 以提升與作為填埋金屬使用之^的密接性以 一里特性者。於本實施形態中，襯裏層12如上述般 201203368 係使用Ru，除此以外亦可使用c〇 (始）、(组）等。 其中’基於提升密接性以及填埋特性之觀點以使用Ru 為佳。作為襯裏層12使用之⑹膜在原料方面可使用例 如Ru3 (CO) u，藉由CVD法來適宜地形成。為了形 成此膜，可使用例如日本特開2010—037631號公報 所揭不之CVD成膜裝置。此襯裏層12之厚度為例如i 〜1 Onm程度。 其次，如圖1 (〇)所示般，於上述襯裏層12上形 成種晶層14 (S4)。此種晶層14係用以提高之後所進 行之填埋製程的效率。此種晶層14基本上係以與填埋 金屬為相同材料所形成，此處係使用Cu。此種晶層14 月匕以例如 PVD ( Physical Vapor Deposition )法、典型上 以藏鑛法來形成。此種晶層14之厚度為例如2〜1〇〇ηιη 程度。此外，亦可省略此種晶層14。 其次’如圖1 (E)所示般，進行將凹部8内以填 埋金屬來填埋之填埋製程以形成填埋用金屬膜16 (S5)。藉此，藉由填埋用金屬膜16將上述凹部8内 完全填埋。作為形成此填埋用金屬膜16之填埋金屬係 如上述般使用Cu。此填埋製程主要可使用鍍敷法，除 此之外亦可使用CVD法、使得原料氣體與反應氣體交 互反覆流動來形成一層層薄膜之ALD (Atomic Layerd Deposition)法、PVD法（亦即濺鍍法）。 於此種情況下，較佳為晶圓W表面之凹部8以外 表面的場域部9之上述填埋用金屬膜16的厚度a·成為
201203368
St冰度b以上厚度的方式來厚厚地形成填埋用金 進行填埋用金屬膜16之成膜直到 ^里/^Γ ’如後祕可增^㈣賴進行之退火 ^理日该長之構成填埋用金屬膜16的〜之結晶粒的粒 往0 制rt、，如圖丨（F)所示般，進行擴散防止膜形成 认㈤）’以被覆填埋用金屬膜w 在，曰圓表面之全面形成本發明方法 擴政防止用金屬膜18。作為此擴散防止用金屬膜i8係 使用曰日格間隔與上述填埋用金屬膜16之金屬材料接、斤、 之金屬材料。此處，由於填埋用金屬膜16係使用Cu” 故作為晶_隔與銅最接近之金屬材料 m方法係和圖i(c)所說明之 之襯晨層12之形成方法相同。 藉由事先形成此種擴㈣止用金屬膜18 私所進行之退火處理時，因抑制在填埋用金屬膜16 ^ 素擴散’可將原本因擴散所會消耗之移^ ==成長。其結果’可高效率地進行晶粒(結 曰日祖）之成長而可促進此成長。 〇5n:rfr下’上述擴散防止用金屬膜18之厚度以 . 上為佳。若薄於0.5nm，無法於填埋用金屬膜 16上面均勻地形成此金屬膜18，成、 恐無法高效率地発揮上述作用。此外;== = 1 〇 右上述擴散防止 屬膜18之厚度過厚’由於在後述之去除製程需要 201203368 許多時間故生產性會降低^從而，其膜厚以5Qnm程度 以下為佳。 其次，如圖1 (G)所示般，將形成有上述擴散防 止用金屬膜18之半導體晶圆曝曬於高溫狀態下進行退 火處理，使得各金屬元素之結晶構造安定化（S7)。此 退火溫度以在100〜50()¾之範圍内為佳，更佳為15〇〜 400 C之範圍内，特佳為2〇〇〜35〇。〇之範圍内。當此退 火溫度低於100¾之情況，無法充份發揮退火效^，此 外’若過尚於500°C，會發生元素上吸現象非所喜好者。 如此般’藉由於Cu所構成之填埋用金屬臈16表面 事先形成由Ru所構成之擴散防止用金屬膜18，由於該 等晶格間隔非常近似而密接性變高，故於製程s7之退 火處理進行之時，可抑制於Cu表面之Cu元素的熱擴 散。其結果，原本應消耗於此熱擴散之能量適於結晶成 長而可高效率地進行結晶粒（亦即晶粒）之成長，^促進 此成長。其結果，由於傾向於產生電子轉移之纟士 a 此之界面的長度或是面積變少，對應於此，可抑制電子 轉移之發生。 其次，如圖1 (H)所示般，進行去除製程（S8)， 將半導體晶圓表面上多餘的薄膜刮除而去除之。此去除 製程係將存在於凹部8之外側、半導體晶圓表面之不要 的薄膜以例如 CMP ( Chemical Mechanica丨 ) 處理來去除。藉此，完成凹部之填埋處理。 如此般，在本實施形態，由於在表面具有凹部8之 201203368 作為被處理體的半導體晶圓表面形成填埋用金屬膜16 並進行凹部之填埋，以被覆金屬膜16的方式於作為被 處理體之半導體晶圓表面之全面形成擴散防止用金屬 膜18,之後對作為被處理體之該半導體晶圓進行退火， 故不僅可謀求填埋金屬之密接性以及填埋特性的改 善，亦可提升電子轉移财性。 <本發明方法之評價> 其次，針對上述本發明之薄膜之形成方法就進行實 驗之際的評價結果來說明。首先，在說明擴散防止用金 屬膜18之作用之前先針對襯裏層12之作用來說明。此 概裏層12如前述般，主要係用來改善和作為填埋用金 屬膜16之銅的密接性。如此般，為了改善密接性，使 用與銅之晶格間隔儘量近似之材料作為襯裏層12乃為 所喜好者。圖3係顯示以銅為中心之各金屬之結晶構造 狀態之圖，圖4A、圖4B係顯示依存於襯裏層而積層 Cu層時之面間隔狀態之示意圖。 圖3係顯示Cu、Ru、Ta、Ti之各元素之緊密堆積 平面的結晶構造、晶格爹數、晶格間隔（面間隔以及對 Cu之位偏量）。尤其在晶格間隔方面，若著眼於面間 隔以及對Cu之面間隔位偏量，則Ru對Cu ( 111)面之 面間隔最近。此外，上述Ta、Ti之晶格位偏量分別為 11.9%、9.77%，相對於此，Ru之晶格位偏量僅為2.57 %，位偏量最少。 從而，可知若將Ru金屬作為襯裏層12來使用，可 201203368 提升與Cu膜之密接性，並可提升凹部之填埋特性。圖 4A、圖4B係顯示Cll之晶格位偏’圖4A係襯裏層使用 Ta或是Ti者，圖4B係襯裏層使用RU者。 如圖4A所示般’當作為底層之襯襄層使用面間隔 位偏量大之Ta、Ti之情況，於其上所積層之Cu膜的晶 格間隔L1會較原來之晶格間隔產生大幅位偏，而於該 處產生應變使得兩者間之密接性變差。 相對於此，如圖4B所示般，當作為底層之襯裏層 係使用面間隔位偏量小之Ru之情況，於其上所積層之 Cu膜的晶格間隔L2會變得與原本之晶格間隔接近，其 結果’可大幅提升兩者間之密接性。 但是’若比較Cu膜之結晶尺寸，由於在Cu/Ru 界面具有良好之密接性，故即使進行退火處理，會成為 Cu結晶難以成長之狀態。其結果，RU膜上之Cu膜的 f晶尺寸相較於Ta膜、Ti膜上之C項的結晶尺寸來 知小。例如，於厚度為4nm之丁aN以及厚度2nm之Ta 膜的積層構造上形成Cu膜並進行退火處理時之Cu (111)面的結晶尺寸為15nm。相對於此於膜之 積層構造上形成Cu膜並進行退火處理時之Cu (111) 处 子轉移傾向於在Cu膜中士曰 界面以晶界擴散之形彳'、、〇日日（日日拉） 夕^ Μ丨 切生。從而，若如上述般Cu膜 、口曰曰、則相對地Cu結晶彼此之界面長度或是 201203368 面積會增加而容易產生晶界擴散，電子轉移财性會惡 化。進而’若Cu膜之結晶尺寸小，則若於之後之程序 t Ίχ生Cu結晶之成長’於此時在Cu膜中恐會發生空 孔(void)。 是以’本發明係如上述般’在作為填埋用金屬膜 16之Cu膜上形成擴散防止用金屬膜18，一邊抑制Cu 膜表面之擴散一邊促進結晶成長。為了確認上述擴散防 止用金屬膜18之作用，如圖5A、圖5B所示般準備了 形成有擴散防止用金屬膜之半導體晶圓與未形成擴散 防止用金屬膜之半導體晶圓，針對Cu結晶之成長進行 了確認。 圖5A、圖58係顯示進行確認擴散防止用金屬膜作 用之實驗時之薄膜積層構造之截面圖，圖5A係顯示於 真里用i屬層16上未形成擴散防止用金屬膜a之試 =圖則顯示於填埋用金屬層16上形成有擴散防: 用金屬膜18之試樣。 上對應於習知方法，时基板之半導體晶圓 上依序積層者由Si〇2所構成之絕緣層6、由Ti 成之阻障層10、*Ru膜所構成之襯裏層12以及相各 於填埋用金屬膜16之Cu膜20。 相對於此’圖5B係對應於本發明方法， 上依序積層著由si〇2m構成之絕緣層6、由了 : 膜所構成之襯裏層12、相當於填 埋用金屬膜16之Cu膣？D W β rh 15糾 膜20以及由Ru膜所構成之擴散 13 201203368 防止用金屬膜18。 對於圖5A以及圖5B所示形成有各種薄膜之各試 樣’分別以15〇°C之溫度施行30分鐘之退火處理。然 後，分別測定各Cu膜20中之Cu結晶的大小。其結果， 在圖5A所示對應於習知方法之情況下，Cu膜20中之 Cu結晶的平均值為58nm程度。相對於此，圖5B所示 對應於本發明方法之情況下，Cu膜20中之Cu結晶之 平均值為122nm程度，可確認cu結晶成長至約2倍之 大小。 圖6A以及圖6B係示意顯示圖5B之對應於本發明 之試樣的Cu膜20中之Cu結晶狀態，圖6A係退火處 理如者，圖6B係退火處理後者。於退火處理前，如圖 6A所示般，Cu膜20中有許多Cu結晶尺寸相當小之部 分，但於退火處理後，如圖6B所示般Cu結晶會成長 而變大。 #仲田次俱埋用金屬膜16之Cu膜20表 =形成有擴散防止用金屬膜18之狀態下進行退火處 〜稭此可促進結晶成長之理由可思考如下。亦即，通 ^動表面之能量最高，故表面的原子非常容易 為易於熱擴散之狀態。但是，若於此Cu膜表 : = = _隔位偏量相對於&為少之&膜，兩 地結合而抑制熱擴散。其結果，原本應 如上述般成為於Uli 結晶之成長上，而 成為於Cu膜成I Cu結晶。因此，依據本發 201203368 明，不僅可謀求填埋金屬之密接性以及填埋特性之改 善’亦可提升Cu晶界擴散之電子轉移耐性。 此外，如前述般形成上述填埋用金屬膜16之際， 若將場域部9中填埋用金屬膜16之厚度a設定為相當 厚，將此厚度a設定為凹部8之深度b以上（a^b)之 厚度’則於退火處理時可使得填埋用金屬膜16之銅結 晶粒更為大幅成長。亦即，由於從銅犋上側部分朝向下 方發生Cu結晶粒之成長，故若於場域部9上存在大量 之膜厚夠厚之銅膜而達成上述“agb”，相對地，可促進 =晶粒之成長讓充分大之結晶粒成長至銅膜之下側部 分為止。從而，可知為讓直到沉積於凹部8内底部側之 Cu膜（金屬膜16)為止可成長充分大的結晶粒，如上 ^將場域部9之填埋用金屬膜16之厚度,設定為凹 4 8之沬度b以上之厚度為佳。 腺的ί上述般，愈為增厚作為填埋用金屬膜16之Cu 胰的厚度，則退火處理時此c膜 a 為增大。圖7說明了㈣^ Ba拉的粒徑可愈 粒之師相㈣「 退火溫度與Cu結晶 ^相對於Cu膜厚之關係圖。此處 :::為膜(4賊〜= 為擴散防止用金屬其=形成作 行了退火處理（動·】πτ膜“作賴#此試樣進 樣方面係製作了 c4.j ΓΓ，30分鐘）。此外，在試 種類，對1進行口二厚度為3〇nm者與5〇_者之2 丁了退火處理。此外，結晶粒之教徑係使 201203368 用XRD (螢光χ射線分析器）來測定。 從此圖表可明顯得知’當填埋用金屬膜之Cu膜的 厚度從30nm增厚為50nm，雖亦取決於退火溫度，惟 Cu結晶粒之粒徑大小係從13〜ι6ηπι放大至18〜 19nm。亦即，可知Cu膜之厚度愈厚，可愈為增大其結 晶粒之粒徑。 此汗’便用上述之成膜方法，於深度（㈧為 132nm、 寬度為80nm之溝槽狀溝渠部所構成之凹部8内填埋cu 膜，將此時之場域部的銅膜厚度（a)設定為34〇nm之 時，針對退火處理後之Cu結晶粒之粒徑利用穿透型電 子』如i鏡（Transmission Electron Microscope :TEM) 來測定。其結果如圖8所示。圖8係顯示對凹部之溝槽 狀溝渠部内填埋C u膜而以相當於溝渠部中央之部分作 切斷時之截面的穿透型電子顯微鏡照片。此處，如圖9 所示般，係顯示了將溝渠部中央朝縱向切斷時之截面。 從5亥圖8所付Cu結晶粒之平均粒徑大小為％細程度， 得到較溝渠寬度之8Gnm為大之粒徑。 在此種If况下，Cu結晶粒之粒徑大小以設定為溝 渠。T凹。p 8之寬度以上（亦即、& 佳κ際以將粒徑大小設定為凹部8之寬度（開口寬度） 〜2:程度之範圍内的大小為佳。此外在現狀之半 導體積體電路，凹部之寬度（亦即溝渠寬度）為1〇〜 200nm权度。此外作為凹部之溝渠部之深度為〜 η"程度’溝渠寬度與作為凹部之溝渠部深度之比、 201203368 亦即高寬比AR為“2〜10”程度。 從/此外’本實施形態不限定於上述實施形態可做各種 交形。例如’在上述實施形態，係舉岐用Cu作為填 里用至屬膜16之情況為例來說明，惟不限定於此，亦 =用轉（W)、铭㈤。亦即，在金屬膜16方面 σ使用選自Cu、W、以及A1所組成群中}者的材料。 此外於上述實施形態，係舉出使用釕（R 散防止用金屬膜18之情況為例來說明，惟不限定^ =只要可將填埋用金屬膜16從上叫制，不論=種 =皆可抑制位於表面之it素的擴散，作為擴散防止用 孟屬膜18之其他元素可適用Co、Ta以及Ti。亦即， 在擴散防止用金屬膜方面可適用選自Ru、c〇、Ta以及 Ti所組成群中1者之材料。 再者，於上述實施形態在被處理體方面係以半導體 晶圓為例來說明，惟此半導體晶圓尚包括秒基板以及 GaAs、SiC、GaN等化合物半導體基板，且不限定於該 等基板’本發明亦可適用於液晶表示裝置所使用之玻璃 基板、陶瓷基板等。 【圖式簡單說明】 圖1(A)〜(H)係顯示本發明之一實施形態之薄膜之 形成方法之各製程中被處理體之半導體晶^狀態的製 程截面圖。 圖2係顯示本發明之一實施形態之薄膜之形成方 法的流程圖。 17 201203368 圖3係顯不以銅為中心之各金屬之結晶構造狀悲 之圖。 圖4A係顯示襯裏層使用Ta或是Ti，於其上積層 著Cu層時之Cu的晶格位偏之示意圖。 圖4B係顯示襯裏層使用Ru，於其上積層著Cu層 時之Cu的晶格位偏之示意圖。 圖5A係顯示於確認擴散防止用金屬膜之作用的實 驗中所使用，於填埋用金屬層上未形成擴散防止用金屬 膜之薄膜積層構造之截面圖。 圖5B係顯示於確認擴散防止用金屬膜之作用的實 驗中所使用，於填埋用金屬層上形成有擴散防止用金屬 膜之薄膜積層構造之截面圖。 圖6A係示意顯示於形成擴散防止用金屬膜後、退 火處理前之Cu之結晶狀態圖。 圖6B係示意顯示於形成擴散防止用金屬膜後、退 火處理後之Cu之結晶狀態圖。 圖7係顯示退火溫度與Cu結晶粒之粒徑相對於Cu 膜厚之關係圖。 圖8係顯示對凹部之溝槽狀溝渠部内填埋Cu膜， 以相當於溝渠部中央之部分切斷時之截面的穿透型電 子顯微鏡照片。 圖9係用以說明試樣之切斷位置之示意圖。 18 201203368 【主要元件符號說明】 1,2,6 絕緣層 4 導電層 8 接觸用凹部 9 場域部 10 阻障層 12 襯裏層 14 種晶層 16 填埋用金屬膜 18 擴散防止用金屬膜 20 Cu膜 19

Claims (1)

  1. 201203368 七、申請專利範圍： = ί形成方法’係對表面具有凹部之被處理 粗表面形成薄膜以填埋凹部；具有下述製程： 於包含該凹部之該被處理體表面形成填埋 孟屬臈來填埋該凹部之製程； ’、 人以被覆該金屬膜之方式在該被處理體表面之 王面形成擴散防止用金屬臈之製程，·以及 ，形成有賴散防止用金屬膜之該被處理體 進仃退火之製程。 二申請專利範圍第！項之薄膜之形成方法，其中於 =該填埋用金屬膜來填埋該凹部之際，該被處理 腊外表面的場域部之該填埋用金屬 膜的厚度為該凹部之深度以上。 =申請專利範圍第i項之薄膜之形成方法，其中在 火製辁，该填埋用金屬膜之結晶粒的粒徑係成 為該凹部之寬度以上的大小。 :申請專利範圍第1項之薄膜之形成方法，其進一 知八有作為形成该填埋用金屬膜來填埋該凹部之 4程的前製程、亦即形成阻障層之製程。 =申請專利範圍第4項之薄膜之形成方法，其進一 =具有：在形成該阻障層之製程與形成該金屬膜來 =埋《^凹之製程之間所進行之形成種晶層之製 程0 如申請專利範圍第1項之薄膜之形成方法，其進一 2. 3. 4. 5. 6. 201203368
    8.9. =具有.作為形成該填埋用金屬膜來填埋該凹部之 製程的前製程亦即形成阻障層之製程、以及 障層上形成襯裏層之製程。 / ^申睛專利範圍第6項之薄膜之形成方法，其進一 步具有：在形成該襯裏層之製程與形成該填埋用金 屬膜來填岭凹狀製程之間所進行之形成種晶 層之製程。 0曰 如申請專利範圍第1項之薄膜之形成方法，其中該 退火製程係在100〜500。〇之範圍内的溫度來進行。 如申請專利範圍第1項之薄膜之形成方法，其進一 步具有：在形成該擴散防止用金屬膜之後，將該擴 散防止用金屬膜與該凹部以外之多餘的該填埋用 金屬膜予以去除之製程。 、 10. 11. 12. 如申請專利範圍第丨項之薄膜之形成方法，其中該 填埋用金屬膜係由選自銅、鎢以及鋁所組成群中1 者之材料所構成。 如申請專利範圍第1項之薄膜之形成方法，其中該 擴散防止用金屬膜係由選自Ru、C〇、Ta以及Ti 所組成群中1者之材料所構成。 如申請專利範圍第1項之薄膜之形成方法，其中該 填埋用金屬膜係以選自CVD ( Chemical Vapor Deposition)法、ALD( Atomic Layered Deposition) 法、PVD (Physical Vapor Deposition)法以及鐘敷 法所組成群中1者之方法所形成。 21 201203368 13. 如申請專利範圍第1項之薄膜之形成方法，其中該 擴散防止用金屬膜係以選自CVD ( Chemical Vapor Deposition)法、ALD ( Atomic Layered Deposition) 法、PVD (Physical Vapor Deposition)法以及鐘敷 法所組成群中1者之方法所形成。 14. 如申《月專利|&圍第i項之薄骐之形成方法，其中該 擴散防止用金屬膜之厚度為〇.5nm〜5〇nm。
    22
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