TW201130103A - Semiconductor memory devices and semiconductor packages - Google Patents
Semiconductor memory devices and semiconductor packagesInfo
- Publication number
- TW201130103A TW201130103A TW100101125A TW100101125A TW201130103A TW 201130103 A TW201130103 A TW 201130103A TW 100101125 A TW100101125 A TW 100101125A TW 100101125 A TW100101125 A TW 100101125A TW 201130103 A TW201130103 A TW 201130103A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor
- input
- pad part
- memory devices
- bump pad
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 7
- 238000003491 array Methods 0.000 abstract 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/091—Disposition
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/17181—On opposite sides of the body
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US30277310P | 2010-02-09 | 2010-02-09 | |
KR1020100018362A KR20110099384A (ko) | 2010-03-02 | 2010-03-02 | 와이드 입출력 반도체 메모리 장치 및 이를 포함하는 반도체 패키지 |
US12/891,141 US8796863B2 (en) | 2010-02-09 | 2010-09-27 | Semiconductor memory devices and semiconductor packages |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201130103A true TW201130103A (en) | 2011-09-01 |
Family
ID=44316781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100101125A TW201130103A (en) | 2010-02-09 | 2011-01-12 | Semiconductor memory devices and semiconductor packages |
Country Status (4)
Country | Link |
---|---|
US (2) | US8796863B2 (zh) |
JP (1) | JP2011166147A (zh) |
DE (1) | DE102010061616A1 (zh) |
TW (1) | TW201130103A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103681591A (zh) * | 2012-09-14 | 2014-03-26 | 瑞萨电子株式会社 | 半导体器件 |
TWI641109B (zh) * | 2016-09-23 | 2018-11-11 | 日商東芝記憶體股份有限公司 | Memory device |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5627197B2 (ja) | 2009-05-26 | 2014-11-19 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ |
JP2011112411A (ja) | 2009-11-25 | 2011-06-09 | Elpida Memory Inc | 半導体装置 |
KR20120056018A (ko) * | 2010-11-24 | 2012-06-01 | 삼성전자주식회사 | 범프들과 테스트 패드들이 십자 모양으로 배열되는 반도체 장치 |
US9490003B2 (en) * | 2011-03-31 | 2016-11-08 | Intel Corporation | Induced thermal gradients |
US9658678B2 (en) | 2011-03-31 | 2017-05-23 | Intel Corporation | Induced thermal gradients |
JP5864957B2 (ja) * | 2011-08-31 | 2016-02-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN104115227B (zh) | 2011-12-23 | 2017-02-15 | 英特尔公司 | 使用系统热传感器数据的存储器操作 |
KR101896665B1 (ko) * | 2012-01-11 | 2018-09-07 | 삼성전자주식회사 | 반도체 패키지 |
US9117496B2 (en) | 2012-01-30 | 2015-08-25 | Rambus Inc. | Memory device comprising programmable command-and-address and/or data interfaces |
JP2013196740A (ja) * | 2012-03-22 | 2013-09-30 | Toshiba Corp | 半導体記憶装置およびその駆動方法 |
JP2013211292A (ja) * | 2012-03-30 | 2013-10-10 | Elpida Memory Inc | 半導体装置 |
US8987787B2 (en) * | 2012-04-10 | 2015-03-24 | Macronix International Co., Ltd. | Semiconductor structure and method for manufacturing the same |
JP6058336B2 (ja) * | 2012-09-28 | 2017-01-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5439567B1 (ja) * | 2012-10-11 | 2014-03-12 | 株式会社東芝 | 半導体装置 |
KR102048255B1 (ko) * | 2012-10-25 | 2019-11-25 | 삼성전자주식회사 | 비트 라인 감지 증폭기 및 이를 포함하는 반도체 메모리 장치 및 메모리 시스템 |
JP2014106917A (ja) * | 2012-11-29 | 2014-06-09 | Canon Inc | 情報処理装置、その制御方法、及びプログラム |
KR102032887B1 (ko) * | 2012-12-10 | 2019-10-16 | 삼성전자 주식회사 | 반도체 패키지 및 반도체 패키지의 라우팅 방법 |
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- 2011-02-09 JP JP2011025905A patent/JP2011166147A/ja active Pending
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CN103681591A (zh) * | 2012-09-14 | 2014-03-26 | 瑞萨电子株式会社 | 半导体器件 |
CN103681591B (zh) * | 2012-09-14 | 2018-06-26 | 瑞萨电子株式会社 | 半导体器件 |
TWI641109B (zh) * | 2016-09-23 | 2018-11-11 | 日商東芝記憶體股份有限公司 | Memory device |
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US8796863B2 (en) | 2014-08-05 |
US20110193086A1 (en) | 2011-08-11 |
JP2011166147A (ja) | 2011-08-25 |
DE102010061616A1 (de) | 2011-08-11 |
US9070569B2 (en) | 2015-06-30 |
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