TW201110222A - A process of making semiconductor package - Google Patents

A process of making semiconductor package Download PDF

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Publication number
TW201110222A
TW201110222A TW099130144A TW99130144A TW201110222A TW 201110222 A TW201110222 A TW 201110222A TW 099130144 A TW099130144 A TW 099130144A TW 99130144 A TW99130144 A TW 99130144A TW 201110222 A TW201110222 A TW 201110222A
Authority
TW
Taiwan
Prior art keywords
wafer
thinned
protective layer
semiconductor
semiconductor package
Prior art date
Application number
TW099130144A
Other languages
English (en)
Other versions
TWI428972B (zh
Inventor
Wen-Chih Chiou
Weng-Jin Wu
Shau-Lin Shue
Original Assignee
Taiwan Semiconductor Mfg
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Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201110222A publication Critical patent/TW201110222A/zh
Application granted granted Critical
Publication of TWI428972B publication Critical patent/TWI428972B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

201110222 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置的製作，且特別是有關 於一種三維（3D)積體電路(ICs)的製作。 【先前技術】 由於各種電子元件（亦即電晶體、二極體、電阻器、 電容等）的積極度的持續改良，半導體工業已經歷持續快 φ 速的成長。大部分而言，積極度的改良來自不斷縮減最 小線寬，而使既定區域中可整合更多元件。三維積體電 路可以解決當裝置數量增加時’裝置間内連線的數量與 長度的限制。形成三維積體電路的〜種方法是晶粒_對_ 晶圓堆疊接合，其晶圓上接合一個或多個晶粒，且晶粒 的尺寸可小於晶圓上的晶片尺寸。為了減少半導體封裝 體的厚度、增加晶片速率及用於高密度製造，目前正努 力減少半導體.晶圓厚度。厚度的減少可藉由晶背研磨達 • 成，晶背研磨是施行在形成電路圖案的相反面，而具有 電路圖案的表面通常是以黏著材料貼附至一載板用為支 撐。因為薄化晶圓強度不足’容易受如彎曲及/或歪曲 (warp)的影響而形變’因在以切割製程個別的晶片封裝體 之前’需以成型化合物（如熱固環氧樹脂（therm〇_curing epoxy resin))封裝晶圓的表面。然而，在晶圓邊緣附近露 出的黏著材料，很容易受到蝕刻攻擊，在暫時性載板接 合及去接合(temporary carrier bonding and de-bonding)中 會造成問題。傳統在黏著材料的邊緣提供邊緣密封層， 0503-A34906TWF/noelle 3 201110222 但接下來的晶圓薄化塑命 材料的另一部分。 ”路鄰近晶圓邊緣的黏著 【發明内容】 一種半導體封裝製程，包括. 具有相對之第一表面及第 供曰曰圓，該晶圓 圓之第一表面貼一表面，利用-黏著層將該晶 之部分該黏著層，·自該第二表面薄緣 键仆曰F7 . ττ/ l 哥化孩日日圓’以形成一 屬化日日回，形成一保護層以 分；接合多個晶粒在該薄化//上鄉者層的該暴露部 人輪44壯寻化日日圓上；以及利用一成型化 ί製程晶圓及該多個晶粒。如前述之半導體封 其中該晶圓包括：__半導體基板，具有一正面 穿孔’填充有-導電材料，其至少通過- ::Μ半導體基板；以及一積體電路，形成在該半導體 基板的正面上。 T f to 對之笛種：導體封裝製程’包括：提供-晶圓，具有相 一-表面及第二表面；利用一黏著層將該晶圓之第 一表面貼附至-載板而暴露出鄰近該晶圓—邊緣之部分 該黏著層’自該第二表面薄化該晶圓，以形成一薄化晶 圓’形成一保護層以覆蓋該黏著層的該暴露部分以及該 晶圓的該邊緣·’在該薄化晶圓上接合一晶粒；利用一成 型化&物封裝該薄化晶圓及該晶粒；以及移除該載板。 如刖述之半導體封裝製程，其中該晶圓包括：一半導體 基板，具有一正面及一背面；一穿孔，以一導電材料填 入，其至少通過一部分該半導體基板；以及一積體電路， 〇503-A34906TWF/noelle 4 201110222 在該半導體基板的該正面上形成。 為讓本發明之上述和其他目的 明顯易懂，下文牯盤山鉍从―^ 和優點月匕更 作詳細說㈣ΐ較佳貫施例，並配合所附圖式， 【實施方式】 所敘書中關於，，一實施例，，的描述係指該實施例 十处、疋的物件、結構或特性被包含在至少-實施 .t中。因此’本說明書t多處的，，在—實施例中，，不必缺 為相同貫施例。再者，在—或多個實施例中於適當條件 :二：：特定的物件、結構或特性的組合。應注 圖式並非依比例繪製，而僅為說明使用。 在此第1A至1F圖為一系列剖面圖，用以說明形成 具有，晶圓邊緣之黏著材料之保護層的晶粒-對·晶圓堆 疊的實施例。 第1A圖為藉由黏著層14在載板12貼附上晶圓1〇 的-實施例的剖面圖。提供具有多個半導體晶片在其上 的晶圓10,該晶圓10包含半導體基板如石夕、石申化嫁水 晶晶圓、石墨、玻璃、石英、陶竟、熱固材料等。晶圓 10具有第-表面10a及與第—表面…相對的第 l〇b。在第一表面10a上形成包括主動及被動裝置之積體 電路如電晶體、電阻器、電容等，以與接合塾(ΐ5_ 及/或其他内連線結構接觸。在第一表面1〇a上形成黏著 層u’而後將載板12接合至黏著層14上以便在後續 程處理晶圓1〇時可更佳容易。在此同時，載板12 0503-A34906TWF/noelle 5 201110222 代地或額外地配置上對應的黏著表面。載板12是以可移 除或可溶材料構成如玻璃、金屬、陶曼、聚合物、梦等。 在一實施例中，晶圓10包括多個用於三維應用的矽 通孔（through silicon vias，TSVs)。如第 2A 圖所示，晶 圓10包含具有正面11a及背面lib的半導體基板11，其 中在正面11a上形成積體電路及内連線結構，而多個穿 孔（through vias)40至少部分穿過半導體基板11。穿孔40 係由正面11a延伸至背面lib且具有所需深度的金屬填 充插塞。穿孔40可與在内連結構上形成的接合墊電性連 接。穿孔40的製作是在”第一階内連線（first-level interconnection)’’之前進行，其係指在接觸結構（contact structure)及電晶體上的金屬間介電層（inter-metal dielectrics lay er，IMD layer)中圖案化的最底層金屬。此外 亦可在製造内連線結構之後執行金屬填入孔洞的製程 (metal-filled via process) ° 第1B圖為進行晶圓薄化製程（wafer thinning process) 的晶圓剖面圖。在接上載板12後，依半導體封裝體的使 用目的可在晶圓10無結構（structure-free)區域（第二表面 10b)中加工以得到所需的最後厚度，其可藉磨光 (grinding)、钮刻及/或研磨（polishing)製得預定厚度之薄 化晶圓10”。在一實施例中，晶圓10薄化至厚度約 至50μιη。在另一實施例中，晶圓10薄化至厚度約25Km 至250μιη。在提供包含穿孔40之晶圓10的實施例中’ 經過如第2Β圖所示的晶圓薄化製程後，穿孔40的一端 40a自薄化基板11”的背面lib”露出及/或突出。 0503-A34906TWF/noelIe 6 201110222 為了避免在後續蝕刻製程中破壞薄化晶圓10”的邊 緣l〇e及黏著層14的暴露部分I4p，形成保護層18以至 少覆蓋邊緣10e及暴露部分i4p。保護層18也可延伸覆 蓋部分的載板12如載板12的邊緣12e。因此在後續蝕刻 製程中可藉由保護層18保護其下的黏著層14。如第1C 圖所示在一實施例中，提供保護層18以覆蓋薄化晶圓1〇” 的第二表面l〇b”及黏著層μ的暴露部分14p，且其可延 伸覆蓋住載板12的邊緣i2e。保護層18的材料可為介電 材料如氧化膜、氮化膜、碳化膜、以聚合物為主的材料、 聚醯亞胺、環氧樹脂、旋塗式玻璃（s〇G)、旋塗（spin_〇n) 材料或前述之組合，利用化學氣相沉積（CVD)、物理氣相 沉積（PVD)、旋轉式塗佈法（spin_〇n c〇ating)、射出印刷 或其他未來發展的沉積製程形成。在提供穿孔4〇之晶圓 實施例中，保護層18是形成在薄化基板u”的背面 11b ’如第四圖所示’其可在後續製程中部分移除。第 2B圖^會示在背面Ub，，的保護層18，而在形成保護層 18之刖，可在背面Ub，，上執行任何其他的製程。 :1D及1E圖為在薄化晶圓1〇”上接合多個晶粒兀 而Τη，，Sa粒·對"'晶圓堆疊的剖面圖。在薄化晶圓10”的表 上形成包括電性連接（eleCtriCal COnnections)及/ 所&為導電結構44)的㈣金屬化層，而後 ί常=〇”上接合晶粒2〇,其中其連接方法包括-叙书用的方法如氧化物_對·童 人、鈉蚪X 氧化物接合、氧化物-對-矽接 製十了移除部份保護層18以暴露出用於 〇503-A34906TWF/noelJe 201110222 外部接點（external contact)的導電區域。晶粒2〇可 憶體晶片、無線電射頻(RF)晶片、邏輯晶片等二 ^有第-表面及第二表面，而在第-表面上形成積= 路。在-實施例中，在晶粒2 0的第一表面接合上薄化曰 圓10”。在一實施例中，在晶粒2〇白勺第二表面接合上= 化晶圓10”。在提供包含穿孔4〇之晶圓1〇的實施^中，， 如第2C圖所示，在穿孔4〇的一端術上形成導電 44如焊料凸塊或銅凸塊以接合晶粒2〇的第二表面或第一 表面。導電結構44也包括重分佈層（redistribmi〇n RDLs)及接合墊，在形成焊料凸塊或銅凸塊之前，可在薄 化晶圓10”的表面10b，，上形成接合墊。在背面金屬化製 程中，可部分移除保護層18，例如由穿孔4〇的一端 移除。在一實施例中，保護層18仍在薄化基板u” 面lib”上。 第1F圖為在晶粒-到-晶圓堆疊上進行成型製程的剖 面圖。在晶粒·到-晶圓堆疊上覆蓋成型化合物22並填入 相鄰晶粒20間的剩餘空間，但可不覆蓋薄化晶圓1〇，，的 邊緣區域。成型化合物22可為可固化材料如聚合物為主 的材料、樹脂為主的材料、聚醯亞胺、氧化矽、環氧樹 脂、苯並環丁烯（benz〇cyclobutenes，BCB)、SilkTM(D〇w
Chemical)或前述之組合。成型製程包括射出成型、壓縮 成型、模板印刷（stencil printing)、旋塗覆蓋或其他未來 發展的沉積製程。在覆蓋成型化合物22之後，進行固化 或烘烤步驟固化保護材料。 一般在晶圓級(wafer-level)測試完成後，會在成型化 0503-A34906TWF/noelle 8 201110222 合物頂部疊上膠帶，而後將晶粒_到-晶圓堆疊從載板12 分離以暴露薄化晶圓10”的第一表面l〇a。分離製程是藉 由如利用溶劑、利用紫外光照射或剝除（pulled off)。再 者’在薄化晶圓10”的第一表面l〇a上’形成各半導體晶 片的外部接觸（亦即焊料凸塊、包含銅的凸塊或其組合) 以與電性終端接合’接著按一般方式沿著分割線切割封 褒後的晶粒-到-晶圓堆疊以形成個別的半導體封裝體。在 切割之後’透過如異方性導電膜（anis〇tr〇picaUy conductive connection film)在IC卡上安裝堆疊的一或多 個晶片。 第3A至3B圖的剖面圖說明在晶粒_到_晶圓堆疊形 成黏著材料之保護層的實施例。與在第1A至1F圖及第 2A至2C圖相同或類似的敘述在此省略。藉黏著層14在 載板12上貼附上晶圓1〇，而後晶圓1〇進行薄化製程至 斤需的最終厚度。為了避免在後續ϋ刻製程中破壞黏著 層Μ的暴露部分Μρ，如第3Β圖所示，在晶圓薄化製 轾後，形成保護層18以覆蓋鄰近晶圓邊緣…的黏著層 =暴露部分14p。保護層18也可延伸覆蓋薄化晶圓 緣，但沒有覆蓋整個暴露表面i〇b”。保護層u 的延伸覆蓋載板12的邊緣12e。在後續蝕刻 後在/專化晶圓10”的表面l〇b”上，开彡杰4 二電或其他結構的f側金屬化層 ： 二二= 二來物如第3B圖所示，在晶 隹且上覆盍成型化合物22且填入相鄰晶粒20 〇503-A34906TWF/noeIle 0 201110222 間的剩餘空間。 雖然本發明已以數個較佳實施例揭露於上，然其並 非用以限定本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者為準。 0503-A34906TWF/noeIIe 10 201110222 【圖式簡單說明】 ,、第1A〜1F圖為一系列剖面圖，用以說明在晶圓邊緣 形成黏著材料的保護層的—實施例。 第2A〜2C圖為一系列剖面圖，用以說明處理包含穿 孔（through vias)之晶圓的方法的一實施例。 ，、第3A〜3B圖為一系列剖面圖，用以說明在晶圓邊緣 形成黏著材料的保護層的另一實施例。
【主要元件符號說明】
20〜晶粒； l〇b〜薄化晶圓10”的第二表面； 10〜晶圓； 10b〜晶圓10的第二表面 12〜載板； 11〜半導體基板； 40〜穿孔； 1〇”〜薄化晶圓； 18〜保護層； 10 a〜晶圓10的第一表面； 14〜黏著層； 22〜成型化合物； 40a〜穿孔40的-端； 11”〜薄化基板； 12e〜載板12的邊緣； 44〜導電結構； lib”〜薄化基板的背面； 10e〜溥化晶圓1〇”的邊緣； 14p〜黏著層14的暴露部分； 11a〜半導體基板η的正面； lib〜半導體基板11的背面。 0503-A34906TWF/noelle 11

Claims (1)

  1. 201110222 七 面 申請專利範圍： 1·一種半導體封裝製程，包括： 提供一晶圓，該晶圓具有相斟 旁相對之第一表面及第二表 暴黏著層將該晶圓之第一表面貼附至-載板而 暴路出鄰近該晶圓一邊緣之部分該黏著層· 自該第二表面薄化該晶圓，以形成：薄化晶圓； 形成-保護層以覆聽轉層的該暴露部分； 接合多個晶粒在該薄化晶圓上；以及 利用成型化合物封襄該薄化晶圓及該多個晶粒。 2.如申请專利範圍第i項所述之半導體封裝製程，其 中該保護層覆蓋該晶圓邊緣。 3·如申凊專利㈣第1項所述之半導體封裝製程，其 中該保護層覆蓋鄰近該晶圓邊緣的部分載板。 4. 如申請專利範圍第1項所述之半導體封裝製程，其 中該保護層覆蓋至少一部分該晶圓的第二表面。 5. 如申請專利範圍第1項所述之半導㈣裝製程，其 中該保4層包括氧化膜、氮化膜、碳化膜、乾膜、旋塗 材料膜或前述之組合。 6.如申請專利範圍第1項所述之半導體封裝製程，其 中該晶圓包括： 一半導體基板，具有一正面及一背面； 一穿孔，填充有一導電材料，其至少通過一部分該 半導體基板；以及 一積體電路，形成在該半導體基板的正面上。 0503-A34906TWF/noelle 12 201110222 7. 如申請專利範圍第6項所述之半導體封農製程，其 中該晶圓進行薄化後，該半導體基板的背面上暴露出該 穿孔的一端。 8. 如申請專利範圍第6項所述之半導體封裝製程，其 中該晶圓進行薄化後，在該半導體基板的背面上形成該 保護層。 X 9. 如申請專利範圍第7項所述之半導體封裝製程，更 包括在該薄化晶圓上接合該多個晶粒之前，在該穿孔的 鲁 該暴路端形成一導電結構。 10. 如申請專利範圍第9項所述之半導體封裝製程， 其中該導電結構包括一重分佈層（redistribution layer RDL)。 ’
    0503-A34906TWF/noelIe 13
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