CN210200731U - 集成无源器件ipd管芯 - Google Patents

集成无源器件ipd管芯 Download PDF

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Publication number
CN210200731U
CN210200731U CN201920780908.7U CN201920780908U CN210200731U CN 210200731 U CN210200731 U CN 210200731U CN 201920780908 U CN201920780908 U CN 201920780908U CN 210200731 U CN210200731 U CN 210200731U
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Prior art keywords
substrate
ipd
layer
tsv
die
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Takashi Noma
野间崇
Hideyuki Inotsume
秀行猪爪
Kazuo Okada
和央冈田
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本实用新型题为“集成无源器件IPD管芯”。本实用新型公开了一种集成无源器件管芯。在一个一般方面，所述集成无源器件(IPD)管芯包括至少一个无源部件，所述至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中。所述IPD管芯包括穿衬底通孔(TSV)穿衬底通孔(TSV)，所述穿衬底通孔从所述衬底的背面朝所述衬底的所述前表面延伸。所述TSV限定通向至少一个无源部件的互连通路，所述至少一个无源部件嵌入在设置于所述衬底的所述前表面上的所述绝缘体材料中。所述衬底具有小于所述衬底的初始厚度的四分之三的厚度。

Description

集成无源器件IPD管芯
本申请是申请日为2018年8月15日、申请号为201821308749.2、发明名称为“集成无源器件IPD管芯”的实用新型专利申请的分案申请。
技术领域
本公开涉及半导体器件，并且具体地讲，涉及集成无源器件(IPD)。
背景技术
现代电子器件(例如，晶体管)和电路被制造为半导体衬底上的集成电路(IC)。在电子电路封装中，IC安装在电路板上。电子电路封装还可包括分立无源部件，诸如安装在电路板上的电容器、电感器和电阻器，以制成完整的运算电子电路。在许多情况下，无源部件(诸如电容器、电感器和电阻器部件)可被制造为半导体衬底上的集成无源器件(IPD)。与例如电子电路封装中使用的独立式分立无源部件相比，IPD可具有减小的尺寸、增加的密度或优异的电特性。IPD用作例如低成本、小轮廓射频(RF)部件 (例如，电容器和电感器以匹配手机端口适配器(PA))并且互连在如手机和其他无线设备的消费品中。IPD可用作RF衬底以匹配RF电子器件中的其他管芯。
发明内容
根据本公开的一个方面，提供有一种集成无源器件IPD管芯，包括：具有背面和正面的衬底，所述衬底具有磨削到小于初始的衬底的厚度的四分之三的厚度；绝缘体材料层，所述绝缘体材料层设置在所述衬底的正面上；无源器件，所述无源器件包括电感器、电阻器和电容器中的至少一个，所述无源器件被所述绝缘体材料层完全包围，所述无源器件具有设置在暴露端子和另一端子之间的器件结构；和贯穿衬底通孔TSV，所述贯穿衬底通孔从所述衬底的背面朝所述衬底的正面表面延伸到所述绝缘体材料层中的绝缘体材料腔中，所述绝缘体材料腔暴露由所述绝缘体材料层完全包围的无源器件的端子，所述TSV限定通向由设置在所述衬底的正面上的绝缘体材料层完全包围的无源器件的暴露端子的互连通路。
优选地，其中所述TSV是渐缩TSV，所述渐缩TSV具有渐缩壁，所述渐缩壁从较宽的表面开口向较窄的TSV底部倾斜。
优选地，所述IPD管芯还包括：铜层，所述铜层设置在所述衬底的所述背面上以及沿着所述渐缩壁并在所述TSV底部上设置在所述TSV中，所述铜层限定对嵌入在所述绝缘体材料中的所述无源器件的端子的电连接。
优选地，所述IPD管芯还包括：阻焊层；和，晶圆凸块，所述晶圆凸块与所述铜层接触。
优选地，其中所述器件结构包括以下中的至少一个：电感器的感应导线或线结构，电阻器的电阻材料垫，和电容器的电容器间隙材料垫。
优选地，其中所述TSV是干法蚀刻的。
优选地，其中所述IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到包括在板上的导电垫。
根据本公开的另一个方面，提供有一种集成无源器件IPD管芯，包括：至少一个无源部件，所述至少一个无源部件完全嵌入在设置在衬底正面上的绝缘体材料层中；贯穿衬底通孔TSV，从所述衬底的背面朝所述衬底的正面延伸；以及铜层，所述铜层设置在所述衬底的背面上以及所述TSV 中，所述铜层限定穿过所述TSV的对完全嵌入在所述绝缘体材料中的所述至少一个无源部件的端子的电连接。
优选地，其中所述衬底具有小于所述衬底的初始厚度的四分之三的厚度。
优选地，其中所述IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到包括在板上的导电垫。
在一个一般方面，集成无源器件(IPD)管芯包括至少一个无源部件，该至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中。IPD管芯包括贯穿衬底通孔(TSV)，该贯穿衬底通孔从衬底的背面朝衬底的前表面延伸。TSV限定通向至少一个无源部件的互连通路，该至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中。衬底具有小于衬底初始厚度的四分之三的厚度。
优选地，所述至少一个无源部件包括具有嵌入在所述绝缘体材料中的端子的电感器、电阻器或电容器中的至少一者。
优选地，所述TSV是渐缩TSV，所述渐缩TSV具有渐缩壁，所述渐缩壁从较宽的表面开口向较窄的TSV底部倾斜。
优选地，所述IPD管芯还包括铜层，所述铜层设置在所述衬底的所述背面上以及沿着所述渐缩壁并在所述TSV底部上设置在所述TSV中，所述铜层限定对嵌入在所述绝缘体材料中的所述至少一个无源部件的端子的电连接。
优选地，所述的IPD管芯还包括：阻焊层；和晶圆凸块，所述晶圆凸块与所述铜层接触。
在另一个一般方面，集成无源器件(IPD)管芯可包括至少一个无源部件和贯穿衬底通孔(TSV)，该至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中，该贯穿衬底通孔从半导体衬底的背面朝衬底的前表面延伸。IPD管芯可包括铜层，该铜层设置在衬底的背面上以及TSV中。铜层可限定穿过TSV的对嵌入在绝缘体材料中的所述至少一个无源部件的端子的电连接。
优选地，所述IPD管芯的所述衬底具有小于所述衬底的初始厚度的四分之三的厚度。
优选地，所述IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到包括在板上的导电垫。
在又一个一般方面，方法包括磨削衬底的背面以减小半导体衬底的中心部分的厚度，同时将机械支撑环留在衬底的外部部分上，并且从衬底的背面形成贯穿衬底通孔(TSV)。TSV限定通向至少一个无源部件的互连通路，该至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中。
附图说明
图1A是根据本公开的原理的示例性集成无源器件(IPD)的图示。
图1B和图1C是根据本公开的原理的示例性集成无源器件(IPD)管芯的图示。
图2A至图2S示出了根据本公开的原理在通过半导体器件制造工艺的多个步骤处理衬底以制造示例性IPD时衬底的剖视图。
图3是根据本公开的原理的耦接到电路板的示例性IPD的图示。
图4A至图4C示出了根据本公开的原理的结合至少图2A至图2S描述的工艺的变型的剖视图。
图5是示出制备本文所述的器件的方法的流程图。
在各个附图中，类似的参考符号或标号表示类似的元件。
具体实施方式
相关申请
本申请要求2017年11月22日提交的美国专利申请15/813,710的优先权和权益，该美国专利申请要求2017年8月23日提交的美国临时申请 62/549,206的优先权，这两份申请全文均以引用的方式并入本文。
可使用半导体器件制造工艺制造集成无源器件(IPD)，其包括支撑在半导体衬底上的一个或多个无源部件(例如，诸如电容器、电感器或电阻器的部件)。半导体器件制造工艺可类似于用于形成日常电气和电子器件中存在的集成电路的工艺。半导体器件制造工艺可包括光刻和化学处理步骤的多步骤序列，在此期间在由半导体材料制成的衬底上逐层形成电子电路。用于材料图案化、沉积、移除等的前端工艺可用于将集成无源器件 (IPD)的有源部件(例如，金属氧化物半导体场效应晶体管(MOSFET)、双极结型晶体管(BJT)、二极管)和无源部件(例如，电容器、电感器或电阻器)嵌入在半导体衬底上的绝缘体材料中。金属化工艺可用于实现对嵌入在IPD的半导体衬底上的绝缘体材料中的有源部件和/或无源部件的电连接。
使用半导体器件制造工艺，可由具有不同电特性的材料层形成特别是 IPD的无源部件。可通过多种沉积技术在半导体衬底之上或之中形成这些层。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和化学镀工艺。每一层均可被图案化以形成无源部件的各部分或者 IPD中的各部件之间的电连接。
这些层可使用光刻法进行图案化，该光刻法涉及在待图案化的层上方沉积感光材料(例如，光刻胶)。可使用光将图案从光掩模转移到光刻胶。可使用溶剂移除受到光照射的光刻胶图案的部分，从而暴露待图案化的下层的部分。可移除光刻胶的剩余部分以留下图案化层。或者，可通过使用诸如电解电镀或化学镀的技术将材料直接沉积到由此前沉积/蚀刻工艺形成的区域或空隙中，而使一些层图案化。
将材料薄膜沉积在现有图案上方可扩大下层图案并且形成非均匀的平坦表面。可能需要均匀的平坦表面来生产更小且更密集封装的器件部件。可使用平面化从晶圆的表面移除材料并且产生均匀的平坦表面。平面化涉及使用抛光垫来抛光晶圆的表面。在抛光期间将研磨材料和腐蚀性化学品添加到晶圆的表面。
蚀刻到半导体衬底中的贯穿衬底通孔(TSV)(也可称为贯穿芯片通孔或称为贯穿硅通孔(如果使用硅衬底的话))可提供垂直互连通路以便实现对嵌入在IPD的半导体衬底上的绝缘体材料中的无源部件的电连接。
根据本公开的原理，可在已在半导体衬底的正面(其可包括前表面) 上的绝缘体材料中制造无源部件之后，使用在半导体衬底的背面中蚀刻的后通孔TSV建立对嵌入在IPD的半导体衬底上的绝缘体材料中的无源部件的电连接。
图1A示出了根据本公开的原理的IPD 100A的示例性结构的一部分，其中通过半导体衬底背面的贯穿衬底通孔(TSV)建立对无源部件的电连接。
IPD 100A可例如包括支撑在半导体衬底120(也可称为衬底)(例如，减薄硅晶圆)上的IPD绝缘体层110。衬底120可具有正面(例如，正面100A-fr)和背面(例如，背面100A-bk)。IPD绝缘体层110可支撑在衬底120的正面(例如，正面100A-fr)上。IPD绝缘体层110可包括无源部件(例如，电感器结构111、电容器结构112和电阻器结构113)完全或至少部分嵌入在其中的不同绝缘体层(例如，二氧化硅层11a-1、11a-2、 11a-3等以及氮化硅层(SiN)11b-1、11b-2、11b-3等)。每个IPD绝缘体层 110可具有约10μm或更小的厚度。IPD绝缘体层110支撑在其上的半导体衬底120(例如，减薄硅晶圆)可具有约200μm或更小(例如，150μm)的厚度A1(其可为衬底120的初始厚度的四分之三或更小(例如，二分之一、四分之一)。在一些实施方式中，衬底120可为高电阻率硅晶圆。衬底与嵌入在IPD绝缘体层110中的IPD 100A的端子112a-1之间的距离A2 可为大约5-10微米(例如，5.6μm)。
在IPD 100A中，电感器结构111可例如包括设置在表面接合垫111b 与端子112a-2之间的感应导线或线结构111a。电容器结构112可例如包括设置在栅极端子112a-4和端子112a-3之间的电容器间隙材料垫112b。电阻器结构113a可例如包括设置在端子112a-2和端子112a-3之间的电阻材料垫113a。在上述无源部件中，导电元件(例如，感应导线或线结构111a、表面接合垫111b、端子112a-1、端子112a-2、端子112a-3、端子112a-4 等)可由导电材料(例如，铜和/或铝等)制成。例如，部件端子(例如，端子112a-2、端子112a-3、端子112a-4等)可由铝制成，并且感应导线或线结构111a可由铜制成。电容器间隙材料垫112b可由电介质材料(例如，二氧化硅、氧化铪、未掺杂多晶硅等)制成。电阻材料垫113a可由电阻材料(例如，氮化钛(TiN)、钛-钨(TiW)、氮化钽(TaN)、多晶硅等)制成。
在图1A所示的示例性IPD 100A中，可由在IPD绝缘体层110支撑在其上的衬底120的背面(例如，背面100A-bk)上蚀刻的贯穿衬底通孔(例如，TSV 130a)提供端子(例如，端子112a)与嵌入的无源部件(例如，电感器结构111、电容器结构112或电阻器结构113)电连接的背面通路。 TSV 130a可例如从表面开口130b延伸到TSV底部130d(这可暴露例如嵌入在IPD绝缘体层110中的无源部件的端子112a)。TSV底部130d可具有介于几微米(例如，5μm、10μm)和数百微米(例如，800μm、1000μm、 2000μm)之间的宽度A3(例如，直径)。TSV 130a可具有渐缩结构，其中表面开口130b宽于TSV底部130d，并且渐缩壁130c从较宽的表面开口130b向较窄的TSV底部130d倾斜。铜层132可设置在衬底120的背面 (例如，背面100A-bk)上，并且可沿着渐缩壁130c并在TSV底部130d 上共形地设置在TSV 130a中。铜层132可从衬底120的背面(例如，背面 100A-bk)提供对IPD绝缘体层110的无源部件的端子112a的电连接。
可通过前端半导体器件制造工艺对半导体衬底上的不同材料(例如，电介质和绝缘体材料(诸如二氧化硅或氮化硅等)和导电材料(诸如铜、铝、多晶硅等))进行逐层图案化、沉积和移除，从而在IPD绝缘体层 110中形成无源部件的各种元件(例如，感应导线或线结构111b、端子 112a-1等)。半导体衬底120可例如为标准衬底(例如，具有525μm典型厚度的100mm直径硅晶圆，或具有775μm典型厚度的300mm直径硅晶圆等)。在形成其中嵌入有IPD部件的IPD绝缘体层110之后，可将半导体衬底120减薄到约200μm或更小(例如，150μm)的厚度。此外，可从背面(例如，背面100A-bk)在衬底120(例如，减薄硅晶圆)中蚀刻贯穿衬底通孔(例如，TSV 130a)以便实现通向嵌入在衬底120的正面(例如，正面100A-fr)上形成的IPD层110中的无源部件111、112、113的垂直互连通路。可使用导电材料(例如，铜层132)建立对嵌入在IPD层110中的无源部件的垂直互连。
虽然图1A的示例性IPD 100A被描述为使用硅晶圆作为从背面蚀刻后通孔TSV130a的示例性半导体衬底120，但其他IPD可使用其他种类的衬底(例如，玻璃、氧化铝(Al2O3)或氧化铍(BeO)衬底)，其中可从背面蚀刻后通孔TSV(例如，后通孔TSV 130a)以便实现通向嵌入在正面IPD层 110中的无源部件111、112、113的垂直互连通路。
图1B和图1C示出了根据本公开的原理的示例性集成无源器件(IPD)管芯100B，其具有后通孔贯穿衬底通孔(TSV)以便实现通向器件部件的互连通路。IPD管芯100B可例如包括设置在衬底21(例如，玻璃衬底)上的可调谐射频(RF)电路30。衬底21可具有正面(例如，正面21-fr)和背面 (例如，背面21-bk)。如图1B中的剖视图及图1C中的俯视平面图所示，设置在衬底21的正面上的RF电路30的无源部件可例如包括电阻器 31、电容器32和电感器33。无源部件可至少部分地嵌入在设置于衬底的正面上的绝缘体层22(例如，二氧化硅层)中。
电阻器31可包括设置在端子31-1和导电垫31-3之间的电阻材料层31- 2(例如，氮化硅(SiN)或其他高K材料层)。端子31-1和导电垫31-3可由金属(例如，铜)制成。电容器32(其可为可调谐电容器)可包括设置在端子32-1和导电垫32-3之间的电容间隙材料32-2。电容间隙材料32-2可例如为钛酸锶钡(BST)薄膜。端子32-1和导电垫32-3可由金属(例如，铜或铝)制成。电感器33可包括连接到导电垫33-2的导线或线圈结构33- 1。导线或线圈结构33-1和导电垫33-2可由金属(例如，铜)制成。导线或线圈结构33-1可连接到电阻器端子31-1和电容器导电垫32-3以形成电路30。电路30还可包括接合到电阻器导电垫31-3的正面引线接合34-1以及接合到电容器端子32-1的正面引线接合34-2以便实现对电路30的正面电连接。引线接合25-1和引线接合25-2可例如为金引线接合。
设置在衬底21的正面21-fr上的导电垫31-3、32-3和33-2也可用作电路30的电路端子。在图1B和图1C所示的示例性IPD管芯100B中，根据本公开的原理，蚀刻穿过衬底20的渐缩TSV(例如，TSV 23-1和TSV-23- 2)提供通向电路30的电路端子(例如，分别为导电垫31-2和导电垫32- 3)的背面互连通路。在图1B和图1C所示的示例性IPD管芯100B中，可例如镀覆在衬底的背面上及TSV中的导电层24(例如，铜层)通过TSV (例如，TSV 23-1和TSV-23-2)提供对导电垫31-2和导电垫32-3的电连接。
结合图2A至图2S来描述用于制造示例性IPD的示例性半导体器件制造工艺。图2A至图2S示出了根据本公开的原理在通过半导体器件制造工艺的多个步骤处理衬底以制造示例性IPD(例如，IPD 215，图2S)时衬底的剖视图。虽然在各个附图中类似的参考符号或标号用于标记类似的元件，但为了视图的视觉清晰和描述的简单起见，未在一些附图中标记一些元件。
图2A至图2S所示的半导体器件制造工艺在下文可称为IPD制造工艺。IPD制造工艺的多个步骤可例如涉及衬底的逐层晶圆级处理。这些步骤可例如包括衬底上的(或衬底的)光刻胶涂布、光刻图案化、材料沉积以及移除。由IPD制造工艺制造的IPD 215可处于封装就绪状态。
如图2A所示，IPD制造工艺从选择具有正面(例如，正面201-fr)和背面(例如，背面201-bk)的半导体衬底(例如，高电阻率Si晶圆201) 开始，并且在图2B中，在半导体衬底的正面(例如，正面201-fr)上形成第一绝缘体层202a。第一绝缘体层可例如由二氧化硅(SiO2)、氮化硅(SiN) 和/或氮氧化硅(SiON)材料或它们的组合中的任何一者制成。半导体衬底可例如为约275μm厚的51mm直径衬底、约375μm厚的76mm直径衬底、约 625μm厚的125mm衬底、约675μm厚的150mm直径衬底、约725μm厚的 200mm直径衬底、或约775μm厚的300mm直径衬底。
IPD制造工艺还可包括图2C所示在第一绝缘体层202a上形成电阻器的图案化的电阻层203；图2D所示形成图案化的第二绝缘体层202b；以及图2E所示在其上形成图案化的第一金属层204a。图案化的电阻层203可例如由TiN、TiW、TaN、多晶硅材料或它们的组合中的任何一者制成。与第一绝缘体层202a一样，图案化的第二绝缘体层202b可由SiO2、SiN和SiON材料或它们的组合中的任何一者制成。图案化的第一金属层204a可由任何金属材料(例如，铝(Al)、铜(CU)、金属合金等)中的任何一者制成。图案化的第一金属层204a可包括嵌入在IPD 215(图2S)中的无源部件的端子(例如，如同端子112a-1，IPD 100A)。
图2E以示意性剖视图示出了在如IPD制造工艺的图2E所示的那样处理衬底201之后该衬底的结构。
如图2F所示，IPD制造工艺还可包括形成电容器的图案化的间隙层 205。电容器的图案化的间隙层可由SiN、氧化钽(TaO)、铪(HfO)材料或它们的组合制成。
此外，如图2G所示，IPD制造工艺还可包括形成电容器电极的图案化的第二金属层204b；形成图案化的第三绝缘体层202c；以及形成图案化的第三金属层204c。与图案化的第一金属层一样，图案化的第二金属层204b 和图案化的第三金属层204c可例如由Al、Cu、AlCu、AlSi和AlSiCu材料或它们的组合制成。与第一和第二绝缘体层一样，图案化的第三绝缘体层可例如由SiO2、SiN和SiON材料或它们的组合制成。
如图2H所示，IPD制造工艺还可包括形成图案化的第四绝缘体层 202d；以及形成用于接触的图案化的第四金属层204d。与图案化的第三金属层一样，图案化的第四金属层可例如由Cu、Al、AlCu、AlSi、AlSiCu材料或它们的组合制成。与第一、第二和第三绝缘体层一样，图案化的第四绝缘体层可由SiO2、SiN和SiON材料或它们的组合制成。
在IPD制造工艺的该阶段，使用前端晶圆级处理(例如，如图2A至图2H所示)可完全形成嵌入的无源部件：IPD 215的电阻器206、电容器 207和电感器208。图2H以示意性剖视图示出了IPD工艺的经前端处理的衬底的结构。经前端处理的结构包括嵌入在衬底201的正面(例如，正面 201-fr)顶上的绝缘体层202a-202d中的无源部件，即电阻器结构206、电容器结构207和电感器结构208。为了便于本文描述，经前端处理的结构在本文可称为半处理的IPD器件。
在半处理的IPD器件中，电阻器结构206包括此前在第一绝缘体层 202a上形成的电阻器的图案化的电阻层203。可通过由IPD制造工艺中的图案化的第一金属层204a、图案化的第二金属层204b、图案化的第三金属 204c和图案化的第四金属层204d的后续形成(图2F、图2G和图2H)所制成的端子来电连接图案化的电阻层203。电容器207包括此前在第一金属层204a上图案化的间隙层205(图2F)以及由IPD制造工艺中的图案化的第二金属层204b、图案化的第三金属204c和图案化的第四金属层204d的后续形成(图2G和图2H)所制成的端子。电感器结构208包括由IPD制造工艺中的图案化的金属层204a、204b、204c和204d的形成(图2F、图 2G和图2H)所制成的线圈结构的图案化导线。
IPD制造工艺中的另外步骤(例如，图2I至图2S)可涉及经前端处理的衬底201的后端或背面处理。IPD制造工艺可包括胶带贴装工艺以将保护胶带209a施加到经前端处理的衬底201的正面(例如，前表面)。图2I示出了例如耦接到(例如，安装到)经前端处理的衬底201的前表面上的胶带209a。
如图2J所示，IPD制造工艺中的另外步骤可涉及背面磨削经前端处理的衬底201以对衬底201(示出为减薄衬底201t)的中心部分201c进行减薄以便实现背面成形，同时在衬底201的外圆周上保留机械支撑环201r；以及湿法蚀刻或抛光以使磨削表面平滑。磨削工艺(例如，TAIKO磨削工艺)可用于背面磨削衬底201并且形成机械支撑环201r。磨削工艺可仅从背面(例如，背面201-bk)磨薄衬底的中心部分201c，同时在衬底外边缘上的环区段中留下框架或支撑环(大约3mm宽)。减薄衬底201t的中心部分201c的厚度A4可例如为5μm至200μm厚，而大约3mm宽机械支撑环 201r的厚度A5可例如为约200至800μm(即，大约与起始衬底厚度(图 2A至图2I所示)相同)。因此，减薄部分的厚度A4与支撑环201r的厚度 A5之比可介于160∶1至1∶1之间。在衬底的外圆周上具有机械支撑环201r 改善了晶圆强度，并且可降低在减薄衬底201t的进一步处理期间可发生的衬底翘曲和边缘崩裂。
如图2K所示，IPD制造工艺还可包括在减薄衬底201t的背面(例如，背面201-bk)上形成图案化的光刻胶层210(例如，铜光刻胶)(例如，以准备好穿过背面光刻胶层210中的开口形成贯穿衬底通孔(TSV))。
用于形成贯穿衬底通孔(TSV)的IPD制造工艺可包括如图2L所示，使用硅干法蚀刻穿过光刻胶216中的图案开口在衬底中蚀刻TSV 211。
图2L以示意性剖视图示出了在形成贯穿蚀刻的TSV 211之后经处理的衬底的结构。如图2L所示，减薄衬底中的硅干法蚀刻的TSV(例如，TSV 211)可为渐缩TSV，其从减薄衬底201t的背面表面穿过衬底的厚度大约延伸到衬底201t与第一金属层(例如，金属层204a)的正面界面。
如图2M所示，IPD制造工艺还可涉及移除减薄衬底的背面(例如，背面201-bk)上的图案化的光刻胶；以及使用SiO2蚀刻(在TSV 211的底部)在第一绝缘体层(例如，绝缘体层201a)中形成开口，从而穿过TSV 211暴露第一金属层(例如，金属层204a)的表面。SiO2蚀刻可涉及穿过 TSV 211对第一绝缘体层(例如，绝缘体层201a)进行干法蚀刻或湿法蚀刻。图2M以示意性剖视图示出了在IPD制造工艺中的SiO2蚀刻之后经处理的衬底的结构。
如图2N所示，IPD制造工艺还可包括硅干法蚀刻以另外回蚀或清洁硅表面；以及在衬底201t的暴露表面上及在TSV 211的暴露硅表面上沉积钛/ 铜阻挡层或晶种层212。可例如通过溅射工艺沉积钛/铜阻挡层或晶种层 212。
接下来，如图2O所示，IPD制造工艺还可包括在钛/铜阻挡层或晶种层212上形成图案化的光刻胶层213；以及如图2P所示，在背面衬底表面上及在TSV 211中沉积铜层214。沉积铜层214可涉及电解或化学镀铜工艺。
接下来，如图2Q所示，IPD制造工艺还可包括移除图案化的光刻胶 213；以及准备铜层214的表面以用于晶圆级封装(例如，以用于倒装芯片凸块和组件)。准备铜层214的表面可包括将凸块下金属(UBM)蚀刻(例如，钛(Ti)和钛钨(TiW)蚀刻)施加到铜层214。
IPD制造工艺还可包括如图2R所示，胶带移除和胶带贴装工艺，例如以将保护胶带209a替换为磨削工艺胶带209b)；以及移除机械支撑环201r (例如，通过背面磨削到降低的高度)。移除机械支撑环201r可例如使用环磨削工艺(例如，TAIKO环磨削工艺)。环磨削工艺可背面磨削机械支撑环201r，使得减薄衬底201t的环区段(即，晶圆外边缘)与中心部分之间的高度差减小。可减小高度差，例如以允许在IPD制造工艺200的另外步骤中经处理的衬底附连到芯片切分胶带以及更高质量的切分。图2R以示意性剖视图示出了IPD制造工艺的环磨削工艺后经处理的衬底的结构(其中机械支撑环201r被磨掉)。
如图2S所示，IPD制造工艺还可包括胶带贴装工艺以便将切分胶带 (未示出)附连到经处理的衬底；并且从经处理的衬底切分芯片或管芯 (例如，IPD 215)。
经处理的衬底的经切分的芯片或管芯可从切分胶带拾取并且用作电子电路封装中的单独IPD芯片或管芯。
在电子电路封装的示例性实施方式中，根据本公开的原理，经切分的 IPD芯片或管芯(例如，IPD 100A、IPD 215)可耦接到(例如，安装到) 与电子电路封装中的其他部件互连的印刷电路板的导电垫(例如，接地垫)上。
图3示出了例如电子电路封装实施方式，其中IPD(例如，IPD 100A)耦接到(例如，安装到)印刷电路板320的接地垫(例如，铜垫 321)上。在图3所示的示例中，IPD 100A可例如使用导电环氧树脂322耦接(例如，安装)以便实现接地垫321与IPD 100的背面上的铜层132之间的电接触。铜层132(其例如穿过IPD 100A的TSV 103a接触器件端子 112a)可提供嵌入在IPD 100A中的一个或多个无源部件(例如，电感器结构111、电容器结构112和电阻器结构113)与电子电路封装中的其他部件 (未示出)之间的稳定电接触。
在一些电子电路封装实施方式中，IPD(例如，IPD 100A)可使用晶圆凸块形成技术来与电子电路封装中的其他部件互连。晶圆凸块形成技术可涉及在晶圆级以凸块或焊球的形式施加到IPD器件的焊料的使用。焊料凸块可接合在IPD管芯(例如，IPD 100A)的有源表面(例如，铜层 132)与印刷电路板的顶表面或电子电路封装中任何类型的衬底载体之间。
图2A至图2S所示的IPD制造工艺可包括附加或替代步骤以便准备处于使用晶圆凸块形成法的电子电路封装实施方式的就绪状态的IPD。例如，经改进的IPD制造工艺可包括图4A至图4C所示的一些处理变化。如图4A所示(例如，在光刻胶移除之前或在结合图2M所述的干法蚀刻之前)，在衬底201t的暴露表面上生长氧化物层216。
图4A以示意性剖视图示出了在使用经改进的IPD制造工艺生长氧化物层216的情况下在铜镀覆和光刻胶移除(结合图2Q所述)之后经处理的衬底的结构。如图4A所示，氧化物层216可位于衬底201t的表面和溅射沉积(结合图2N所述)的钛/铜阻挡层或晶种层212之间。
此外，经改进的IPD制造工艺还可包括形成阻焊层217并且形成(例如，滴落)晶圆凸块或焊球218。晶圆凸块或焊球218可由电子电路封装的晶圆凸块形成技术中使用的焊接材料制成，并且阻焊层217可由通常施加到印刷电路板(PCB)的铜迹线以便保护免于氧化并且防止在紧密间隔的焊接垫之间形成焊接桥的聚合物材料制成。晶圆凸块或焊球218可用于焊接 (即，接合)IPD管芯(例如，IPD 315)的有源表面(例如，铜层132) 和印刷电路板的顶表面或电子电路封装中任何类型的衬底载体。
经改进的IPD制造工艺的所述形成阻焊层217和所述形成(例如，滴落)晶圆凸块或焊球可在准备IPD工艺的晶圆级封装的铜层214的表面 (图2Q)之后以及在示例性实施方式中在环形支撑件201r移除(图2R所示的胶带移除和环磨削)之前执行。
图4B以示意性剖视图示出了在环形支撑件201r移除(图2R所示的胶带移除和环磨削)之后经处理的衬底的结构。图4B示出了IPD制造工艺的改进型式，其包括形成阻焊层217并且形成与铜层214接触的晶圆凸块或焊球218。
如图4C所示，IPD制造工艺的其余部分(例如，图4C所示)可如之前(图2S)一样在经改进的IPD制造工艺中执行，其包括将切分胶带耦接 (例如，附连)到经处理的衬底，从经处理的衬底切分芯片或管芯(例如，IPD 315)，以及从切分胶带拾取经切分的芯片或管芯(例如，IPD 315)，这些经切分的芯片或管芯处于准备好使用晶圆凸块形成技术在电子电路封装中用作单独IPD芯片或管芯的状态。
图5是示出制备本文所述的器件的方法的流程图。如图5所示，该方法包括磨削半导体衬底的背面以减小半导体衬底的中心部分的厚度，同时将机械支撑环留在衬底的外部部分上(框510)。在一些实施方式中，厚度可小于200微米。在一些实施方式中，所述至少一个无源部件包括嵌入在绝缘体材料中的具有端子的电感器、电阻器或电容器中的至少一者。
该方法还可包括从衬底的背面形成贯穿衬底通孔(TSV)，其中TSV限定通向至少一个无源部件的互连通路，该至少一个无源部件嵌入在设置于半导体衬底的前表面上的绝缘体材料中(框520)。
在一些实施方式中，所述磨削衬底的背面包括使用磨削工艺将衬底的中心部分减薄到初始厚度的至少四分之三或更小。在一些实施方式中，从衬底的背面形成IPD中的TSV包括衬底的干法蚀刻和绝缘体材料的蚀刻以暴露嵌入在绝缘体材料中的所述至少一个无源部件的端子。
在一些实施方式中，该方法包括将衬底的外圆周上的机械支撑环磨削到降低的高度。在一些实施方式中，从衬底的背面形成IPD中的TSV包括蚀刻渐缩TSV，并且渐缩TSV可具有从较宽的表面开口向较窄的TSV底部倾斜的渐缩壁。
在一些实施方式中，从衬底的背面形成IPD中的TSV包括在衬底的背面上以及沿着TSV的渐缩壁并在TSV底部上在TSV中镀覆铜层，经镀覆的铜层可限定对嵌入在绝缘体材料中的所述至少一个无源部件的端子的电连接。在一些实施方式中，在衬底的背面上以及沿着渐缩壁并在TSV底部上在TSV中镀覆铜层包括在衬底的背面上以及沿着渐缩壁在TSV中沉积钛 -铜(Ti-Cu)阻挡层和晶种层。在一些实施方式中，所述在衬底的背面上以及沿着渐缩壁并在TSV底部上在TSV中镀覆铜层包括在衬底的背面上生长氧化物层，然后镀覆铜层。
在一些实施方式中，该方法可包括将凸块下金属(UBM)蚀刻施加到铜层。在一些实施方式中，该方法可包括形成阻焊层，并且形成与铜层接触的晶圆凸块或焊球。在一些实施方式中，该方法可包括将切分胶带附连到衬底，将衬底切分成单独IPD管芯，以及从切分胶带拾取单独IPD管芯。
在至少一个一般方面，电子电路封装可包括其上具有导电垫的板，以及耦接到导电垫的集成无源器件(IPD)管芯。IPD管芯可包括至少一个无源部件和贯穿衬底通孔(TSV)，该至少一个无源部件嵌入在设置于衬底的前表面上的绝缘体材料中，该贯穿衬底通孔从半导体衬底的背面朝衬底的前表面延伸。IPD管芯可包括铜层，该铜层设置在衬底的背面上以及TSV中。铜层可限定从板上的导电垫到穿过TSV嵌入在绝缘体材料中的所述至少一个无源部件的端子的电连接。
在一些实施方式中，IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到导电垫。在一些实施方式中，衬底是51mm直径硅晶圆、76mm直径硅晶圆、125mm硅晶圆、150mm直径硅晶圆、200mm直径硅晶圆或 300mm直径硅晶圆中的一者。
还应当理解，当元件(诸如电阻器、或电容器、或电感器、或其他 IPD部件)被提及为在另一个元件上、连接到另一个元件、电连接到另一个元件、耦接到另一个元件、或电耦接到另一个元件时，该元件可直接在另一个元件上、连接另一个元件、或耦接到另一个元件，或可存在一个或多个中间元件。相反，当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时，不存在中间元件或层。虽然在整个详细描述中可能不会通篇使用术语直接在...上、直接连接到...、或直接耦接到...，但是被示为直接在元件上、直接连接或直接耦接的元件可以此类方式提及。本申请的权利要求(如果包括的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书中所使用的，除非根据上下文明确地指出特定情况，否则单数形式可包括复数形式。除了附图中所示的取向之外，空间相对术语 (例如，在...上方、在...上面、在...之上、在...下方、在...下面、在...以下、在...之下等等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中，在...之上和在...之下的相对术语可分别包括竖直地在...之上和竖直地在...之下。在一些实施方式中，术语邻近可包括横向邻近或水平邻近。
本文所述的各种技术的实施方式可在数字电子电路中、计算机硬件、固件、软件中或它们的组合中实现(例如，包括在其中)。方法的部分也可通过专用逻辑电路例如FPGA(现场可编程门阵列)或ASIC(专用集成电路)进行，并且装置可实现为该专用逻辑电路。
可在计算系统中实现实施方式，该计算系统包括工业电机驱动器、太阳能逆变器、镇流器、通用半桥拓扑结构、辅助和/或牵引电机逆变器驱动器、开关模式电源、车载充电器、不间断电源(UPS)、后端部件(例如，作为数据服务器)，或者包括中间件部件(例如，应用服务器)，或者包括前端部件(例如，具有用户可通过其与实施方式进行交互的图形用户界面或Web浏览器的客户端计算机)，或者包括此类后端、中间件或前端部件的任何组合。部件可通过任何形式或介质的数字数据通信(例如，通信网络)互连。通信网络的示例包括局域网(LAN)和广域网(WAN)，例如互联网。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明，但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此，应当理解，权利要求(如果附加的话)旨在涵盖落入实施方式的范围内的所有此类修改形式和变化形式。应当理解，这些修改形式和变化形式仅仅以示例的方式呈现，而不是限制，并且可以进行形式和细节上的各种改变。除了相互排斥的组合以外，本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式可包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (10)

1.一种集成无源器件IPD管芯，包括：
具有背面和正面的衬底，所述衬底具有磨削到小于初始的衬底的厚度的四分之三的厚度；
绝缘体材料层，所述绝缘体材料层设置在所述衬底的正面上；
无源器件，所述无源器件包括电感器、电阻器和电容器中的至少一个，所述无源器件被所述绝缘体材料层完全包围，
所述无源器件具有设置在暴露端子和另一端子之间的器件结构；和
贯穿衬底通孔TSV，所述贯穿衬底通孔从所述衬底的背面朝所述衬底的正面表面延伸到所述绝缘体材料层中的绝缘体材料腔中，所述绝缘体材料腔暴露由所述绝缘体材料层完全包围的无源器件的端子，所述TSV限定通向由设置在所述衬底的正面上的绝缘体材料层完全包围的无源器件的暴露端子的互连通路。
2.根据权利要求1所述的IPD管芯，其中所述TSV是渐缩TSV，所述渐缩TSV具有渐缩壁，所述渐缩壁从较宽的表面开口向较窄的TSV底部倾斜。
3.根据权利要求2所述的IPD管芯，还包括：铜层，所述铜层设置在所述衬底的所述背面上以及沿着所述渐缩壁并在所述TSV底部上设置在所述TSV中，所述铜层限定对嵌入在所述绝缘体材料中的所述无源器件的端子的电连接。
4.如权利要求3所述的IPD管芯，还包括：
阻焊层；和，
晶圆凸块，所述晶圆凸块与所述铜层接触。
5.根据权利要求1所述的IPD管芯，其中所述器件结构包括以下中的至少一个：
电感器的感应导线或线结构，
电阻器的电阻材料垫，和
电容器的电容器间隙材料垫。
6.根据权利要求1所述的IPD管芯，其中所述TSV是干法蚀刻的。
7.根据权利要求1所述的IPD管芯，其中所述IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到包括在板上的导电垫。
8.一种集成无源器件IPD管芯，包括：
至少一个无源部件，所述至少一个无源部件完全嵌入在设置在衬底的正面上的绝缘体材料层中；
贯穿衬底通孔TSV，从所述衬底的背面朝所述衬底的正面延伸；以及
铜层，所述铜层设置在所述衬底的背面上以及所述TSV中，
所述铜层限定穿过所述TSV的对完全嵌入在所述绝缘体材料中的所述至少一个无源部件的端子的电连接。
9.根据权利要求8所述的IPD管芯，其中所述衬底具有小于所述衬底的初始厚度的四分之三的厚度。
10.根据权利要求8所述的IPD管芯，其中所述IPD管芯使用导电环氧树脂或使用晶圆凸块焊料耦接到包括在板上的导电垫。
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