TW201019440A - Bumped chip and semiconductor flip-chip device applied from the same - Google Patents

Bumped chip and semiconductor flip-chip device applied from the same Download PDF

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Publication number
TW201019440A
TW201019440A TW097142422A TW97142422A TW201019440A TW 201019440 A TW201019440 A TW 201019440A TW 097142422 A TW097142422 A TW 097142422A TW 97142422 A TW97142422 A TW 97142422A TW 201019440 A TW201019440 A TW 201019440A
Authority
TW
Taiwan
Prior art keywords
silver
bumps
wafer structure
layer
bumped wafer
Prior art date
Application number
TW097142422A
Other languages
English (en)
Inventor
Chih-Wen Ho
Yung-Fa Huang
Ming-Kuo Wei
Po-Chien Lee
Original Assignee
Int Semiconductor Tech Ltd
Gold Jet Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Semiconductor Tech Ltd, Gold Jet Technology Inc filed Critical Int Semiconductor Tech Ltd
Priority to TW097142422A priority Critical patent/TW201019440A/zh
Priority to US12/582,285 priority patent/US20100109159A1/en
Publication of TW201019440A publication Critical patent/TW201019440A/zh

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Description

201019440 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種凸 塊化晶片結構及其應用之半導體覆晶裝置。 【先前技術】 覆晶接合技術.（flip-chip bonding technology)是將 晶片之主動面的銲墊上設置複數個導電凸塊（或稱為
突出狀電極），藉由晶片翻轉方式接合到基板以完成電 性連接。相較於使用打線連接（wire bond)之電性連接 方式’提供了晶片至基板之較短電性連接路徑與適用 於咼密度輸出/入接點數量之產品製造，具有良好的高 頻訊號的傳輸品質。 然而導電凸塊接合在晶片與基板之間係為覆晶間 隙内的點對點結合，一旦受到熱應力與基板翹曲變形 會導致凸塊斷裂，進而造成晶片與基板之間電氣訊 號傳遞失敗。 目月】的覆晶接合技術可分為兩大帛，一《使錫錯凸 ，回焊成球形，但錫錯凸塊*符合無錯化要求，並且 回焊的高溫下錫船凸塊不具有維持覆晶間隙的功 F;距的：的錫鉛凸塊容易產生焊料橋接，+適用於微 ::::Γ。另—是使用金凸塊—合 基板。雖然其可靠性膠電性連接至 接短路問題，彳Α 不會有回焊成球狀的橋 θ凸塊的材料成本過高，仍亟需發展 5 201019440 · · 同等級品質的替代凸塊。 近來，有人提出一種亦有使用低成本的導電凸塊來 取代金塊’導電凸塊的全部或是下半部選用較硬的銅 為材料，簡稱為銅凸塊。然而銅λ塊因.其較硬之材質 相對使得柔軟度較差，施加於銅凸塊的應力會直接傳 遞到銅凸塊與晶片金屬墊的接合界面，導致銅凸塊的 底部斷裂或是造成晶片受損。特別在多個凸塊無法控 制相當準確的等高或是基板與晶片之間的覆晶間隙為 ❹ 非一致（例如基板翹曲變形時）的狀況時，銅凸塊的底 部斷裂問題會變得更嚴重。此外，銅容易氧化，在凸 塊製程必須保持在還原氣氛，並在凸塊製成之後另作 防氧化的保護’製程限制頗多，並不能有效降低凸塊 的製造成本。 【發明内容】 有鑒於此’本發明之主要目的係在於提供一種凸塊 φ 化晶片結構’能在不會影響柱狀凸塊的性能與品質下， 取代習知的金凸塊，更優於習知的銅凸塊，不會有銅凸 塊的底部斷裂問題，藉以符合無鉛化、高可靠度與低成本 之凸塊要求。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種凸塊化晶片結 構’主要包含一晶片、一或一個以上凸塊承座、一或一個 以上銀凸塊以及一或一個以上抗潛變層。該晶片係具有一 或一個以上薛塾以及一保護層，該保護層係覆蓋於該晶 201019440 片之一表面上並具有一或一個以上開孔，以顯露該些銲 墊。該些凸塊承座係設於該些銲墊上並覆蓋該保護層之 該些開孔之周邊。該些銀凸塊係呈柱狀並設置於該些凸 塊承座上’每一銀凸塊係具有一頂面以及一柱側壁❶該 些抗潛變層係包覆該些銀凸塊之頂面與柱侧壁。在不同 實施例中，該些抗潛變層亦可僅包覆該些銀凸塊之柱側 壁’該些銀凸塊或可直接設置於該些銲墊。 ❹ 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述凸塊化晶片結構中，該些銀凸塊之材質係可選 自於純銀或銀合金。 在前述凸塊化晶片結構中，該些銀凸塊之銀合金係可 包含不小於80%的銀含量。 在前述凸塊化晶片結構中，該些凸塊承座係可包含一 黏著層以及一潤濕層，該黏著層係貼附於該些銲墊，該潤濕 % 層係貼附於該黏著層。 在前述凸塊化晶片結構中，該些抗潛變層之材質係可 包含金，使其具有抗氧化與高導電之特性。 在前述凸塊化晶片結構中，該些凸塊承座係具有不被 該』銀凸塊覆蓋之側緣，而該些抗潛變層係可更延伸覆蓋至 該些凸塊承座之上述側緣。 在前述凸塊化晶片結構中，該些銀凸塊之外形係可選 自圓柱體、方柱體以及長條形體之一。 在别述凸塊化晶片結構中，該些銀凸塊之高度係可介 201019440 於 5μηι 到 25μιη。 ，該些抗潛變層之厚度係可 ，該些銀凸塊之頂面與柱側 在前述凸塊化晶片結$ + 介於 0·03μπι 到 3μπι。 在前述凸塊化晶片、结構 壁之間可為有角度彎曲。
在前述凸塊化晶片、结 不高於該些銀凸塊之硬度。 本發明另揭示運用前述^ & 體覆晶裝置，另包含一基板，其 數個連接墊’該些銀凸塊係經由 板之該些連接墊。 ，該些抗潛變層之硬度係可 塊化晶片結構的一種半導 中該基板之一表面係設有複 該抗潛變層電性連接至該基 由以上技術方案可以砉山 丄# 構 ❹ 有出’本發明之凸塊化晶片結 ’有以下優點與功效： 一、在柱狀凸塊的領域中， 選用銀凸塊取代習知的金凸 塊或銅凸塊’產生如回 邪叫金凸塊不致過硬的硬度，以 優於習知的銅凸塊，故T A > h ^ 敌不會有銅凸塊的底部斷裂問 題，藉以符合無鉛化、古-Γ^ 阿可靠度與低成本之凸塊要求。 此外，利用在銀凸壤表而 及衣面的抗潛變層包覆效果，避免 銀凸塊在應力下產生潛變的緩慢變形現象。 利用銀凸塊及在其表面之抗潛變層使凸塊在高溫 下不會產生覆晶間隙變化。 利用在銀凸塊表面之於、瓶谢β 抗潛變層更延伸覆蓋至凸塊承座 之外露側緣’錢銀凸塊為全包覆型態，*會在覆晶 接合之後在銀凸壤枝側壁的底部產生抗潛變層的 8 ❹
201019440 朋裂’藉以增進該抗潛變層的抗潛變作用 低銀凸塊的潛變發生。 【實施方式】 以下將配合所附圖* 應注意的是’該些囷示均為簡化之示意圖，僅 法來說明本發明之基本架構或實施方法，故僅 案有關之兀件，且所顯示之元件並非以實際 目、形狀、尺寸比料製，某些尺寸比例與其 寸比例已經被修飾放大或是簡化以提供更 述，實際實施之數目、形狀及尺寸比例為一種 設計，且詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種凸塊 構舉例說明於第1圖之截面示意圖與第2A 5 製程中元件截面示意圖。 如第1圖所示’該凸塊化晶片結構1〇〇主 晶片110、一或一個以上凸塊承座12〇、一或 銀凸塊130以及一或一個以上抗潛變層14〇。 該晶片110係具有一或一個以上銲墊 護層（passivation layer)112，該保護層 112 係 晶片 之一表面113上並具有一或一個 114，以顯露該些鮮塾111。該晶片110係為 質，例如矽或是III-V族半導艎，該表面113 片110之主動面，可形成有積體電路元件，選 制器、微處理器、記憶艘、邏輯電路、特殊應 ，有效降 施例，然 以示意方 顯示與本 實施之數 他相關尺 清楚的描 選置性之 化晶片結 • 2F圖之 要包含一 一個以上 以及一保 覆蓋於該 以上開孔 半導髋材 即為該晶 自於微控 用積體電 9 201019440 路（例如顯示器驅動電路）等或上述的任意組合。該些銲 墊111係由金屬製成，例如鋁、銅以及其合金等，可作 為該晶片110訊號輸出入之端子。該保護層112係為電 絕緣性的表面層，或稱其為鈍化層，材質可為聚亞醯 胺、苯環丁烯（BCB)、磷矽玻璃（ph〇sph〇silicate glass)、 氧化矽（silicon oxide)、氮化矽（siHc〇n nitride)或氮化物 (nitride)，可藉由化學氣相沉積（CVD)技術所形成，能 • 提供保護該表面113上之積體電路元件並使該表面U3 更為平坦。在本實施例中，該保護層丨丨2之開孔丨丨4係 可局部覆蓋該些銲墊111之周緣，即該些開孔114之尺 寸略小於該些銲墊111之尺寸。 如第1圖所示’該些凸塊承座12〇係設於該些銲墊 111上並覆蓋該保護層112之該些開孔114之周邊。該 些凸塊承座120係為塾狀的凸塊下金屬層（under bump metallurgy layer，UBM layer)，該些銲墊 111 係與該些 φ 凸塊承座120電性連接。具體而言，該些凸塊承座ΐ2〇 係可包含一黏著層（adhesion layer)121以及一潤濕層 (wetting lay er) 122，用以增進該些銀凸塊130與該些銲 墊111之間的連結。詳細而言，該黏著層121係貼附於 該些銲墊111，該潤濕層122係貼附於該黏著層121。 該黏著層121可以提供該些銲墊111及該保護層112良 好的黏著性，其材質可為鈦（Ti)或鎢化鈦（TiW)。該潤濕 層122係提供與該些銀凸塊130良好的沾附性，其材質 可·為金等。該黏著層1 2 1與該潤濕層1 22係可以濺鍍方 10 201019440 式形成。通常該些凸塊承座120係大於該保護層112之 開孔114，以延伸至該保護層112之對應開孔ιι4之周 緣’而具有形成在該保護層112上的外露侧緣123。 如第1圖所示，該些銀凸塊130係呈柱狀並設置於 該些凸塊承座120上，每一銀凸塊13〇係具有一頂面 131以及一柱側壁132。通常該些銀凸塊13〇之頂面131 與柱侧壁132之間可為有角度彎曲，例如約9〇度❶關 眷於該些銀凸塊130的柱狀型態，該些銀凸塊〗3〇的高度 可大於該些銀凸塊130的底部面積之一直徑或一寬 度。該些銀凸塊130之高度係可介於5μιη(微米）到 2 5卜111(微米）。詳細而言，該些銀凸塊13〇之材質係可選 自於純銀或銀合金》當為銀合金時，該些銀凸塊13〇之 銀合金係可包含不小於80%的銀含量。因此，該些銀凸 塊130具有大約與習知金凸塊相同但低於鋼凸塊的硬 度，並且導電性與金屬延伸性良好。故該些銀凸塊13〇 〇 之成本相較於習知之金凸塊具有較低之成本，並符合無 船化之要求，能在不會影響凸塊的性能與品質下，取代 習知的金凸塊，更優於習知的銅凸塊，不會有習知銅凸 塊的底部斷裂問題。 該些抗潛變層140係包覆該些銀凸塊之頂面131 與柱侧壁132。該些抗潛變層140之厚度係可介於〇〇3μπ1 到3μπι。在一具體實施例中，該些抗潛變層14〇之厚度係 約為Ιμιη。相對於該些銀凸塊的高度，該些抗潛變層ι4〇 係為一表面覆蓋之薄層。該些抗潛變層14〇之材質係可 11 201019440 包含金’例如純金或金合金（goldalloy)，使其具有抗氧 化與高導電之特性。此外，該些抗潛變層140之硬度係可 不高於該些銀凸塊130之硬度，以不影響或改變整體凸塊的 結構強度。 一般來說’材料在常溫下，受到彈性限度以下之應 力長時間作用時，其間並不發生變化。但在高溫環境 下，受到較彈性限度低之應力作用時，材料會隨著時間 漸漸地發生變形，此一現象稱之為潛變（creep) 〇由於銀 ❿ 凸塊的潛變現象會高於金凸塊與銅凸塊，故本發明必須 利用在該些銀凸塊130表面的抗潛變層140的包覆效果， 特別是包覆該些銀凸塊130的柱側壁132，避免該些銀凸 塊130在應力下產生潛變的緩慢變形現象，防止該些銀 凸塊13 0往側向變胖的變形，以維持覆晶間隙與有效 接合。 較佳地’該些凸塊承座120係具有不被該些銀凸塊 ❹ 130覆蓋之側緣123’而該些抗潛變層140係可更延伸 覆蓋至該些凸塊承座120之上述侧緣123，故該些抗潛 變層140為完全包覆該些銀凸塊13〇與該些凸塊承座 120，以使該些銀凸塊130與該些凸塊承座uo無顯露 於大氣環境的表面。故在一較佳實施例中，該些銀凸塊 130為全包覆型態，不會在覆晶接合之後在該些銀凸塊 130之柱側壁132的底部產生該些抗潛變層140的崩 裂，藉以增進該些抗潛變層140的抗潛變作用，有效降 低該些銀凸塊130的潛變發生。 12 201019440 請參閱第2A至2F圖所示，本發明進一步說明該a 塊化晶片結構100之製造方法，以彰顯本案的功效° 首先，如第2A圖所示，提供一晶片11〇’多個晶片 110在該步驟中可構成於一晶圓，該晶片110係具有一 或一個以上銲墊111以及一保護層112，該保護層I12 係覆蓋於該晶片110之一表面113上並具有一或一個以 上開孔11 4，以顯露該些銲墊1丨i。 接著’如第2B圖所示，形成包含一或一個以上凸塊 承座120的凸塊下金屬層於該些鲜塾上並覆蓋該保 護層112。該凸塊下金屬層係可包含一黏著層121以及 潤濕層I22，且可藉由已知半導體製程之沉積技術形 成，例如濺鍍（sputtering)。包含該些凸塊承座12〇之該 凸塊下金屬層係覆蓋暴露出之銲墊lu以及整面的保 護層112。 之後’如第2C圖所示，形成—圖案化遮罩，例如一 ® j阻層1〇形成於該凸塊下金屬層之外表面。一般而 言’該光阻層10可選自液態光 〜尤阻或乾膜光阻，接著ϋ 行一曝光顯影製程，形成複數個開 间孔11，以相對應地 曝露出各銲墊ill上方預定形成該 <&凸塊承座120之位 置。該些開孔1 1係提供作為銀凸塊 , 吸1“與凸塊承座12 之形成區域。在本實施例中，該此 Λ -開孔11係大於對應 位置之該些銲墊U1。或者，不受 又限地，該些開孔1 亦可形成於該些銲墊1U之外，龙 亚配合RDL(重配置鱗 路層）製程中因接點配置設計上的絷 ^需要而需變更接點纪 13 201019440 位置。 接著’如第2D圖所示，在該些開孔11内以電艘 (electroplating)方式形成複數個銀凸塊13〇。該些銀凸 塊130係接合於包含該些凸塊承座120之凸塊下金屬層 上。 接著，如第2E圖所示，移除該光阻層1〇，以使得 該凸塊下金屬層中不包含該些凸塊承座120的部位為 外露。接著，如第2F圖所示，可以蝕刻方式移除部分 之該黏著層121以及該爛漁層122，以形成該些凸塊承 座120’其尺寸係可由該些銀凸塊130的底部覆蓋面積 所界定’並形成上述之侧緣123。故該些銀凸塊130之 該些柱侧壁132係與該些凸塊承座120之側緣123切 齊。 最後，如第1圖所示’形成一或一個以上抗潛變層 140來包覆該些銀凸塊130之頂面131與柱側壁132。 φ 該些抗潛變層140可藉由置換金、電鍍或化學鍍方法形 成。利用抗、潛變層140包覆銀凸塊130，能避免該些銀 凸塊130產生潛變現象。 具體而言’如第3A至3C圖所示，該些銀凸塊13〇 之外形係可選自方柱體、圓柱體以及長條形體之一。但 不受限制地’亦可為各種形狀之多角柱體。每一銀凸塊 130、130’、130’’係具有一頂面 131、131’、131，’以及 一柱侧壁132、132’、132’’。較佳地’該些銀凸塊13〇 形狀係為正四面體結構（tetragonal)，即四方體之上下表 14 201019440 面與側面垂直，具有一定穩定性，可達到耐潛變性能之 提高。該些頂面131、131’、131’’與對應之柱侧壁132、 132’、132”之間係為有角度彎折。 請參閱第4圖所示，為該凸塊化晶片結構100運用 於一半導體覆晶裝置之截面示意圖。該凸塊化晶片結 構100係覆晶接合至一基板20，具有縮短的電傳遞路 徑，以提南晶片之效能。 如第4圖所示，該半導體覆晶裝置主要包含該凸塊 化晶片結構100以及該基板20，其中該基板20之一表 面21係設有複數個連接墊22，該基板20係可為一種 玻璃基板或可為高密度雙面導通之多層印刷電路板，内 部形成有導電跡線（conductive trace)。該些銀凸塊130 係經由該抗潛變層14〇電性連接至該基板20之該些連 接墊22°即該抗潛變層i4〇係壓焊接合至該些連接墊 22 ’便使該晶片1丨〇與該基板3 〇達到電性連接β該些 ❹ 銀凸塊130經由該抗潛變層140電性連接至該基板20 之該些達:接塾22的接合方法係可選用超音波鍵合或熱 壓合°即使在高溫下，覆蓋該些柱側壁1 32的該抗潛變 層140可保護該銀凸塊130不會產生受到應力的潛變。 較佳地’該基板20係可為一玻璃基板，當該凸塊化晶 片結構100在覆晶接合於該基板之後，可由該基板 20的另表面（相對於該表面21之相反表面）透過該基 板2〇目視《光學檢測覆蓋在該些銀Λ塊130表面的抗 潛變層140是否有豳 $崩裂的現象。 15 201019440 更細部而言，如第丨與4圖所示，該半導體覆晶裝 置可另包含有一底部填充膠（underfill)30，其係形成於 該凸塊化晶片結構丨00與該基板20之間的覆晶縫隙 間’以包覆位在該些銀凸塊1 30之柱侧壁1 32之該些抗 潛變層140。該底部填充膠30係可以先點塗畫在該晶 片11 0之一側邊或兩側邊，並利用毛細現象填滿上述覆 晶缝隙，再予以固化處理，用以保護該些銀凸塊1 3〇與 該些抗潛變層140。 翁 請參閱第5圖所示，為該凸塊化晶片結構ι〇〇運用 於另一半導體覆晶裝置之截面示意圖。 在本實施例中，該凸塊化晶片結構1 〇 0可藉由一異 方性導電膠（Anisotropic Conductive Paste, ACP)40 與該 基板20電性連接。該異方性導電膠4〇係可藉由印刷、 黏貼等方式先形成於該基板20上’再使該凸塊化晶片 結構100覆晶接合至該基板20。該異方性導電膠4〇係 φ 包含複數個導電粒子41，部分之該些導電粒子41係電 性接觸該抗潛變層14〇與該些連接墊22而達成縱向導 電之功效。該些導電粒子41係為等球徑，其直徑大小 可是介於2μηι至3 μιη之間，該些導電粒子41係均勻分 散在該異方性導電膠40内’以達到縱向的異方性導 電。即該些抗潛變層140與該些連接墊22之間係被部 分之該些導電粒子41電性接觸’以使該基板2〇與該晶 片110達到縱向的電性連通，亦不會有直接焊接導致金 屬擴散（metal diffusion)的問題，也能減少覆晶接合的 16 201019440 應力產生。 依據本發明之第二具體實施例，另一種凸塊化晶片 結構舉例說明於第6圖之截面示意圖◦該凸塊化晶片結 構200主要包括一晶片110、一或一個以上銀凸塊13〇 以及一或一個以上抗濟變層140。其中與第一實施例相 同的主要元件將以相同符號標示，故可以理解亦具有相 同功能並能達成上述功效，不再詳予資述。 0 在本實施例中，該凸塊化晶片結構2 〇 〇可省略該些 凸塊承座120之元件製作’以減少製程成本。該些銀凸 塊130可直接形成在該些銲墊1丨丨上，但該些抗潛變層 140仍必須包覆該些銀凸塊13〇之柱側壁132。此外， 該凸塊化晶片結構200可另包含一或一個以上銲料 250,設置於該些柱狀銀凸塊13〇之頂面131。在覆晶 接合時，經熱壓合之高溫以使該些銲料25〇與一基板之 連接墊接合，以形成電性藕接與機械結合關係。通常該 •些銲料250係可選用無船銲劑為較佳’以錫96·5%_銀 3/〇-銅〇.5%之銲料為例，在到達溫度約攝氏217度以 上’最高溫約為攝氏245度時便能產生焊接之濕潤性， 而且該些銀凸塊13〇與該些抗潛變層14〇則必須具有高 於上述加熱溫度之溶點。 依據本發明之第三具體實施例，另一種凸塊化晶片 結構舉例說明於第7圖之截面示意圖。該凸塊化晶片結 構300主要包括—晶片110、一或一個以上銀凸塊13〇 以及一或一個以上抗潛變層14〇 »其中與第一實施例相 17 201019440 同的主要元件將以相同符號標示，不再詳予赘述。 在本實施例中’該凸塊化晶片結構300可另包含一 或一個以上保銲劑350’設置於該些柱狀銀凸塊130之 頂面131。該些保銲劑350係可包括無機函化物及有機 齒化物二大類。該些保銲劑350具有耐高溫抗氧化性 月f，在覆晶接合之後具有優良的銲接性（s〇lderabiHty) 且厚度均一。 潛變層 溫下不 高可靠 用於半 並非對 較隹實 何熟悉 所作的 本發明 ❿ ❹ 總而言之，本發明之凸塊化晶片結構利用抗 包覆銀凸塊’能避免銀凸塊之潛變發生，故在高 會產生覆晶間隙變化的問題，更可符合無鉛化、 度與低成本之凸塊要求。因此’銀凸塊可具體應 導體晶片上的杈狀凸塊。 以上所述，僅是本發明的較佳實施例而已， 本發明作任何形+ μ & ^ Μ 小式上的限制，雖然本發明已以 施例揭露如上，然而並非用以限定本發明，任 本項技術者，為 在不脫離本發明之技術範圍内， 任何簡單修改、莖祕叫嫩 等效性變化與修飾，均仍屬於 的技術範圍内。 、 【圖式簡單說明】 第1圖：依據本發明之笛 a ^ 曰个赞月之第一具體實施例的一種凸塊化 晶片結構之局部截面示意圖。 第2A至2F圖：依據本發明之第一具體實施例的凸塊 b晶片結構在製程中元件的截面示意圖。 第3A至3C圖：麻祕丄於 本發明之第一具體實施例的凸塊 18 201019440 化晶片結構之銀凸塊不同變化例之立體示意 圖。 第4圖：依據本發明之第一具體實施例的一種凸塊化 晶片結構運用於一半導體覆晶裝置之截面示 意圖。 第5圖：依據本發明之第一具體實施例的一種凸塊化 晶片結構運用於另一半導體覆晶裝置之截面 示意圖。 第0圖：依據本發明之第二具體實施例的另一種凸塊 化晶片結構之局部截面示意圖。 第7圖：依據本發明之第三具體實施例的另一種凸塊 化晶片結構之局部截面示意圖。 【主要元件符號說明】 10 光阻層 11 開孔 20 基板 21 表面 22 連接墊 30 底部填充膠 40 異方性導電膠 41 導電粒子 100 凸塊化晶片結構 110 晶片 111 銲墊 112 保護層 113 表面 114 開孔 120 凸塊承座 121 黏著層 122 潤濕層 123 侧緣 130 銀凸塊 131 頂面 132 柱侧壁 130, 銀凸塊 131， 頂面 132, 柱側壁 19 201019440 130”銀凸塊 131”頂面 140抗潛變層 250銲料 350保銲劑 132，， 柱侧壁
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Claims (1)

  1. 201019440 十、申請專利範困： 1、 一種凸塊化晶片結構，包括： 一晶片，係具有一或一個以上銲墊以及一保護層，該保 護層係覆蓋於該晶片之一表面上並具有一或一個以上開 孔，以顯露該些銲墊； 一或一個以上凸塊承座，係設於該些銲墊上並覆蓋該保 護層之該些開孔之周邊； 參 一或一個以上銀凸塊（Ag bump) ’係呈柱狀並設置於該些 凸塊承座上，每一銀凸塊係具有一頂面以及一柱側壁； 以及 一或一個以上抗潛變層（creeping-resist layer)，係包覆該 些銀凸塊之頂面與柱侧壁。 2、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些銀凸塊之材質係選自於純銀或銀合金。 3、 如申請專利範圍第2項所述之凸塊化晶片結構，其中該 φ 些銀凸塊之銀合金係包含不小於80%的銀含量。 4、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些凸塊承座係包含一黏著層以及一潤濕層，該黏著層係 貼附於該些銲墊，該潤濕層係貼附於該黏著層。 5、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些抗潛變層之材質係包含金，使其具有抗氧化與高導電 之特性。 6、 如申請專利範圍第丨項所述之凸塊化晶片結構，其中該 些凸塊承座係具有不被該些銀凸塊覆蓋之側緣，而該此 21 201019440 抗潜變層係更延伸覆蓋至該些凸塊承座之上述侧緣。 7、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些銀凸塊之外形係選自圓柱艎、方柱體以及長條形體之 —· 〇 8、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些銀凸塊之高度係介於5μιη到25μηι。 9、 如申請專利範圍第1項所述之凸塊化晶片結構，其中該 些抗潛變層之厚度係介於0·03μιη到3μιη。 10、 如申請專利範圍第1項所述之凸塊化晶片結構，其中 該些銀凸塊之頂面與柱側壁之間為有角度彎曲。 11、 如申請專利範圍第丨項所述之凸塊化晶片結構，其中 該些抗潛變層之硬度係不高於該些銀凸塊之硬度。 12、 一種凸塊化晶片結構，包括： 一晶片’係具有一或一個以上銲墊以及一保護層，該保 護層係覆蓋於該晶片之一表面上並具有一或一個以上開 孔’以顯露該些銲墊； 一或一個以上銀凸塊（Ag bump)，係呈柱狀並設置於該些 銲塾上，每一銀凸塊係具有一頂面以及一柱側壁；以及 一或一個以上抗潛變層（creeping_resist layer)，係包覆該 些銀凸塊之柱側壁。 13、 如申請專利範圍第12項所述之凸塊化晶片結構另包 含一或一個以上銲料，設置於該些柱狀銀凸塊之頂面。 14、 如申請專利範圍第12項所述之凸塊化晶片結構，另包 含一或一個以上保銲劑，設置於該些柱狀銀凸塊之頂面。 22 201019440 15、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 該些銀凸塊之材質係選自於純銀或銀合金。 16、 如申請專利範圍第12項所述之凸塊化晶片結構其中 該些銀凸塊之銀合金係包含不小於80%的銀含量。 17、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 該些抗潛變層之材質係包含金，使其具有抗氧化與高導 電之特性。 $ 18、如申請專利範圍第12項所述之凸塊化晶片結構，其中 該些銀凸塊之外形係選自圓柱體、方柱體以及長條形艘 之一。 19、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 該些銀凸塊之高度係介於5 μιη到2 5 μηι。 20、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 該些抗潛變層之厚度係介於〇.〇3μιη到3μιη。 21、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 ❿ 該些銀凸塊之頂面與柱侧壁之間為有角度彎曲。 22、 如申請專利範圍第12項所述之凸塊化晶片結構，其中 其中該些抗潛變層之硬度係不高於該些銀凸塊之硬度。 23、 如申請專利範圍第12項所述之凸塊化晶片結構，另包 含一或一個以上凸塊承座’係設於該些銲墊與該些銀凸 塊之間並覆蓋該保護層之該些開孔之周邊，並且該些凸 塊承座係具有不被該些銀凸塊覆蓋之侧緣，而該些抗潛 變層係更延伸覆蓋至該些凸塊承座之上述側緣。 24、 一種半導體覆晶裝置’主要包含如申請專利範圍第1 23 201019440 項之凸塊化晶片結構以及一基板，其中該基板之一表面 係設有複數個連接墊，該些銀凸塊係經由該抗潛變層電 性連接至該基板之該些連接墊。 25、 如申請專利範圍第24項所述之半導體覆晶裝置，其中 該抗潛變層係壓焊接合至該些連接墊。 26、 如申請專利範圍第24項所述之半導體覆晶裝置，另包 含有一底部填充膠，其係形成於該凸塊化晶片結構與該 馨 基板之間’以包覆位在該些銀凸塊之柱側壁之該些抗潛 變層® 27、 如申請專利範圍第24項所述之半導體覆晶裝置，另包 含有一異方性導電膠，其係形成於該凸塊化晶片結構與 該基板之間，該異方性導電膠係包含複數個導電粒子， 部分之該些導電粒子係電性接觸該抗潛變層與該些連接 塾。 28、 如申請專利範圍第24項所述之半導體覆晶裝置，其中 ❿ 該基板係為一玻璃基板。 24
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