TW200949958A - Method of manufacturing semiconductor device for providing improved isolation between contact and cell gate electrode - Google Patents
Method of manufacturing semiconductor device for providing improved isolation between contact and cell gate electrode Download PDFInfo
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- TW200949958A TW200949958A TW098109494A TW98109494A TW200949958A TW 200949958 A TW200949958 A TW 200949958A TW 098109494 A TW098109494 A TW 098109494A TW 98109494 A TW98109494 A TW 98109494A TW 200949958 A TW200949958 A TW 200949958A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000002955 isolation Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 5
- 230000008859 change Effects 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract description 3
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 20
- 239000010410 layer Substances 0.000 description 11
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000011859 microparticle Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000010419 fine particle Substances 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000238631 Hexapoda Species 0.000 description 1
- 235000006040 Prunus persica var persica Nutrition 0.000 description 1
- 240000006413 Prunus persica var. persica Species 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- HPQRSQFZILKRDH-UHFFFAOYSA-M chloro(trimethyl)plumbane Chemical compound C[Pb](C)(C)Cl HPQRSQFZILKRDH-UHFFFAOYSA-M 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
200949958 六、發明說明: 【發明所屬之技術領域】 本發明係關於半導體裝置的製造方法,尤有關於例如動態隨 機存取記憶體(DRAM ’ dynamic random access memory)及虛擬靜態 隨機存取記憶體(SRAM,static random access memory)之半導體記 憶裝置之記憶單元接觸部之形成技術。 【先前技術】 ❹ 近來’尺寸減小已在例如DRAMs(其在每一記憶單元中包含 了電晶體及一電容器)及虛擬SRAMs(其具有與DRAMs相同之單 兀結構)之記憶裝置中獲得進展。尺寸減小提供了增加的記憶容 量’且同時因為良率提升而降低了晶片成本。 錄· Ϊ而/半導體5己憶單元的尺寸減小卻伴隨而來非期望的困 .f人很難在各記憶單元内之閘電極及單元接觸部之間提供空 技術題,已知*法之一产使用自我對準Malign)接觸部 雷^:早疋接觸部係在將單元接觸部尺寸調整成等於鄰接閘 電極之_距離之情況下,關關電極自我對準。 文件以下秘由本發日狀之關於本發明之搜尋所發現之先前技術 ❹ 曰本公開專利公報第JP-A 2000-269458號, 曰本公開專利公報第JP-A2〇〇7_〇6725〇號, 日本公開專利公報第1993-343669號, 曰f公開,利公報第1994-021089號。 米的等級)的3固的問極長度減小至小於四分之一微 粒子會作用如軸彳喊綱之微小粒子生。微小 (skirt-like)钮刻殘留而導致在鄰近閘電極處產生類似裙部之 的單元接觸部轉裙f之侧雌可能直接接觸其後« 之間的短路⑽〇rt咖上?線f閘電極之間或電容電極與間電極 -個問題是:由微小2 會非期望地降低生產的良率。還有 粒子引起的缺陷需要以嚴苛條件施行用以偵 .200949958 測初始缺陷的產品篩選。 為了在f製次建構者(sub-constructor)之生產製程中達成高良 率及維持市場之兩可靠度,特別在基於系統級封裝(仰,吻她^
Package)及多晶片模組(MCM,刚行Chip M〇duie)之已知良品晶粒 fGD ’ Known GoodDie)業務的情況中’上述現象之抑制具有重 =1對付此問題的—目前使用方法為最佳化減少微小粒子之钱 讀件,然而’因為自動化缺陷偵測設備之偵測,在進一步之尺 HI、情況下將舰極限,因此f要進-步的發展來對付微小粒 子的問題。 〇 ❹ 後脖_ 1A至1H來提供微錄子問題之詳細說明。首 ,’ ^由使用溝渠(trench)隔離技術,將隔離氧化膜1〇2形成於p 之表面部分内;然後將閑氧化膜103形成在由隔離
及CVD氧化膜娜,來覆蓋Ρ财基H 廟m然,ί-,以光阻圖案作為遮罩1虫刻CVD氧化膜106,以形成如 1 =不的遮罩氧化膜107。再者,暖藉由以遮罩氧化膜1〇7 ίίΐί 應注意’在N+換雜頻104的触刻處理中,可』 曰產生微小粒子,且微小粒子會作用 + 局部地產生殘餘物109。 ^早曰娜頻104 然後’如圖1C所示,藉由使用單元閘電極 110 ° 化膜111之後㊉成層間介電質112,並隨後以化學機伽 f Mp^hemiealmeehaniealpGlishing_料桃,如 ^。k後,藉由使用光阻随作為鮮及使用第—氮化膜 ,為停止層(stopper)來爛層間介電質112,㈣成單雜觸孔1 ,如圖1E所不。再者,對第—氣u ❿5 自單元閑電㈣之侧面上之 200949958
Hint 吏電ϋ與摻雜石夕接觸部115發生短路,如圖IG^ ϊ極11V 電膜形成之後’形成了電容接觸部117、電容 電極118、電容介電質119、及雪交扨 电谷 ⑵可連接至單元接麻洞113。^ 1製以元成每-者皆包含一電晶體及一電容器的dram記憶單 與接。二’二U為單元閘電極108可能經由殘餘物109而 因、…及位元線接觸部121所構成)電連接, <電容了位元線122與單元㈣極⑽之間及/ 次電办電極118與早元閘電極1〇8之間之短路問題。 ❹ 【發明内容】 人.狀—實喊財,—種半_灯的製造方法,包 i ί成篦刻:匕積在半導體基板上之電導膜而形成複數個閘電 偏覆蓋閘電極;經由在第—氮倾上施行回 門的&理’岐半導縣板局部轉露在雜兩閘電極之 將殘留在鄰接兩閘電極之間的區域中之閘電極膜之 之=區中形=物改變成熱氧化膜;及在鄰接兩閉電極 在η明之另—實補樣中,—種轉體裝置,包含:一閉 鄰接二半導體基板上方並被一側壁所覆蓋;一接觸部, 观接側壁而械,以在半導縣板之擴散區域與設置於閘電極上 .200949958 方,二互連線路(interconnection)之間提供連接。在至少侧壁鄰接 於該半導體基板之-表面之—部分巾,㈣極與接卿係藉由絕 緣材料而絕緣,而絕緣材料係閘電極之材料之氧化物。 本發明有效地防止位元線與單元閘電極之間及/或電容電極盥 單元閘電極之間發生短路。 【實施方式】 現將參考例示性實施例來闡述本發明。熟習本技藝者當明 瞭矛]用本务明之教示可元成許多不同之實施例,且本發明不限 於解釋目的所述之實施例。 (第一實施例) 參照圖2A至2K,以下將提供本發明之第一實施例中之半導 體裝置之例木製造程序的說明。本實施例之製造程序開始於:使 用溝渠隔離技術,將具有0.25至〇·4〇μιη之深度之罐氧化膜2 ,成在Ρ型雜板丨之表面上。然後,以5至1Gnm之厚度將問 氧化膜3形成在被隔離氧傾2 _之侧活性區 序开f f摻雜賴4(厚度為W至心㈣、石夕化鶴厚度 0.1至0.15_)、及CVD氧化膜6(厚度為〇 2至〇
型石夕基板卜如圖2A所示。 卩;术復皿P ❹ 2B戶^ =光η阻f案作為遮罩侧㈣氧化膜6,以形成如圖 2B所不之具有〇.n至0·2μιη之遮罩氧化膜7。再者, 遮罩氧化膜7作為鮮依序侧魏顧 曰 形成多晶石夕化金屬㈣cide)結構之單元閘電極8得吾雜人夕膜主4音而 此製程會遭受以下問題:在N+摻雜频4的侧處’^產。 =^15阿之微小粒子可能有遮罩之作用,並局部地產生由 N摻雜矽所形成之殘餘物9。 擴==在形成覆蓋整個表*=== 亂化膜11之後’形成隨後其表面會以CMp技術作平坦化之層 200949958 ::::示。隨後,藉由使用光阻圖案作為遮罩 而形成具扣至〇.18 虫刻層間介電質12, 示。爯去,越由笛一 j開之单兀鋪孔洞13,如圖沈所 在單元接觸孔、、nn U之聰(etehbaek)而使? _基板1 在单疋接觸孔洞13中之部分曝露出來 14 換 時因為同蝕刻選擇比造成之第一氮化膜11 _^_N+ =?二4上_刻速率差異,故殘之部分4露出來
G ΐί⑯ί由涉及在例如溫度為85G〇C之電爐之乾燦空氣中進 =退火的”、、氧化技術’來形成具有10至2511111厚度之埶氧化 度較乂π程卜因為n+捧雜石夕殘_之電子濃 “幾乎所有』祕:=此N摻雜矽殘餘物9之氧化增強,而 =成手所有之殘餘物9轉變為氧化增強氧化膜24,如圖犯所
Q 祕ί後’形成具有30至80 nm厚度之第二氮化膜25以覆蓋整 =構,如圖2H所示。然後,藉由在第二氮化膜25上施行回^ =,可使P财基板1之部分曝露妹。_處理導致氧化姆 点膜Γ之尖端部分被移除’而形成覆蓋氧化膜27,以覆蓋; =自第-氮化膜25之側壁26與Ρ型石夕基板i之間的空 ν ij示。然後,、經由沉積覆蓋整個表面之^摻神膜並H圖 如圖2J所示。隨後,在另一層間介電質形成之^ ?電,8上方形成電容接觸部17、電容電極18、電容介 ^ =板20。然後,在形成另一層間介電質之後,在單元閘 方形成位το線22錢供紅線22與N+#_翻部 門 200949958 ‘異,本發明之第-實施例之製造程柯允钱乎 =形成之㈣物9藉由録化轉變絲 ^雜= :卜由覆蓋氧化增強氧化膜24之第二氮化膜25形==,= ,以側壁26及覆蓋氧化臈27使N、雜石夕接觸部15與單 = 8互相電絕緣。更明確地,單元閘電極8與N+推雜矽 在側壁26與P型石夕基板!之表面相接觸之區域°^ =斤隔離,其中該覆蓋氧化膜27係由用於單匕 f ”化物,成。如此可以有效地防止位元線22 g ❹ 8之間及/或電容電極18與單元閘電極8之間發生 (第二實施例) 道麟圖3A-至3K ’接下來將提供本發明之第二實施例中之丰 =裝置之例7F製造程序的說明。第—實施例係針對提供由Ν 雜石夕所械之局部殘留物9所造成之問題的够,兮’ T〇:s"' mii 4 至0.15 μηι之微小粒子而產生。 另一方面,第二實施例係針對避免由在以光 CVD 6 〇,5 , 〇<15 ^ ^,J:^ ❹ 如圖3A所示,以與第一實施例相同的方式二 程開始時先形成隔離氧化膜2、閘氧化膜3、N+#^石夕膜4 鎢膜5、及CVD氧化膜6。然後,以光阻圖幸作^_ 氧化膜6,以形成遮罩氧化膜7。在此働 及二=形罩成氧;=^^ $極30與鄰接^摻雜雜觸部15之間發生=度 200949958 會以CMP 11之後,形成隨後其表面 藉由使用光阻圖案t為電/ l2,如圖3D所示。然後,
(stopper)來蝕刻層間介電質;氮化膜Η作為停止層 所示。 間;1電貪12 ’而形成單元接觸孔洞13,如圖3E ❹ 過程中存在而使其可自我對準於單元閘電極8之 上形 _,如該所示,接著並 二^阶曝露出來。此導致形成側壁26。被形成來覆蓋側氧= 膜32q之侧壁26,供了雙重絕緣結構,如圖31所示。 一取後,以N+摻雜矽接觸部15填充單元接觸孔洞13,如圖耵 所不’因—而製造了與第一實施例相似之半導體裝置,如圖苽所示。 ❹ 此貫施例之製造程序使用由第二氮化膜25所形成之側壁 26、及形成自長度放大單元閘電極3〇之侧氧化膜32,來提供N+ 摻雜矽接觸部15與單元閘電極8之間的穩固絕緣,即使在形成長 度放大單元閘電極3〇時亦然。如此可以有效地防止位元線22與 單元閘電極8之間及/或電容電極18與單元閘電極8之間發生短' 路。包含上述熱氧化處理之第二實施例之製造程序提供了與第一 實施例所提供者相似的優點。 '
顯而易見的是’本發明不限於上述的實施例,在不背離本發 明之範疇下可做修正及改變。 X 【圖式簡單說明】 自結合了附圖之上列特定較佳實施例的敘述,本發明之上述 .200949958 ~ 目的、優點與特徵將更清晰,其中: 其 用來+置之製祕的剖面圈 古土f 至2K顯示本發明之第一實施例中之半導體裝置之製造 万法的剖面圖;及 圖3Α至3Κ顯示本發明之第二實施例中之半導體裝置之製造 方法的剖面圖。 【主要元件符號說明】 ^ 1 ρ型矽基板 2隔離氧化膜 3閘氧化膜 4 Ν+摻雜矽膜 5矽化鎢膜 6 CVD氧化膜 7遮罩氧化膜 8單元閘電極 9殘餘物 10 Ν型擴散層 Q 11第一氮化膜 12層間介電質 13單元接觸孔洞 14側壁 15 Ν+掺雜矽接觸部 17電容接觸部 18電容電極 19電容介電質 2〇電容板 21位元線接觸部 22位元線 11 200949958 23熱氧化膜 24氧化增強氧化膜 25第二氮化膜 26侧壁 27覆蓋氧化膜 29微小粒子 30長度放大單元閘電極 31 側表面 32側氧化膜 101 P型矽基板 102 隔離氧化膜 103閘氧化膜 104 N+摻雜矽膜 105 矽化鎢膜 106 CVD氧化膜 107遮罩氧化膜 108 單元閘電極 109 殘餘物 110 N型擴散層 111第一氮化膜 112層間介電質 113 單元接觸孔洞 114侧壁 115 N+摻雜矽接觸部 116 短路部分 117 電容接觸部 118 電容電極 119電容介電質 120 電容板 121 位元線接觸部 12 200949958 122 位元線
Claims (1)
- 200949958 七、申請專利範圍: 1.一種半導體裝置的製造方法,包含以下步驟: 經由蝕刻沉積在一半導體基板上之一閘電極膜而形成複數個 閘電極; 形成一第一氮化膜以覆蓋該閘電極; 經由在該第一氮化膜上施行一回餘(etch-back)處理,而使該半 導體基板局部地曝露在該複數個閘電極之鄰接兩者之間的區域 中; 、將該閘電極膜殘留在該複數個閘電極之該鄰接兩者之間的該 區域中之殘留物熱氧化,以使該殘留物改變成一熱氧化膜;及 在該複數個閘電極之該鄰接兩者之間的該區域中形成一接觸 〇 部。 2.根據申請專利範圍第1項之半導體裝置的製造方法,更包含 以下步驟: ⑽fif露該轉縣板的步狀後,_轉縣板在該複 ϊΐΐ 卿接兩者之間的舰域中之—表面部分上形成一 擴散層。 以下ϋ射請專雜㈣1狀半賴裝置的製紗法,更包含 之-半導體基板的步驟之後,形成覆蓋該半導體基板 的該在該複數個閉電極之該鄰接兩者之間 4·根據申清專利範圍第1 導^ ^ ^ ^ ^ 閑電氧化速率較該半導體k之熱 _=^圍第=料峨=,其中該 其中,當二1::;;匕;上因=成該閑電極之側壁,及 局部曝露時,藉由料〃;;:中之一因為_飿處理而在一側面上 200949958 6. —種半導體裝置,包含: 一閘電極’形成在一半導體基板上方並被一侧壁所覆蓋;及 β、一接觸部,鄰接該側壁而形成,以在該半導體基板之一擴散 區域與认置於遺閘電極上方之一互連線路(interc〇nnecti〇n)之間提 供連接, =中,在至少該側壁鄰接於該半導體基板之一表面之一部分 :該藉由絕緣材料而絕緣,而該絕緣材料 絕緣’纟侧壁位於該 伸至置,其__延 八、圖式:15
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