TWI331393B - Memory device and method of fabricating the same - Google Patents

Description

1331393 Revision Date: Patent Specification No. 96105263, May 25, 1999, the present invention is related to the invention. And its manufacturing method. [Prior Art] The development technology of integrated circuits is changing with each passing day, and its development trend is moving toward powerful functions, size reduction and speed acceleration, and the manufacturing technology of dynamic random access memory (DRAM) is also the case, especially its memory capacity. The increase is the most important key. Most of today's DRAM cells are made up of a transistor and a capacitor. The current design is paired with a deep trench capaci tor, which is fabricated in a deep trench in the semiconductor germanium substrate. Reduce the size and power consumption of the memory unit, thus speeding up its operation. Since the memory capacity of DRAM has reached 256 million bits or even 512 million bits or more, the memory cell and the size of the transistor need to be greatly reduced in order to create a memory in the case where the component accumulation requirement is higher and higher. Higher capacity, faster processing DRAM. Referring to Figure 1, a cross-sectional view of a conventional memory device 10 is depicted. A deep trench capacitor 20 is fabricated in a semiconductor germanium substrate 12, including a buried lower plate 14, a node dielectric 16 and an upper electrode plate 18. The deep trench capacitor 20 is formed by first forming a deep trench in the P-type semiconductor germanium substrate 12 by reactive ion etching (RIE), and then by heavily doping an oxide (for example, arsenic glass (ASG)) and High temperature for a short time

0548-A50285-TW Amendment No. 96105263 Patent Specification, Amendment Period · May, 1999: κ mouth fire process ' can make n+ type ions month. The Japanese domain forms a buried lower electrode plate in the lower part of the JS channel in the ΓΗ-type diffusion zone; in the deep trench: only:::: trench, capacitor 20 into a nitrogen-cut layer, material = and bottom shape I) And shouting (kiss s) the first-multilayer is called to form the upper electrode plate 18 of the deep trench capacitor 20. ~ can be made before the side wall of the area above the deep trench - collar type "lel:ctric" 22, and then in the upper area of the deep trench: as the second polycrystalline layer of noisy) 24 'Continue Bs p〇iy 26. Afterwards, a shallow meaning can be made: isolation area (10) 32, word line WL1, WL2, source r; , bit contact plug BC and bit, Line BL and other processes, #中浅"; ::: 2 2 is used to distinguish two adjacent DRAM cells or define memory ▲ In addition, in order to connect the deep trench capacitor 20 and the surface f, around the top opening of the deep trench A buried strap outdif fusion 28 is also formed in the base 12, and is also referred to as a node bonding interface (n〇de junc1: i〇n), which is formed by making the second polycrystal The n+ type ions in the germanium layer 24 diffuse outward into the adjacent hair substrate 12 via the third polysilicon layer. Therefore, the third polycrystalline layer 26 is also referred to as a buried polycrystalline layer (BS poly) 26. The purpose of the collar dielectric layer 22 is to achieve effective isolation between the buried buried out-of-band diffusion region 28 and the buried electrode plate 14 to prevent the vertical leakage here from increasing the retention time of the DRAM cell ( Retenti〇n time) °

0548-A50285-TW 1331393 'No. 96】05263 Patent Specification Revision This revision period: May 25, 1999 However, the traditional collar dielectric layer 22, the second polysilicon layer (Poly 11) 24, The wire structure of the tripoly germanium layer 26 affects the distribution of the buried out-of-band diffusion region 28 and the overlap tolerance of the transistor and the deep trench, and causes the buried out-of-band diffusion region 28 to be buried as the size of the memory device continues to shrink. A serious leakage current occurs and a sub-voltage (sub-Vt) problem occurs. In addition, as the size of the memory device continues to be reduced with more advanced processes, the resistance of the second polysilicon layer (Poly II) 24 of the wire structure becomes more severe, the high resistance value and the delay effect of the resistor and capacitor. (RC delay), which will affect the operation of the memory device. The stomach therefore requires a new memory device wire structure to solve the problems caused by the distribution of the buried out-of-band diffusion region 28, improve the sub-critical voltage (sub-Vt) problem, and improve the resistance and resistance of the wire structure. RC delay. SUMMARY OF THE INVENTION The present invention provides a memory device comprising: a substrate having a deep trench and an upper surface; a deep trench capacitor located under the deep trench; a wire structure located in the deep trench Above the deep trench capacitor, wherein the wire structure comprises: a conductive layer connecting the deep trench capacitor, a collar dielectric layer on the sidewall of the deep trench to surround the conductive layer, and a buried strap layer above the collar dielectric layer Adjacent to the conductive layer; and a buried barrier layer, the deep trench sidewalls above the collar dielectric layer abut the substrate and the buried strap layer. The present invention provides a method of fabricating a memory device, comprising: providing a substrate; forming a deep trench in the substrate; forming a deep trench capacitor in the lower portion of the deep trench; forming a jaw dielectric layer on the deep trench capacitor

0548-A50285-TW The patent specification of 96105263 modifies the side wall of the deep trench of the party; formation = positive date: " May 25th ^ vrn Φ ^ , , V electric layer adjacent to the deep collar type in the trench The dielectric layer comprises a dielectric layer formed over the buried dielectric layer and adjacent to the conductive layer to form a conductive line. [Example]: The description of the embodiment is related to the implementation of the easy-to-read part of the figure. Part of the method, in the embodiment, the name, the wording of the name such as "lower, upper, horizontal, vertical, upper and lower: this part, etc." and its derivative words must refer to the figure Direction: The term name is used only to facilitate the convenience of the description of the implementation, without the need to construct or operate the equipment. Names such as "join, interconnect, couple, etc." are related to ^, the intermediate structure is closely attached or bonded to another object, and φ contains a movable or rigid connection unless otherwise described. Referring to FIG. 2, a substrate 112 is provided. The substrate 112 is, for example, a substrate formed of m; ':1, and secondly, a pad layer is formed on the surface of the substrate 112. The II-I deposit-oxygen pad layer 114 covers the substrate. 112, then a ratification fossil mat 116 covers the oxidized stone mat 114. The deep trenches 118 are formed in the substrate 112 by using the lithography layer as a screen by using a lithography process and a reactive ion surname (RIE) potential. ^, Figure 3, followed by the fabrication of deep trench capacitors 13Θ, deep trench capacitors generally include buried lower electrode plates, node dielectric layers and power-on, board' and the following examples are for convenience only. It is not intended to limit the invention. First, the type can be separated by a heavily doped oxide, such as arsenic glass ASG) and a short-time annealing process (RTp).

0548-A50285-TW 1331393 "Patent Specification No. 96105263 Amendment Revision Date: May 25, 1999, for example, As-, diffuses into the area below the deep trench 118 to form an n+ type diffusion region for use as a deep trench capacitor 130 The buried lower electrode plate '124. Secondly, a dielectric layer is formed on the inner sidewall 'and the bottom of the region below the deep trench 118, and the material thereof may include tantalum nitride or tantalum oxide for use as a node of the deep trench capacitor 130. An electric layer 126; and depositing an n+-type doped first polycrystalline layer (Poly I) in the deep trench, and returning the first polycrystalline germanium layer to a predetermined depth for use as a deep trench The upper electrode plate 128 of the capacitor 130. After completing the deep trench capacitor 130 described above, a collar dielectric 122 is formed on the sidewall of the deep trench 118 in the region above the deep trench capacitor stomach 130. For example, the collar type The dielectric layer can be selected by the following process steps. For example, a ruthenium oxide layer can be deposited on the surface of the wafer by low pressure chemical vapor deposition (LPCVD), which covers the first polysilicon layer 128, the deep trench 118, oxygen The ruthenium pad layer 114 and the ruthenium nitride pad layer 116 have a thickness of about 305±3 〇A; and the yttrium oxide layer is densified by a rapid thermal process (RTP) to a thickness of 130±13 A; The ruthenium oxide layer is exposed to the upper surface of the first polysilicon layer 128 and the tantalum nitride pad layer 116 to form a collar type ruthenium oxide layer covering the sidewall of the deep trench 118 and the ruthenium oxide layer. The sidewall of the pad layer 114 also serves to protect the yttrium oxide pad layer 114 from subsequent processes.

Referring to FIG. 4, a conductive layer 132 of the wire structure 140 is formed, which is located in the deep trench 118 adjacent to the deep trench capacitor 130, mainly the upper electrode plate 128, and the conductive layer 132 is formed by a collar dielectric layer] Surrounded by. In this embodiment, the polycrystalline germanium material is replaced by a conductive metal compound. Hereinafter, titanium nitride (TiN) is taken as an example. Before the titanium nitride is formed, a pre-cleaning step can be performed, for example, by using ammonia water NH40H. 0548-A50285-TW 9 1331393 f ___正本赃_: May 99? 5th (DHF) to remove impurities on the wafer; in the deep trench method & method includes chemical vapor deposition, and can be used in a chemical mechanical polishing process (CMP), = deratization = unnecessary titanium nitride on the pad layer 116, exposing the nitriding of the nitrite to the second layer of titanium nitride, for example, the surface of the sulphuric acid and the peroxygen-containing surface can be used to form a wire structure. _ Collar oxygen cut layer mi 'θ / wood degree, to control the memory device here control circuit current and deep trench capacitance ϋ 130 effective storage power. In the embodiment of the present invention, a metal compound such as a derivative replaces the polycrystalline side enthalpy (ie, = can avoid dopant ions in the polycrystalline material, and diffuses to the substrate 112 in a subsequent process (Α〇, ☆~底* affects the effect of the memory device. Therefore, one of the advantages of the 钿 , 可 可 可 可 可 可 可 可 可 可 可 可 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋The flow can be generated to replace the problem of "Thunder", "Throat", and "Sub-Vt"; in addition, f2 continues to reduce the size of the memory device, including 〇.lMm the following process, the present invention is the actual resistance of each of the 0 (four) (four) sii kiss), can have a lower delay. Then carry out a pre-clearing electricity, liquid (recorded to remove the miscellaneous / make - mouse The acid is dissolved in the embodiment of the present invention, and a layer 1j4 composed of a thin nitride or an oxide material, or a layer of nitride nitride can be formed, for example, buried in the barrier layer 134.

0548-A50285-TW 10 ^96105263 Round: May 25, 1999 112 The sidewall of the surgical 'covers the exposed base】] 2, adjacent to the base] 34 and the right second pass formed by the buried layer 136; this buried zone The barrier layer 'has a degree of about 5 to 7 Α, and can use lv, state wood k 丨 secret 7 _ la degree and control current. A is used to properly control the ion diffusion process, and the fabrication of the buried layer (BS) 136 is performed on the 5th dielectric layer 122 and adjacent to the conductive layer 132 to form a conductive layer. - the mouth structure f, in the example, the material of the buried layer is made of amorphous stone (coffee such as I:: A, forming a buried layer 136, and etching the collar oxygen before filling = 2 = slit) Covering the conductive layer 132 and the substrate ιΐ2; it is possible to deposit about 3 〇〇a (AMORPHOUS Silicon) in a 500 c environment. <Non-day shi shi shi 2, 6f, then by using a wet rice engraving process, money The conductive structure 132, the tantalum nitride layer 116, the yttrium oxide layer, the H-substrate 112, and the buried layer (10) 136 are formed to form the wire structure U0. In the embodiment of the present invention In the middle, since the polycrystalline germanium material is replaced by a metal compound such as titanium, (that is, the source of the 10' dopant is only likely to come from the buried layer 136, the wide area 138' has a lower distribution, which can improve the 'k boundary The problem of voltage (sub-Vt). Mountain: Test Figure 7, then form a shallow trench insulation layer (STI) 142, = ', line, ,. In the upper portion of the portion 40, this embodiment can perform a lithography process to define a shallow trench by using a conventional Ding: a post-deposited oxygen layer, and a planarization process is performed on the wafer to form a planarization layer 116. And the oxidized stone mat layer 114, forming a memory device just

0548-A50285-TW 1331393 Patent Specification No. 96105263 Revision of this revision date: May 25, 1999, shallow trench insulation (STI) 142, and defining the active area of the memory device 100 (Active Area) Show). The present invention has been disclosed in the preferred embodiments of the present invention, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 0548-A50285-TW 12 1331393 'Patent No. 96105263 Amendment Revision Date: May 25, 1999 [Simple Description of the Drawings] _ In order to more fully illustrate the contents of the present invention and its benefits, One explanation: The first figure is a schematic cross-sectional view of a conventional memory device. 2 through 7 are schematic cross-sectional views showing different stages of the manufacturing process of the memory device in accordance with an embodiment of the present invention. [Main component symbol description] substrate ~12,112; node dielectric layer ~16,126; deep trench capacitor ~20,130; second polysilicon layer ~24; conductive layer ~132; buried layer ~136; •, wire structure ~ 30, 140; oxidized stone mat layer ~ 114; memory device ~ 10, 100;

Buried lower electrode plate ~14,124; upper electrode plate ~18,128; collar dielectric layer ~22,122; third polycrystalline layer ~26; buried with barrier layer ~134; buried outside the band Diffusion region ~ 28, 138 shallow trench insulation ~ 32, 142; tantalum nitride pad ~ 116.

0548-A50285-TW 13

Claims (1)

1331393 Amendment date: Amendment of Patent Specification No. 96105263 of May 25, 1999. Scope of application: I. A memory device comprising: a substrate having a deep trench and an upper surface; Located in the lower part of the deep trench; 2-wire structure, the deep trench capacitor on the deep trench, 'Γ collar ^^ structure ^:: a conductive layer connected to the deep trench capacitor book ^ S is located in the side of the deep trench to surround the a conductive layer, and a buried 4 is located above the collar dielectric layer and adjacent to the conductive layer. The deep trench side soil 4 adjacent to the collar dielectric layer is connected to the substrate and the buried layer; Buried into the out-of-band diffusion region, the dopant in the substrate adjacent to the embedded buried-band out-diffusion region is only from the layer, and the conductive layer is composed of a metal compound. The memory device of claim 1, wherein the deep trench===peripheral device, wherein the bottom of the deep trench, the wooden trench in the base of a node dielectric layer is adjacent to the buried The electrode plate and the upper trench are surrounded by the dielectric layer. . Tomb t Please refer to the memory device described in item 3 of the patent scope, in which the conductive layer contains titanium nitride (TiN). /, A V ^ As claimed in the patent scope of item i, the buried barrier layer has a thickness of about 5 to 7 people. /,in. The memory device according to the first aspect of the patent application, wherein the bean layer is embedded in the belt layer and comprises an amorphous layer. 1 /, 〒 &quot; 玄 0548-A50285-TW 1331393 Amendment No. 96105263 Patent Specification - 7. If you apply for the special revision date ·&quot;year D month 25曰- shallow trench insulation layer, embedded in the memory Body device, more includes... Please specialize in the upper area. Buried oxide or nitrided '(4), which is 9. The manufacturing method of the buried or nitrided side constituting the 5 丨 丨 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思 思Forming a deep trench in the substrate. = a deep trench capacitor in the lower portion of the deep trench; a sidewall of the trench; and an electrical layer above the deep trench capacitor 11 of the deep trench two conductance layer: surrounding the deep trench adjacent to the deep a trench capacitor, and forming a buried strap layer on the collar dielectric layer to form a wire structure; β connecting the conductive sidewall shape into the deep trench substrate H with a barrier layer above the collar dielectric layer The dopant in the buried-band L diffusion region adjacent to the barrier layer of the buried strap is only from the germanium buried strap layer 'where the conductive layer is composed of a metal compound. The method of manufacturing the memory device of claim 10, wherein the method of forming the deep trench comprises: depositing a pad on the substrate; patterning the underlayer; and using the pad The layer is a mask that etches the substrate. 0548-A50285-TW Patent Specification No. 96105263 Revision 22 l ^ Revision Date: May 25, 1999 Method, in which the method of manufacturing the memory farm described in item 1G of the profit range becomes the method of the deep trench capacitor And comprising: a buried lower electrode plate, the bottom side wall of the deep trench under the base and the deep trench. y into the upper electrode plate, which is located in the deep trench by the dielectric layer, and the manufacturing of the memory device described in item 1G of the scope of the second application, "connecting/forming the dielectric layer" The method comprises: and: a bottom Ϊ oxygen layer covering the deep trench capacitor, the deep trench sidewall and the ordering! Idle speed hot process (RTP) to densify the oxidized stone layer; the upper layer is exposed to expose the depth The method of the method of the present invention, wherein the method of the memory device described in the item 第 〇 , , , , , , , i i 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆Composition. The method further comprises the following steps: manufacturing the memory device according to the above-mentioned memory device, and fabricating the memory device according to the method of the method of embedding the wire structure. The buried ▼ barrier layer has a thickness of about 5 to 7 Å. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; It is composed of an oxide or nitride material. 19. The method of fabricating a memory device according to claim 10, wherein the buried barrier layer is composed of yttrium oxide or tantalum nitride material. 0548-A50285-TW 1331393 Revision date: May 25, 1999 Revision of Patent Specification No. 96105263 VII. Designation of Representative Representatives: (1) The representative representative of the case is: Figure 7. (b) A brief description of the component symbols of this representative figure: buried with barrier layer ~ 134; buried in the out-of-band diffusion region ~ 138; wire structure ~ 140 shallow trench insulation layer ~ 142. Memory device ~100; buried lower electrode plate ~124 upper electrode plate ~128; collar dielectric layer ~122; substrate ~112; node dielectric layer ~126; deep trench capacitor ~130; conductive layer ~132; Buried layer ~136; 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: No 0 0548-A50285-TW 4