200834885 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種記憶體裝置，特別是有關於一種具 有記憶體裝置之導線結構及其製造方法。 【先前技術】 積體電路的發展技術日新月異，其發展趨勢往功能強 大，尺寸縮小與速度加快的方向前進，而動態隨機存取記 • 憶體（DRAM)的製造技術亦是如此，尤其是其記憶容量的 增加更是最重要的關鍵。 現今大多數的DRAM單元是由一個電晶體與一個電容 器所構成，目前的設計係搭配一種深溝渠電容器（deep trench capacitor)，將三維的電容器結構製作於半導體 矽基底内的深溝渠中，可以縮小記憶單元的尺寸與電力消 耗，進而加快其操作速度。由於目前DRAM之記憶容量已 達到256百萬位甚至512百萬位元以上，在元件積集度要 φ 求越來越高的情況下，記憶單元與電晶體的尺寸需要大幅 縮小，才可能製造出記憶容量更高，處理速度更快的DRAM。 請參閱第1圖，係繪出傳統記憶體裝置10之剖面示 意圖。一半導體矽基底12内製作有一深溝渠電容器20， 包含一埋入式下電極板（buriedplate) 14、一節點介電 層（node dielectric) 16以及一上電極板18。深溝渠電 容器20之形成，首先係利用反應性離子蝕刻（RIE)，於 P型半導體矽基底12内形成深溝渠，然後，藉由一重度 摻雜氧化物（例如：砷玻璃（ASG))以及高溫短時間的退 客戶編號:92280 本所編號:0548-A50285-TWF/WCWong/Chad 5 200834885 f 火製程，可使n+型離子，例如As_，擴散至深溝渠下方區 域，而形成一 n+型擴散區14，用來作為深溝渠電容器20 的埋入式下電極板；於深溝渠下方區域之内側壁與底部形 成一氮化矽層，用來作為深溝渠電容器20的節點介電層 16;而於深溝渠内沉積一 n+型摻雜之第一多晶矽層（ Poly I )，並回餘（recess)第一多晶石夕層至一預定深度，則可 以形成深溝渠電容1§20的上電極板18。 接著，先於深溝渠上方區域的侧壁上製作一領型介電 層（col lar dielectric ) 22，再於深溝渠上方區域内製 • 作一 n+型摻雜之第二多晶矽層（Poly II) 24，再繼續製 作一第三多晶矽層（BS Poly) 26。後續則可進行一淺溝 槽隔離區（STI) 32、字元線WL1、WL2、源/汲極擴散區 域、位元接觸插塞BC以及位元線BL等製程，其中淺溝槽 隔離區32是用來區分兩相鄰之DRAM胞或定義記憶體裝置 之主動區。 此外，為了連接深溝渠電容器20以及表面之電晶 體，深溝渠之頂部開口周圍的矽基底12内形成有一埋入 φ 帶外擴散區域（buried strap outdiffusion) 28，亦稱 之為一節點接合介面（node junction)，其形成方式是使 第二多晶矽層24内之n+型離子經由第三多晶矽層26而 向外擴散至鄰近的石夕基底12中。因此，第三多晶石夕層26 也稱為一埋入帶多晶梦層（BS poly) 26。領型介電層22 之目的是使隔絕埋入帶外擴散區域28與埋入電極板14 之間達到有效的隔絕，以防止此處的漏電流問題 (vertical leakage)增加 DRAM 胞之保留時間（retention time) 〇 客戶編號:92280 本所編號:0548-A50285-TWF/WCWong/Chad 6 200834885 統之領型介電層22、第二多晶石夕層⑴ 一夕日日矽層26之導線結構，影響埋入帶外擴散區 域28的分佈，以及電晶體與深溝渠之重疊容忍度，在記 寸繼續縮小時’導致埋人帶外擴散區域28處 !又嚴，的漏電流，亚產生次臨界電壓（）的問題。 * t匕夕合’ ^著更先進製程而繼續微縮記憶體裝置之尺寸 變的爭αΛ : ( 〇ly Π) 24的阻值影響 k的更為嚴重’局阻值及其電阻電容延遲 delay)，將影響記憶體裝置之運作。 需要—種新的記憶體裝置導線結構，以解決埋 入f外擴政區域28的分佈所產生的問 的問題，以及改善導線結構之阻二!ί 容延遲效應（RC delay)。 Έ 【發明内容】 本發明提供一種記憶體裝置，包含··一基底，且 ί溝iiitt面;—深溝渠電容器，位於該深溝渠下 二其結:=深溝渠電容器上 口口 ^ ,入 再匕a · &電層連接該深溝渠雷究 二：ί”電層位於深溝渠側壁以包圍該導電層、及- 領型介電層上方並鄰接該導電層;以及- 該基底及該埋人帶層。電層上方之珠溝渠側壁鄰接 本發明提供—種記憶體裝置的製造方法，包含 一基底；形成一深溝渠於該基底中；形 二 於該深溝渠下部；形成-領型介電層㈣深溝渠ϊ容= 客戶編號:92280 本所編號:0548-A50285-TWF/WeW〇ng/ehad 7 200834885 =壁；形成—導電層於該深溝渠内鄰接該深 = ^該領型介電層所包圍；以及形成一埋入 ::該7頁型介電層上方並鄰接該導電層，以形成導線 、、、口 〇 【實施方式】 μ :ί例中員施方式之描述係關連至所屬圖示之易讀 μ::不係王部貫施方式之一部份，在實施方式中’相 關名稱用詞例如「較低、較上、水平、垂直、上、下、頂 :、，」尽其衍生詞彙皆須參考圖示中所繪之方向， 名％用詞僅便於實施方式描述之便利性，而不需 在f疋方向上建構或操作儀器設備。名稱賴上關於聯繫 七：如*連接、互連、耦合等」係有關於其中之結構 直接或透過巾間結構與另—物體緊連或黏合，亦包含可動 式或剛性連接，除非有另外描述。 參考第2圖’提供一基底112，該基底ιΐ2例如是由 石夕材料形成之基底，其次，於基底112表面形成一塾層， 例如y先沉積-氧切塾層114覆蓋該基底112，然後沉 積-氮化轉層116覆蓋該氧切塾層114。以墊層作為 罩幕，藉由使用微影製程及反應性離子_(rie)製程， 於基底112内形成深溝渠118。 、圖，接著進行丨罙溝渠電容器130的製作，深 溝渠電容器-般包括埋入式下電極板、節點 極板，而以下實施例則僅為方便說明起’，並: 電 定本發明。首先可藉由-重度摻雜氧以限 (ASG)’以及高溫短時間的退火製 ’坤玻璃 V Κ1Ρ)，使η+型離 客戶編號:92280 本所編號:〇548-A50285-TWF/WCWong/Chad 8 200834885 子，例如As·’擴散至深溝友 擴散區，用來作為深溝渠=U8下方區域，形成一 n+型 124。其次形成一介電層於裔13〇的埋入式下電極板 與底部，其材料可包含氮^菜溝知118下方區域之内侧壁 電容器130的節點介電屑矽或氧化矽，用來作為深溝渠 型摻雜之第一多晶矽層7 26 ;以及於深溝渠内沉積一 n+ 多晶石夕層至一預定深;n，並回蝕（re_)第一 電極板128。 用來作為深溝渠電容器130的上200834885 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a memory device, and more particularly to a wire structure having a memory device and a method of fabricating the same. [Prior Art] The development technology of integrated circuits is changing with each passing day, and its development trend is moving toward powerful functions, size reduction and speed acceleration, and the same is true for dynamic random access memory (DRAM) manufacturing technology, especially its The increase in memory capacity is the most important key. Most of today's DRAM cells are made up of a transistor and a capacitor. The current design is combined with a deep trench capacitor to make a three-dimensional capacitor structure in a deep trench in the semiconductor germanium substrate. The size and power consumption of the memory unit accelerates its operating speed. Since the memory capacity of DRAM has reached 256 million bits or even 512 million bits or more, in the case where the component accumulation degree is to be higher and higher, the size of the memory cell and the transistor needs to be greatly reduced, and it is possible to manufacture. A DRAM with higher memory capacity and faster processing speed. Referring to Figure 1, a cross-sectional view of a conventional memory device 10 is depicted. A deep trench capacitor 20 is fabricated in a semiconductor germanium substrate 12, including a buried lower plate 14, a node dielectric 16 and an upper electrode plate 18. The deep trench capacitor 20 is formed by first forming a deep trench in the P-type semiconductor germanium substrate 12 by reactive ion etching (RIE), and then by heavily doping an oxide (for example, arsenic glass (ASG)) and High temperature and short time customer number: 92280 The number of the company: 0548-A50285-TWF/WCWong/Chad 5 200834885 f The fire process allows n+ ions, such as As_, to diffuse into the area below the deep trench to form an n+ type diffusion. a region 14 for use as a buried lower electrode plate of the deep trench capacitor 20; a tantalum nitride layer is formed on the inner sidewall and the bottom portion of the lower trench region for use as the node dielectric layer 16 of the deep trench capacitor 20; Depositing an n+-type doped first polysilicon layer (Poly I) in the deep trench and returning the first polycrystalline layer to a predetermined depth, the deep trench capacitor 1 § 20 can be formed. Upper electrode plate 18. Next, a collar dielectric layer 22 is formed on the sidewall of the upper region of the deep trench, and then an n+ doped second polysilicon layer is formed in the upper region of the deep trench (Poly II) 24, continue to make a third polysilicon layer (BS Poly) 26. Subsequently, a shallow trench isolation region (STI) 32, a word line WL1, WL2, a source/drain diffusion region, a bit contact plug BC, and a bit line BL may be performed, wherein the shallow trench isolation region 32 It is used to distinguish two adjacent DRAM cells or active areas that define memory devices. In addition, in order to connect the deep trench capacitor 20 and the surface of the transistor, a buried strap outdiffusion 28 is formed in the germanium substrate 12 around the top opening of the deep trench, also referred to as a node bonding interface ( The node junction is formed by diffusing the n+ type ions in the second polysilicon layer 24 to the adjacent stone substrate 12 via the third polysilicon layer 26. Therefore, the third polycrystalline layer 26 is also referred to as a buried polycrystalline dream layer (BS poly) 26. The purpose of the collar dielectric layer 22 is to achieve effective isolation between the buried buried out-of-band diffusion region 28 and the buried electrode plate 14 to prevent the vertical leakage here from increasing the retention time of the DRAM cell ( Retention time) 〇Customer ID: 92280 The number of the company: 0548-A50285-TWF/WCWong/Chad 6 200834885 The dielectric layer 22, the second polycrystalline layer (1) The wire structure of the layer 26 Affects the distribution of the buried out-of-band diffusion region 28, and the overlap tolerance of the transistor and the deep trench. When the recording continues to shrink, it leads to the buried out-of-band diffusion region 28! Strict, leakage current, sub-critical sub-critical Voltage () problem. * t匕夕合' ^ With a more advanced process and continue to shrink the size of the memory device ΛαΛ : ( 〇ly Π) 24 resistance affects k more serious 'local resistance value and its resistance and capacitance delay delay) Will affect the operation of the memory device. A new memory device wire structure is needed to solve the problem of the distribution of the buried area 28 and to improve the resistance of the wire structure! RC delay. Έ [Summary of the Invention] The present invention provides a memory device comprising: a substrate, and a yip iiitt surface; a deep trench capacitor located under the deep trench and its junction: = deep trench capacitor on the mouth ^, into匕a · & electrical layer is connected to the deep trench 2: ί" electrical layer is located in the sidewall of the deep trench to surround the conductive layer, and - above the collar dielectric layer and adjacent to the conductive layer; and - the substrate and the buried The human belt layer. The sidewall of the bead channel above the electric layer is adjacent to the method for manufacturing a memory device, comprising a substrate; forming a deep trench in the substrate; forming a lower portion of the deep trench; forming a collar type Electrical layer (4) Deep trench capacity = Customer ID: 92280 Our number: 0548-A50285-TWF/WeW〇ng/ehad 7 200834885 = wall; formation - conductive layer adjacent to the deep trench in the deep trench = ^ Surrounded by the electric layer; and forming a buried:: the 7-page type dielectric layer is adjacent to the conductive layer to form a wire, and a port. [Embodiment] μ: The description of the mode of the member is related Easy to read to the picture shown in the picture:: Not part of the way of the king In the embodiment, the words of the relevant names such as "lower, upper, horizontal, vertical, upper, lower, top:,," shall be referred to in the direction indicated in the figure. The words are merely convenient for the description of the embodiments, without the need to construct or operate the instrumentation in the direction of the f. The name relies on the connection seven: such as *connection, interconnection, coupling, etc., the structure of which is directly or through the structure of the towel and the other object is closely connected or bonded, also includes movable or rigid connection, unless otherwise described . Referring to FIG. 2, a substrate 112 is provided, which is, for example, a substrate formed of a stone material, and secondly, a layer of germanium is formed on the surface of the substrate 112, for example, a first deposition-oxygen-cut layer 114 covers the substrate 112, and then A deposition-nitridation layer 116 covers the oxygen chopping layer 114. With the underlayer as a mask, a deep trench 118 is formed in the substrate 112 by using a lithography process and a reactive ion _ (rie) process. The figure is followed by the fabrication of the trench capacitor 130. The deep trench capacitor generally includes a buried lower electrode plate and a node plate, and the following embodiments are for convenience only, and the present invention is electrically determined. First, it can be made by -doping oxygen to limit (ASG)' and annealing at high temperature for a short time, 'Kun glass V Κ1Ρ', so that η+ type is away from customer number: 92280. Number: 〇548-A50285-TWF/WCWong /Chad 8 200834885 Sub, for example, As· diffuses into the deep trench friend diffusion zone and is used as a deep trench = U8 lower region to form an n+ type 124. Next, a dielectric layer is formed on the buried lower electrode plate and the bottom portion of the 13-inch layer, and the material thereof may include the node dielectric crumb or yttrium oxide of the inner sidewall capacitor 130 in the region below the nitrogen channel. a deep trench-type doped first polysilicon layer 7 26; and an n+ polycrystalline layer deposited in the deep trench to a predetermined depth; n, and etched back (re_) the first electrode plate 128. Used as a deep trench capacitor 130
130 木溝渠電容器130之後，於深溝渠電容器 上方&戍的洙溝渠118側壁上形成一領型介電層 (collar dielectric) 122。舉例而言，領型介電層可選擇採 用下列製程步驟完成，例如可先藉由低壓化學氣相沉積法 (LPCVD) ’於晶圓表面沉積一氧化矽層，其覆蓋第一多 晶矽層128、深溝渠118、氧化矽墊層114及氮化矽墊層 116，具有一厚度約305士3〇人；再藉由一快速熱製程 (RTP) ’緻密化該氧化矽層，厚度變為13〇士13人；然後 蝕刻該氧化矽層，使之露出第一多晶矽層128及氮化矽墊 層Π6之上表面，形成一領型氧化矽層，該領型氧化矽層 覆蓋深溝渠118之侧壁及氧化矽墊層114之侧壁，此作用 亦在保護氧化矽墊層114不受後續製程所侵害。 參考第4圖，接著需形成導線結構14〇之導電層132, 其位於深溝渠118内，鄰接該深溝渠電容器13()，主要是 上電極板128,且該導電層132由領型介電層122所包圍。 本實施例則以具導電性之金屬化合物來取代多晶矽材 料，以下則以氮化鈦（TiN)為例，其中，於形成氮化鈦 之前’可進行一預先清洗步驟，如藉由使用氨水nh4oh 客戶編號:92280 本所編號:0548-A50285-TWF/WCWong/Chad 9 200834885130 After the wooden trench capacitor 130, a collar dielectric 122 is formed on the sidewalls of the trenches 118 above the deep trench capacitors. For example, the collar dielectric layer can be selected by the following process steps. For example, a layer of germanium oxide can be deposited on the surface of the wafer by low pressure chemical vapor deposition (LPCVD), which covers the first polysilicon layer. 128, the deep trench 118, the yttrium oxide pad layer 114 and the tantalum nitride pad layer 116 have a thickness of about 305 士 3 ;; and the densification layer is densified by a rapid thermal process (RTP), and the thickness becomes 13 gentlemen 13; then etching the yttrium oxide layer to expose the first polysilicon layer 128 and the upper surface of the tantalum nitride layer ,6 to form a collar type yttria layer, the collar type yttrium oxide layer is deep The sidewall of the trench 118 and the sidewall of the yttrium oxide pad layer 114 also protect the yttrium oxide pad layer 114 from subsequent processes. Referring to FIG. 4, a conductive layer 132 of the conductive structure 14 is formed, which is located in the deep trench 118 adjacent to the deep trench capacitor 13 (), mainly the upper electrode plate 128, and the conductive layer 132 is dielectrically shaped by the collar. Surrounded by layer 122. In this embodiment, the polycrystalline germanium material is replaced by a conductive metal compound, and titanium nitride (TiN) is exemplified below, wherein a pre-cleaning step can be performed before the formation of titanium nitride, such as by using ammonia water nh4oh. Customer ID: 92280 Our number: 0548-A50285-TWF/WCWong/Chad 9 200834885
或稀薄氮氟酸（DHF )以清除晶圓上的雜質；於深溝渠 118内填充氮化鈦，形餘化鈦之方法係包含化學氣相沉 積法（CVD) ’然後可進行一化學機械研磨製程（CMp)， 去除氮化矽墊層116上不必要之氮化鈦，露出氮化矽墊層 116上表面，接著蝕刻氮化鈦，例如可使用含硫酸及過氧 化氳之蝕刻液（H2S〇4 + H2〇2)，蝕刻氮化鈦至深溝渠118 内低於，底表面之一既定深度，以形成導線結構之導電層 132，然後以例如濕蝕刻之方式蝕刻領型氧化矽層122至 低於導電層132之深度，以控制記憶體裝置此處之導電路 •徑覓度^進而控制電流大小及深溝渠電容器13〇之有效儲 存電荷时，。本發明之實施例中，導電層132選擇以氮化 鈦（TiN)等金屬化合物取代多晶矽材料（亦即p〇iy π)， 可避免多晶矽材料中之摻雜物離子，譬如砷離子（As-)， 於後續製，中擴散至基底112而影響記憶體裝置之效 能；因此實施例優點之一，可有效控制埋入帶（buded strap，BS)外擴散區域的分佈，提高電晶體與深溝渠之 重豐谷忍度，在記憶體裝置尺寸繼讀縮小時，可減少漏電 φ 流的產生，以改善次臨界電壓（sub-Vt)的問題；此外， 隨著更先進製程而繼續微縮記憶體裝置之尺寸時，包含 0·1μιη以下製程，本發明實施例之導電層132，具有較低 之電阻（low resistivity)，可改善電阻電容延遲效應（RC delay)。接著進行一預先清洗步驟，可使用緩衝氫氟酸溶 液（BHF 40 : 1 )，以清除晶圓上雜質。 / 在本發明之實施例中，可形成一埋入帶阻擋層134， 例如由薄氮化物或氧化物材料所構成，較佳者為氧化石夕芦 或氮化矽層。埋入帶阻擋層134 —般係位於該領型介電^ 客戶編號:92280 本所編號:〇548-A50285-TWF/WCWong/Chad 10 200834885 122上方之深溝渠侧壁，覆蓋露出之基底112，鄰接基底 112及後續製程所形成之埋入帶層13 6 ;此埋入帶阻擋層 134具有一厚度約5至7A，可用以適當控制離子擴散程 度及控制電流。 參考第5爵，接著進行埋入帶層（bs) 136的製作， 位於該領型介電層122上方並鄰接導電層132,以形成導 線結構140，用以電性連接深溝渠電容器ι3〇及上方電路Or thin fluorofluoric acid (DHF) to remove impurities on the wafer; filling the deep trench 118 with titanium nitride, and the method of forming the residual titanium includes chemical vapor deposition (CVD) 'and then performing a chemical mechanical polishing Process (CMp), removing unnecessary titanium nitride on the tantalum nitride pad layer 116, exposing the upper surface of the tantalum nitride pad layer 116, and then etching the titanium nitride, for example, an etching solution containing sulfuric acid and barium peroxide (H2S) 〇4 + H2〇2), etching titanium nitride into the deep trench 118 below a predetermined depth of the bottom surface to form a conductive layer 132 of the wire structure, and then etching the collar oxide layer 122 by, for example, wet etching It is lower than the depth of the conductive layer 132 to control the conduction circuit and the diameter of the memory device, thereby controlling the current magnitude and the effective storage charge of the deep trench capacitor 13〇. In the embodiment of the present invention, the conductive layer 132 is selected to replace the polycrystalline germanium material (ie, p〇iy π) with a metal compound such as titanium nitride (TiN), thereby avoiding dopant ions in the polycrystalline germanium material, such as arsenic ions (As- ), in the subsequent system, diffusing to the substrate 112 affects the performance of the memory device; therefore, one of the advantages of the embodiment can effectively control the distribution of the outer diffusion region of the buried strap (BS), and improve the transistor and the deep trench. The weight of the valley, the memory device size can be reduced, the leakage current φ flow can be reduced to improve the sub-threshold voltage (sub-Vt); in addition, with more advanced processes continue to reduce the memory When the size of the device includes 0. 1 μm or less, the conductive layer 132 of the embodiment of the present invention has a low resistivity and can improve the RC delay. A pre-cleaning step is then performed using a buffered hydrofluoric acid solution (BHF 40:1) to remove impurities from the wafer. / In an embodiment of the invention, a buried barrier layer 134 may be formed, for example, of a thin nitride or oxide material, preferably an oxidized stone or a tantalum nitride layer. The buried barrier layer 134 is generally located in the collar type dielectric ^ Customer ID: 92280 The number of the deep trench above the 〇 548-A50285-TWF/WCWong/Chad 10 200834885 122 covers the exposed substrate 112, The buried strap layer 13 is formed adjacent to the substrate 112 and subsequent processes; the buried strap barrier layer 134 has a thickness of about 5 to 7 A, which can be used to appropriately control the degree of ion diffusion and control current. Referring to the fifth vest, a buried strap layer (bs) 136 is then formed over the collar dielectric layer 122 and adjacent to the conductive layer 132 to form a conductor structure 140 for electrically connecting the deep trench capacitor ι3 〇 Upper circuit
結構，本實施例中該埋入帶層材質係以非晶矽（am〇rph〇us silicon)為例；形成埋入帶層136，填入之前蝕刻領型氧 化破層122之細缝中，覆蓋導電層132及基底H2，'形成 之方式，可在500 C環境中，沉積約3⑽人之本質非晶石夕 (intrinsic AMORPHOUS Silicon)。 參考第6圖，之後可藉由使用濕蝕刻製程，蝕刻埋入 帶層136 ’以露出導電層132、氮化石夕墊層116、氧化石夕 藝層114及一部份基底112’完成埋入帶層（bs) 136的 製作，形成導線結構⑽。在本發明之實施例中，因為以 氮化鈦（TlN)等金屬化合物取代多晶矽 η)，掺雜物之來源僅可能來自埋入帶層136，因工 成之埋入帶外㈣區域m，具有較低之 呈 臨界電壓（sub-Vt)的問題。 142 參考第7圖，接著需形成—淺溝槽絕 後入導線結構140之部分上方區域，本實^可利用傳統 技術，進打-微影製程以定義出淺溝槽絕妷 後沉積-氧化石夕層，對晶圓進行—平；去 化石夕塾層116及氧财墊層⑴，形成記憶體裝置議i 客戶編號:92280 本所編號:0548-A50285-TWF/WCWong/Chad 200834885 淺溝槽絕緣層（STI) 142,同時定義出記憶體裝置100之 主動區域（Active Area )(圖中未示）。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟悉此項技藝者，在不脫離本發明之精 神和範圍内，當可做些許更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 客戶編號:92280 12 本所編號:0548-A50285-TWF/WCWong/Chad 200834885 【圖式簡單說明】 為了更完整闡述本發明内容及其中之益處，特對於圖 示内容作一說明： 第1圖係繪出傳統記億體裝置之剖面示意圖。 第2至7圖係依據本發明之實施例，記憶體裝置製造 過程不同階段之剖面示意圖。 【主要元件符號說明】 基底〜12、112; 節點介電層〜16、126 ; 深溝渠電容器〜20、130 ; 第二多晶砍層〜24 ; 導電層〜132 ; 埋入帶層〜136 ; ;導線結構〜30、140 ; 氧化砍墊層〜114 ; 記憶體裝置〜10、100 ;In the embodiment, the buried strap layer material is exemplified by amorphous germanium (am〇rph〇us silicon); the buried strap layer 136 is formed, and the slit of the collar-shaped oxide break layer 122 is etched into the slit. The conductive layer 132 and the substrate H2 are covered, and the formation of about 3 (10) people of intrinsic AMORPHOUS Silicon can be deposited in a 500 C environment. Referring to FIG. 6, the buried strap layer 136' can be etched by using a wet etching process to expose the conductive layer 132, the nitride blanket layer 116, the oxidized stone layer 114, and a portion of the substrate 112'. The tape layer (bs) 136 is fabricated to form a wire structure (10). In the embodiment of the present invention, since the polycrystalline germanium is replaced by a metal compound such as titanium nitride (TlN), the source of the dopant may only come from the buried band layer 136, and the buried (4) region m is formed by the work. Has a lower threshold voltage (sub-Vt) problem. 142 Referring to FIG. 7 , it is then necessary to form a shallow trench and a portion of the upper portion of the wire structure 140. This can be determined by conventional techniques, and the lithography process is used to define the shallow trench after the deposition - the oxidized stone. On the eve layer, the wafer is flattened; the fossil scorpion layer 116 and the oxygen cushion layer (1) are formed to form a memory device. Customer ID: 92280 The number of the shop: 0548-A50285-TWF/WCWong/Chad 200834885 Shallow trench The insulating layer (STI) 142 defines an active area (not shown) of the memory device 100 at the same time. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. Customer ID: 92280 12 Our number: 0548-A50285-TWF/WCWong/Chad 200834885 [Simplified description of the drawings] In order to explain the contents of the present invention and its benefits more fully, the following is a description of the contents: Sketch the schematic diagram of the traditional unit. 2 through 7 are schematic cross-sectional views showing different stages of the manufacturing process of the memory device in accordance with an embodiment of the present invention. [Main component symbol description] substrate ~12,112; node dielectric layer ~16,126; deep trench capacitor ~20,130; second polycrystalline chopping layer ~24; conductive layer ~132; buried layer ~136; Wire structure ~30,140; oxidized chopping layer ~114; memory device ~10,100;
埋入式下電極板〜14、124 ; 上電極板〜18、128 ; 領型介電層〜22、122 ; 第三多晶矽層〜26 ; 埋入帶阻擔層〜134 ; 埋入帶外擴散區域〜28、138 淺溝槽絕緣層〜32、142 ; 氮化秒塾層〜116。Buried lower electrode plate ~14,124; upper electrode plate ~18,128; collar dielectric layer ~22,122; third polysilicon layer ~26; buried band resist layer ~134; buried band Outer diffusion region ~ 28, 138 shallow trench insulation ~ 32, 142; nitriding second layer ~ 116.
客戶編號:92280 13 本所編號:0548-A50285-TWF/WCWong/ChadCustomer ID: 92280 13 Our number: 0548-A50285-TWF/WCWong/Chad