TW200901370A - Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same - Google Patents

Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same Download PDF

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Publication number
TW200901370A
TW200901370A TW097109205A TW97109205A TW200901370A TW 200901370 A TW200901370 A TW 200901370A TW 097109205 A TW097109205 A TW 097109205A TW 97109205 A TW97109205 A TW 97109205A TW 200901370 A TW200901370 A TW 200901370A
Authority
TW
Taiwan
Prior art keywords
insulating layer
interlayer insulating
contact
mask pattern
residual
Prior art date
Application number
TW097109205A
Other languages
English (en)
Chinese (zh)
Inventor
Ji-Young Lee
Dong-Seok Lee
Seung-Pil Chung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200901370A publication Critical patent/TW200901370A/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW097109205A 2007-06-15 2008-03-14 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same TW200901370A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070059103A KR100833201B1 (ko) 2007-06-15 2007-06-15 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법

Publications (1)

Publication Number Publication Date
TW200901370A true TW200901370A (en) 2009-01-01

Family

ID=39665505

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097109205A TW200901370A (en) 2007-06-15 2008-03-14 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same

Country Status (3)

Country Link
JP (2) JP5492384B2 (ja)
KR (1) KR100833201B1 (ja)
TW (1) TW200901370A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607957B (zh) * 2014-05-28 2017-12-11 台灣積體電路製造股份有限公司 自對準奈米線及其形成方法與積體電路 結構

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100833201B1 (ko) * 2007-06-15 2008-05-28 삼성전자주식회사 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법
KR101648128B1 (ko) * 2009-12-28 2016-08-24 삼성전자주식회사 가변적인 폭을 가지는 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
FR2960700B1 (fr) * 2010-06-01 2012-05-18 Commissariat Energie Atomique Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias
CN106941091B (zh) * 2016-01-05 2021-03-05 联华电子股份有限公司 内连线结构、内连线布局结构及其制作方法
WO2017136577A1 (en) * 2016-02-02 2017-08-10 Tokyo Electron Limited Self-alignment of metal and via using selective deposition
US10727056B2 (en) 2017-11-23 2020-07-28 Yangtze Memory Technologies Co., Ltd. Method and structure for cutting dense line patterns using self-aligned double patterning
CN107968047A (zh) * 2017-11-23 2018-04-27 长江存储科技有限责任公司 一种sadp页缓冲器切断方法及结构
WO2019195422A1 (en) * 2018-04-03 2019-10-10 Tokyo Electron Limited Subtractive interconnect formation using a fully self-aligned scheme

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JP3412843B2 (ja) * 1992-09-07 2003-06-03 三菱電機株式会社 多層配線の形成方法及び半導体装置
JP2872086B2 (ja) * 1995-08-30 1999-03-17 日本電気株式会社 半導体装置の製造方法
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
JP3445495B2 (ja) * 1997-07-23 2003-09-08 株式会社東芝 半導体装置
JP3501280B2 (ja) * 1998-08-31 2004-03-02 富士通株式会社 半導体装置の製造方法
JP4074014B2 (ja) * 1998-10-27 2008-04-09 株式会社東芝 半導体装置及びその製造方法
JP2001093910A (ja) * 1999-09-27 2001-04-06 Toshiba Corp 半導体装置の製造方法
JP2002203897A (ja) * 2000-12-27 2002-07-19 Nec Corp 半導体装置の製造方法
JP2002280388A (ja) * 2001-03-15 2002-09-27 Toshiba Corp 半導体装置の製造方法
JP2003188252A (ja) * 2001-12-13 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
KR20050103689A (ko) 2004-04-27 2005-11-01 삼성전자주식회사 반도체 장치 제조 방법
KR100602086B1 (ko) 2004-07-13 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자의 배선 형성방법
JP4619839B2 (ja) * 2005-03-16 2011-01-26 株式会社東芝 パターン形成方法
JP4247198B2 (ja) * 2005-03-31 2009-04-02 株式会社東芝 半導体装置の製造方法
KR100640640B1 (ko) * 2005-04-19 2006-10-31 삼성전자주식회사 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법
KR100833201B1 (ko) * 2007-06-15 2008-05-28 삼성전자주식회사 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7960797B2 (en) * 2006-08-29 2011-06-14 Micron Technology, Inc. Semiconductor devices including fine pitch arrays with staggered contacts

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607957B (zh) * 2014-05-28 2017-12-11 台灣積體電路製造股份有限公司 自對準奈米線及其形成方法與積體電路 結構
US10163723B2 (en) 2014-05-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US10504792B2 (en) 2014-05-28 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US10879129B2 (en) 2014-05-28 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning

Also Published As

Publication number Publication date
JP2013168687A (ja) 2013-08-29
JP2008311623A (ja) 2008-12-25
JP5492384B2 (ja) 2014-05-14
KR100833201B1 (ko) 2008-05-28
JP5667240B2 (ja) 2015-02-12

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