KR100833201B1 - 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 - Google Patents

콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 Download PDF

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Publication number
KR100833201B1
KR100833201B1 KR1020070059103A KR20070059103A KR100833201B1 KR 100833201 B1 KR100833201 B1 KR 100833201B1 KR 1020070059103 A KR1020070059103 A KR 1020070059103A KR 20070059103 A KR20070059103 A KR 20070059103A KR 100833201 B1 KR100833201 B1 KR 100833201B1
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KR
South Korea
Prior art keywords
insulating film
mask pattern
etch stop
interlayer insulating
forming
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KR1020070059103A
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English (en)
Korean (ko)
Inventor
이동석
정승필
이지영
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070059103A priority Critical patent/KR100833201B1/ko
Priority to US11/928,034 priority patent/US20080048340A1/en
Priority to TW097109205A priority patent/TW200901370A/zh
Priority to JP2008104941A priority patent/JP5492384B2/ja
Application granted granted Critical
Publication of KR100833201B1 publication Critical patent/KR100833201B1/ko
Priority to US12/966,110 priority patent/US8361904B2/en
Priority to JP2013117185A priority patent/JP5667240B2/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020070059103A 2005-04-19 2007-06-15 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 KR100833201B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020070059103A KR100833201B1 (ko) 2007-06-15 2007-06-15 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법
US11/928,034 US20080048340A1 (en) 2006-03-06 2007-10-30 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same
TW097109205A TW200901370A (en) 2007-06-15 2008-03-14 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same
JP2008104941A JP5492384B2 (ja) 2007-06-15 2008-04-14 半導体素子及びその製造方法
US12/966,110 US8361904B2 (en) 2005-04-19 2010-12-13 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same
JP2013117185A JP5667240B2 (ja) 2007-06-15 2013-06-03 半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070059103A KR100833201B1 (ko) 2007-06-15 2007-06-15 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법

Publications (1)

Publication Number Publication Date
KR100833201B1 true KR100833201B1 (ko) 2008-05-28

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KR1020070059103A KR100833201B1 (ko) 2005-04-19 2007-06-15 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법

Country Status (3)

Country Link
JP (2) JP5492384B2 (ja)
KR (1) KR100833201B1 (ja)
TW (1) TW200901370A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110075394A (ko) * 2009-12-28 2011-07-06 삼성전자주식회사 가변적인 폭을 가지는 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
CN112838070A (zh) * 2016-01-05 2021-05-25 联华电子股份有限公司 内连线结构、内连线布局结构及其制作方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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KR100833201B1 (ko) * 2007-06-15 2008-05-28 삼성전자주식회사 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법
FR2960700B1 (fr) * 2010-06-01 2012-05-18 Commissariat Energie Atomique Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias
US9633907B2 (en) * 2014-05-28 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
WO2017136577A1 (en) * 2016-02-02 2017-08-10 Tokyo Electron Limited Self-alignment of metal and via using selective deposition
US10727056B2 (en) 2017-11-23 2020-07-28 Yangtze Memory Technologies Co., Ltd. Method and structure for cutting dense line patterns using self-aligned double patterning
CN107968047A (zh) * 2017-11-23 2018-04-27 长江存储科技有限责任公司 一种sadp页缓冲器切断方法及结构
TWI797304B (zh) * 2018-04-03 2023-04-01 日商東京威力科創股份有限公司 使用完全自對準方案的消去式互連線形成

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JP2002280388A (ja) * 2001-03-15 2002-09-27 Toshiba Corp 半導体装置の製造方法
KR20050103689A (ko) 2004-04-27 2005-11-01 삼성전자주식회사 반도체 장치 제조 방법
KR20060005502A (ko) 2004-07-13 2006-01-18 동부아남반도체 주식회사 반도체 소자의 배선 형성방법
KR20060110097A (ko) 2005-04-19 2006-10-24 삼성전자주식회사 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법

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JP3412843B2 (ja) * 1992-09-07 2003-06-03 三菱電機株式会社 多層配線の形成方法及び半導体装置
JP2872086B2 (ja) * 1995-08-30 1999-03-17 日本電気株式会社 半導体装置の製造方法
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
JP3445495B2 (ja) * 1997-07-23 2003-09-08 株式会社東芝 半導体装置
JP3501280B2 (ja) * 1998-08-31 2004-03-02 富士通株式会社 半導体装置の製造方法
JP4074014B2 (ja) * 1998-10-27 2008-04-09 株式会社東芝 半導体装置及びその製造方法
JP2001093910A (ja) * 1999-09-27 2001-04-06 Toshiba Corp 半導体装置の製造方法
JP2002203897A (ja) * 2000-12-27 2002-07-19 Nec Corp 半導体装置の製造方法
JP2003188252A (ja) * 2001-12-13 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
JP4619839B2 (ja) * 2005-03-16 2011-01-26 株式会社東芝 パターン形成方法
JP4247198B2 (ja) * 2005-03-31 2009-04-02 株式会社東芝 半導体装置の製造方法
KR100833201B1 (ko) * 2007-06-15 2008-05-28 삼성전자주식회사 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7960797B2 (en) * 2006-08-29 2011-06-14 Micron Technology, Inc. Semiconductor devices including fine pitch arrays with staggered contacts

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280388A (ja) * 2001-03-15 2002-09-27 Toshiba Corp 半導体装置の製造方法
KR20050103689A (ko) 2004-04-27 2005-11-01 삼성전자주식회사 반도체 장치 제조 방법
KR20060005502A (ko) 2004-07-13 2006-01-18 동부아남반도체 주식회사 반도체 소자의 배선 형성방법
KR20060110097A (ko) 2005-04-19 2006-10-24 삼성전자주식회사 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110075394A (ko) * 2009-12-28 2011-07-06 삼성전자주식회사 가변적인 폭을 가지는 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
KR101648128B1 (ko) 2009-12-28 2016-08-24 삼성전자주식회사 가변적인 폭을 가지는 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
CN112838070A (zh) * 2016-01-05 2021-05-25 联华电子股份有限公司 内连线结构、内连线布局结构及其制作方法
CN112838070B (zh) * 2016-01-05 2023-09-26 联华电子股份有限公司 内连线结构、内连线布局结构及其制作方法

Also Published As

Publication number Publication date
JP5492384B2 (ja) 2014-05-14
JP2013168687A (ja) 2013-08-29
TW200901370A (en) 2009-01-01
JP2008311623A (ja) 2008-12-25
JP5667240B2 (ja) 2015-02-12

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