TWI797304B - 使用完全自對準方案的消去式互連線形成 - Google Patents

使用完全自對準方案的消去式互連線形成 Download PDF

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TWI797304B
TWI797304B TW108111833A TW108111833A TWI797304B TW I797304 B TWI797304 B TW I797304B TW 108111833 A TW108111833 A TW 108111833A TW 108111833 A TW108111833 A TW 108111833A TW I797304 B TWI797304 B TW I797304B
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metal layer
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菊地裕樹
前川薰
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日商東京威力科創股份有限公司
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Abstract

本文描述用於後段製程（BEOL, back-end-of-line）結構之自對準互連線圖案化。一種製造積體電路之互連線結構之方法，該方法包括在初始互連線結構上沉積第一金屬層；在第一金屬層上形成包含凹陷特徵部之已圖案化的間隔物層；及使用作為遮罩之該已圖案化的間隔物層中之一凹陷特徵部，蝕刻一自對準通孔在該第一金屬層中並進入該初始互連線結構。方法更包括以第二金屬層填充第一金屬層中之通孔及已圖案化的間隔物層中之凹陷特徵部；去除已圖案化的間隔物層；及使用作為遮罩之第二金屬層，蝕刻一凹陷特徵部在第一金屬層中。

Description

使用完全自對準方案的消去式互連線形成
本發明實施例係有關半導體結構及半導體製程，具體而言，關於用於後段製程（BEOL, back-end-of-line）結構之自對準互連線圖案化。 [相關申請案之交互參照]
本申請案係關於2018年4月3日提出之美國臨時專利申請案第62/651,938號，並主張其優先權，其完整內容係併入本申請案中之參考資料。
在積體電路中之特徵部微縮已成為不斷增長的半導體工業背後之驅動力。微縮至越來越小的特徵部允許在半導體晶片之有限空間上增加功能單元之密度。例如，縮小電晶體尺寸允許在晶片上納入更多數量之記憶體或邏輯元件，有助於製造具有更大容量之產品。然而，對於再更大容量之驅動並非沒有問題。優化每個元件性能之必要性變得日益顯著。
積體電路普遍包括導電的微電子結構，該微電子結構在本領域中係習知為通孔（via），以將通孔上方之金屬線或其他互連線電連接至通孔下方之金屬線或其他互連線。通孔通常藉由微影製程形成。代表性地，可在介電層上旋轉塗佈光阻層，可將光阻層曝光於穿過圖案化遮罩之圖案化光化輻射，隨後可顯影曝光層以在光阻層中形成開口。接著，藉由使用在作為蝕刻遮罩之光阻層中之開口，可在介電層中蝕刻用於通孔之開口。該開口係稱為通孔開口。最後，藉由一或更多金屬或其他導電材料可填充通孔。
過去，通孔之尺寸及間隔已逐漸縮小，且預期在未來，對於至少一些類型之積體電路（例如 ，先進的微處理器、晶片組構件、圖形晶片等），通孔之尺寸及間隔將繼續逐漸縮小。其中一個挑戰為，通孔與上覆互連線之間之疊對（overlay）及通孔與下覆著地互連線之間之疊對一般需要被控制在大約四分之一通孔節距之高容差。由於通孔節距隨著時間推移變得越來越小，疊對容差傾向以比微影設備能夠跟上之更高的速率進行微縮。
另一個挑戰為，極小的通孔節距一般傾向低於甚至為極紫外（EUV）微影掃描機之解析能力。因此，普遍可使用二、三、或更多不同的微影遮罩，這傾向於增加成本。在某些情況，如果節距繼續縮小，即使使用多重遮罩，也可能無法使用EUV掃描機曝印出這些極小的節距之通孔開口。
在各種實施例中揭露用於後段製程（BEOL, back-end-of-line）結構之自對準互連線圖案化。在一實施例中，一種製造積體電路之互連線結構之方法，該方法包括在初始互連線結構上沉積第一金屬層；在第一金屬層上形成包含凹陷特徵部之已圖案化的間隔物（spacer）層；及使用作為遮罩之該已圖案化的間隔物層中之一凹陷特徵部，蝕刻一自對準通孔在該第一金屬層中並進入該初始互連線結構。該方法更包括以第二金屬層填充第一金屬層中之通孔及已圖案化的間隔物層中之凹陷特徵部；去除已圖案化的間隔物層；及使用第二金屬層作為遮罩，蝕刻一凹陷特徵部在第一金屬層中。
在各種實施例中描述用於BEOL互連線之消去式自對準通孔及溝槽圖案化。消去式方法提供常見的雙鑲嵌製程之替代方案，並避免對層間介電（ILD）材料之電漿蝕刻損害。在以下描述中，沒有詳細描述例如積體電路設計佈局之習知特徵，以免不必要地模糊本發明實施例。此外，應理解圖中所示之各種實施例係為說明性表示，且不一定按比例繪製。
一或更多實施例係針對採用消去式技術之方法，該方法採用消去式技術以形成導電通孔及互連線。根據定義，通孔用於著地在先前的層金屬圖案上。在此情況下，在本文中描述之實施例允許更穩健的互連線製造方案，因為不再依賴微影設備之對準。這種互連線製造方案可用以省去大量的對準/曝光，並可藉由自對準技術以改善電連接良率。
自對準接觸窗（contact）及通孔圖案化可用以從單一微影特徵部而圖案化多重接觸窗或通孔。這利用了放大的特徵部抗蝕遮罩與下覆溝槽之交叉點，該等溝槽被待圖案化之硬遮罩層包圍。例如，該技術可用在DRAM記憶胞中，亦可用於先進邏輯，以避免間距分割接觸窗及通孔之多重曝光。
圖1A-1O根據本發明實施例，顯示在消去式自對準互連線形成方法中代表各種操作之積體電路層之部分。
圖1A根據本發明實施例，顯示基板100，該基板100包括初始互連線結構，該初始互連線結構用於深通孔金屬線製造後之自對準互連線形成。基板100包括底層102、蝕刻停止層（ESL）104、層間介電（ILD）特徵部110、及ILD特徵部110之間之金屬線106及介電硬遮罩（HM）線108。
在一實施例中，ILD材料，例如ILD特徵部110之材料，由介電或絕緣材料層構成、或包括介電或絕緣材料層。適合的介電材料之範例包括，但不限於，矽之氧化物（例如，二氧化矽（SiO2 ））、矽之氟化氧化物、矽之碳摻雜氧化物、本領域習知的各種低k介電材料、及其組合。ILD材料可藉由習知的技術形成，例如化學氣相沉積（CVD）、物理氣相沉積（PVD）、或藉由其他沉積方法。
在一實施例中，如通篇本說明書中所用，互連線材料，例如金屬線106之材料，由一或更多金屬或其他導電結構構成。常見範例為使用可包括或不包括阻擋層之銅線及結構，該阻擋層係在銅與周圍ILD材料之間。金屬互連線可包括阻擋層、不同金屬或合金之堆疊等。根據一些實施例，金屬線106可包含釕（Ru）金屬、鈷（Co）金屬、或銅（Cu）金屬或由其組成。
圖1B顯示圖1A在沉積ESL 112、第一金屬層114、及介電硬遮罩（HM）層116後之結構。在一範例中，介電HM線108及介電HM層116可包括相同材料。根據一些實施例，第一金屬層114可包含Ru金屬、Co金屬、或Cu金屬或由其組成。
圖1C顯示包含凹陷特徵部125之已圖案化的間隔物層118，該凹陷特徵部125在介電HM層116上形成。例如，可首先形成基於習知的微影之圖案，但隨後藉由使用間隔物遮罩（spacer mask）圖案化可將節距減半，如本領域中習知一般。更進一步地，原始節距可藉由第二輪之間隔物遮罩圖案化以減為四分之一。因此，已圖案化的間隔物層118可藉由自對準多重圖案化（SAMP）形成，例如自對準雙重圖案化（SADP）或自對準四重圖案化（SAQP）。在一些範例中，已圖案化的間隔物層118可包含SiO2 、SiN或SiO2 及SiN之組合。
圖1D顯示圖1C在沉積有機平坦化層（OPL）120、在OPL 120上形成抗反射塗層（ARC）122、並在ARC 122上形成包含凹陷特徵部126之已圖案化的光阻層124 之後之結構，其中該OPL 120填充已圖案化的間隔物層118中之凹陷特徵部125。ARC 122可包括SiARC層，該SiARC層可包括交聯且具有不同Si含量之含Si聚合物。目前用於微影之示例性SiARC層可具有17% Si（SiARC 17%）之矽含量或43% Si（SiARC 43%）之矽含量。根據本發明之一些實施例，SiARC層可具有在約10%與約40%之間之Si含量、或大於約40%之Si含量。OPL 120可包括光敏有機聚合物或蝕刻型有機化合物。例如，光敏有機聚合物可為聚丙烯酸酯樹脂、環氧樹脂、酚樹脂、聚醯胺樹脂、聚醯亞胺樹脂、不飽和聚酯樹脂、聚苯醚樹脂、聚苯硫醚樹脂或苯並環丁烯（ BCB）。可使用旋轉塗佈技術形成這些材料。OPL 120可為在固化製程期間中形成交聯結構之有機材料（例如，（ CHx ）n ）。可使用習知的微影及蝕刻方法以形成已圖案化的光阻層124。
圖1E顯示圖1D在自對準通孔形成蝕刻製程、並隨後去除已圖案化的光阻層124及ARC 122之後之結構，其中該自對準通孔形成蝕刻製程係形成自對準通孔128。自對準通孔128延伸穿過ILD特徵部110之間之介電硬遮罩（HM）線108，並停止在金屬線106其中一者上。在一範例中，自對準通孔128可具有20-40nm之寬度（大約為相鄰的ILD特徵部110之間之距離）及大約100nm之深度。本領域技術人員將容易理解，ILD特徵部110與ILD特徵部110之間之HM線108之間需要良好的蝕刻選擇性。
圖1F顯示圖1E在灰化製程之後之結構，該灰化製程去除OPL 120並打開已圖案化的間隔物層118中之凹陷特徵部125。
圖1G顯示圖1F在沉積第二金屬層142之後之結構，該第二金屬層142填充自對準通孔128及已圖案化的間隔物層118中之凹陷特徵部125。此外，第二金屬層142與金屬線106其中一者直接接觸並提供電連接。根據一些實施例，第二金屬層142可包含Ru金屬、Co金屬、或Cu金屬或由其組成。
圖1H顯示圖1G在回蝕刻或化學機械拋光（CMP）製程之後之結構，該回蝕刻或CMP製程係去除第二金屬層142在已圖案化的間隔物層118上方之部分。如圖1H中所示，第二金屬層142可凹陷至已圖案化的間隔物層118之頂部下方。
圖1I顯示圖1H在蝕刻製程之後之結構，該蝕刻製程係去除已圖案化的間隔物層118，從而在第二金屬層142之相鄰的特徵部之間形成凹陷特徵部132。
圖1J顯示圖1I在蝕刻製程之後之結構，該蝕刻製程使用第二金屬層142作為金屬硬遮罩以非等向性地蝕刻介電HM層116及第一金屬層114，從而使凹陷特徵部132延伸穿過第一金屬層114。已蝕刻的第一金屬層114係形成完全自對準互連線，儘管未顯示於圖1J，完全自對準互連線亦可存在於第二金屬層142之前面及後面。根據一實施例，不同金屬可用於第一金屬層114及第二金屬層142，以在第一金屬層114與第二金屬層142之間提供高蝕刻選擇性。根據另一實施例，藉由優化第二金屬層142相對於第一金屬層114之厚度，可將相同金屬用於第一金屬層114及第二金屬層142。例如，增加第二金屬層142相對於第一金屬層114之厚度，可允許將相同金屬用於第一金屬層114及第二金屬層142。
根據一實施例，圖1J中之基板100之進一步製程係示意性地顯示在圖1K-1O中。
圖1K顯示圖1J在沉積ILD層146之後之結構，該ILD層146填充凹陷特徵部132並且形成過載（overburden）在已圖案化的第二金屬層142上方。ILD層146可藉由例如旋轉塗佈沉積而形成。
圖1L顯示圖1K在平坦化製程（例如，化學機械平坦化（CMP））之後之結構，該平坦化製程係去除在介電HM層116上方之ILD層146及第二金屬層142。由於ILD層146係在第一金屬層114及第二金屬層142之電漿圖案化之後才被沉積及平坦化，因此避免了ILD層146之電漿損害。
圖1M顯示圖1L在回蝕刻製程之後之結構，該回蝕刻製程使第二金屬層142凹陷並在ILD層146之特徵部之間形成凹陷特徵部144。
圖1N顯示圖1M在沉積附加的介電硬遮罩（HM）層136之後之結構。在一範例中，附加的介電HM層136及介電HM層116可包含相同材料。
圖1O顯示圖1N在平坦化製程（例如，CMP）之後之結構，該平坦化製程係去除介電HM層116及ILD層146上方之附加的介電HM層136。
根據另一實施例，圖1J中基板100之進一步製程係示意性地顯示在圖 2A-2C中。圖1J中之基板100在圖2A中再現為基板200。
圖2B顯示圖2A在去除介電HM層116上方之第二金屬層142之後之結構。
圖2C顯示圖2B在沉積覆蓋層材料138之後之結構，該覆蓋層材料138在覆蓋層材料138下方之第一及第二金屬層114、142之間形成氣隙140。可使用氣相沉積非共形地沉積覆蓋層材料138，其中反應物不進入第一及第二金屬層114、142之間之空隙。
已在各種實施例中揭露用於後段製程（BEOL）結構之自對準互連線圖案化。前述已呈現之本發明實施例係出於說明及描述之目的。其並非意味著全面描述，或限制本發明於所揭露之特定形式。本說明書及隨後的請求項包含之術語僅用於描述之目的而不應被解釋為限制。熟悉相關技術者可鑑於以上教示瞭解許多修改及變化。熟悉此項技術者將明白圖中所示之各種組件之各種均等組合及替代。因此，本發明之範圍不受此詳細描述所限制，而是受到所附之請求項所限制。
100‧‧‧基板 102‧‧‧底層 104‧‧‧蝕刻停止層（ESL） 106‧‧‧金屬線 108‧‧‧介電硬遮罩（HM）線 110‧‧‧層間介電（ILD）特徵部 112‧‧‧蝕刻停止層（ESL） 114‧‧‧第一金屬層 116‧‧‧介電硬遮罩（HM）層 118‧‧‧已圖案化的間隔物層 120‧‧‧有機平坦化層（OPL） 122‧‧‧抗反射塗層（ARC） 124‧‧‧已圖案化的光阻層 125‧‧‧凹陷特徵部 126‧‧‧凹陷特徵部 128‧‧‧自對準通孔 132‧‧‧凹陷特徵部 136‧‧‧附加的介電硬遮罩（HM）層 138‧‧‧覆蓋層材料 140‧‧‧氣隙 142‧‧‧第二金屬層 144‧‧‧凹陷特徵部 146‧‧‧層間介電（ILD）層 200‧‧‧基板
併入本說明書中並構成其一部分之附圖顯示本發明實施例，並與上述給出之本發明之一般描述及下述給出之詳細描述一起用於解釋本發明。
圖1A-1O根據本發明實施例，顯示在消去式自對準互連線形成方法中代表各種操作之積體電路層之部分；及
圖2A-2C根據本發明實施例，顯示代表各種操作之積體電路層之部分。
100‧‧‧基板
102‧‧‧底層
104‧‧‧蝕刻停止層(ESL)
106‧‧‧金屬線
108‧‧‧介電硬遮罩(HM)線
110‧‧‧層間介電(ILD)特徵部
112‧‧‧ESL
114‧‧‧第一金屬層
116‧‧‧介電硬遮罩(HM)層
132‧‧‧凹陷特徵部
142‧‧‧第二金屬層

Claims (20)

  1. 一種製造積體電路之互連線結構之方法，該方法包括： 在一初始互連線結構上沉積一第一金屬層； 在該第一金屬層上形成包含複數凹陷特徵部之一已圖案化的間隔物層； 使用作為遮罩之該已圖案化的間隔物層中之一凹陷特徵部，蝕刻一自對準通孔在該第一金屬層中並進入該初始互連線結構； 以一第二金屬層填充該第一金屬層中之該通孔及該已圖案化的間隔物層中之該等凹陷特徵部； 去除該已圖案化的間隔物層；及 使用作為遮罩之該第二金屬層，蝕刻一凹陷特徵部在該第一金屬層中。
  2. 如申請專利範圍第1項之製造積體電路之互連線結構之方法，其中沉積該第一金屬層包括： 在該初始互連線結構上沉積一蝕刻停止層(ESL)， 在該蝕刻停止層上沉積該第一金屬層；及 在該第一金屬層上沉積一介電硬遮罩層。
  3. 如申請專利範圍第2項之製造積體電路之互連線結構之方法，其中該已圖案化的間隔物層係形成在該介電硬遮罩上。
  4. 如申請專利範圍第1項之製造積體電路之互連線結構之方法，其中該初始互連線結構包括複數層間介電特徵部、及該等層間介電特徵部之間之複數金屬線及複數介電硬遮罩線，其中該等介電硬遮罩線係設置在該等金屬線之頂部上。
  5. 如申請專利範圍第1項之製造積體電路之互連線結構之方法，更包括： 沉積一有機平坦化層（OPL），其填充該已圖案化的間隔物層中之該等凹陷特徵部； 在該OPL上沉積一抗反射塗層（ARC）；及 在該ARC上形成一已圖案化的光阻層。
  6. 如申請專利範圍第5項之製造積體電路之互連線結構之方法，更包括： 在該蝕刻該自對準通孔在該第一金屬層中之後，從該已圖案化的間隔物層中之該等凹陷特徵部去除該OPL。
  7. 如申請專利範圍第1項之製造積體電路之互連線結構之方法，更包括： 去除該第二金屬層在該已圖案化的間隔物層上方之一部分。
  8. 如申請專利範圍第2項之製造積體電路之互連線結構之方法，更包括： 沉積一層間介電層，其填充該第一金屬層中之該凹陷特徵部。
  9. 如申請專利範圍第8項之製造積體電路之互連線結構之方法，更包括： 去除該介電硬遮罩層上方之該層間介電層及該第二金屬層。
  10. 如申請專利範圍第9項之製造積體電路之互連線結構之方法，更包括： 使該第二金屬層凹陷至該層間介電層之一頂部下方。
  11. 如申請專利範圍第10項之製造積體電路之互連線結構之方法，更包括： 沉積一附加的介電硬遮罩層，其填充該第二金屬層之頂部上之該凹陷特徵部。
  12. 如申請專利範圍第11項之製造積體電路之互連線結構之方法，更包括： 去除該層間介電層之該頂部上方之該附加的介電硬遮罩層。
  13. 如申請專利範圍第1項之製造積體電路之互連線結構之方法，更包括： 去除該介電硬遮罩層上方之該第二金屬層。
  14. 如申請專利範圍第13項之製造積體電路之互連線結構之方法，更包括： 沉積一覆蓋層材料，以在該覆蓋層材料下方之該第一及該第二金屬層之間形成一氣隙。
  15. 一種製造積體電路之互連線結構之方法，該方法包括： 在一初始互連線結構上沉積一蝕刻停止層(ESL)、在該蝕刻停止層上沉積一第一金屬層、及在該第一金屬層上沉積一介電硬遮罩層； 在該介電硬遮罩層上形成包含複數凹陷特徵部之一已圖案化的間隔物層； 使用作為遮罩之該已圖案化的間隔物層中之一凹陷特徵部，蝕刻一自對準通孔在該第一金屬層中並進入該初始互連線結構； 以一第二金屬層填充該第一金屬層中之該通孔及該已圖案化的間隔物層中之該等凹陷特徵部； 去除該已圖案化的間隔物層； 使用作為遮罩之該第二金屬層，蝕刻一凹陷特徵部在該第一金屬層中；及 沉積一層間介電層，其填充該第一金屬層中之該凹陷特徵部。
  16. 如申請專利範圍第15項之製造積體電路之互連線結構之方法，更包括： 沉積一有機平坦化層(OPL)，其填充該已圖案化的間隔物層中之該等凹陷特徵部； 在該OPL上沉積一抗反射塗層(ARC)；及 在該ARC上形成一已圖案化的光阻層。
  17. 如申請專利範圍第15項之製造積體電路之互連線結構之方法，更包括： 在蝕刻該自對準通孔在該第一金屬層中之後，從該已圖案化的間隔物層中之該等凹陷特徵部去除該OPL。
  18. 如申請專利範圍第15項之製造積體電路之互連線結構之方法，更包括： 去除該第二金屬層在該已圖案化的間隔物層上方之一部分。
  19. 如申請專利範圍第15項之製造積體電路之互連線結構之方法，其中該初始互連線結構包括複數層間介電特徵部、及該等層間介電特徵部之間之複數金屬線及複數介電硬遮罩線，其中該等介電硬遮罩線係設置在該等金屬線之頂部上。
  20. 一種製造積體電路之互連線結構之方法，該方法包括： 在一初始互連線結構上沉積一蝕刻停止層(ESL)、在該蝕刻停止層上沉積一第一金屬層、及在該第一金屬層上沉積一介電硬遮罩層； 在該介電硬遮罩層上形成包含複數凹陷特徵部之一已圖案化的間隔物層； 沉積一有機平坦化層(OPL)，其填充該已圖案化的間隔物層中之該等凹陷特徵部； 在該OPL上沉積一抗反射塗層(ARC)； 在該ARC上形成一已圖案化的光阻層； 使用作為遮罩之該已圖案化的間隔物層中之一凹陷特徵部，蝕刻一自對準通孔在該第一金屬層中之並進入該初始互連線結構； 從該已圖案化的間隔物層中之該等凹陷特徵部去除該OPL； 以一第二金屬層填充該第一金屬層中之該通孔及該已圖案化的間隔物層中之該等凹陷特徵部； 去除該第二金屬層在該已圖案化的間隔物層上方之一部分； 去除該已圖案化的間隔物層； 使用作為遮罩之該第二金屬層，蝕刻一凹陷特徵部在該第一金屬層中；及 沉積一層間介電層，其填充該第一金屬層中之該凹陷特徵部。
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