CN102870212B - 具有自对准介电帽的互连结构的结构和制造方法 - Google Patents

具有自对准介电帽的互连结构的结构和制造方法 Download PDF

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CN102870212B
CN102870212B CN201180022085.8A CN201180022085A CN102870212B CN 102870212 B CN102870212 B CN 102870212B CN 201180022085 A CN201180022085 A CN 201180022085A CN 102870212 B CN102870212 B CN 102870212B
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ild layer
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CN102870212A (zh
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D·V·霍拉克
野上毅
S·波诺斯
C-c·杨
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GlobalFoundries Inc
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Abstract

提供具有自对准介电帽的互连结构。在衬底上形成至少一个金属化层级。在所述金属化层级上选择性沉积介电帽。

Description

具有自对准介电帽的互连结构的结构和制造方法
技术领域
本发明大体而言涉及互连结构的制造，更具体而言涉及在铜互连上的自对准介电帽的形成。
背景技术
介电帽被用于铜互连中作为铜扩散阻挡层。介电帽也可作为氧扩散阻挡层以防止铜的氧化。介电帽确保良好的电迁移性能；然而，常规使用的诸如碳化硅（SiC）和碳氮化硅（SiCN）的介电帽的介电常数高（例如，5-7）。该介电帽实质上促成电阻电容（Resistive Capacitive;RC）延迟。期望具有用于电容减小和性能改善的自对准介电帽。
发明内容
在本发明的第一方面中，一种形成器件的方法包括提供衬底。所述方法还包括在所述衬底上形成至少一个金属化层级（metallization level）。所述方法还包括在所述金属化层级上选择性沉积介电帽。
在本发明的第二方面中，一种形成器件的方法包括提供衬底。所述方法包括在所述衬底上方形成第一ILD层，其中所述第一ILD层具有顶面和第一开口。所述方法包括在所述第一开口中沉积第一金属衬里（liner）。所述方法包括在所述第一开口中形成第一金属化层级。所述方法包括在所述第一ILD层的所述顶面上形成第一帽层。所述方法包括在所述第一帽层上方形成第二ILD层，其中所述第二ILD层具有顶面和延伸到所述第一金属化层级中的第二开口。所述方法包括在所述顶面上和所述第二开口中沉积第二金属衬里。所述方法包括在所述第二开口中形成第二金属化层级。所述方法包括执行对所述第二金属化层级的CMP，其中所述第二金属化层级的顶部与所述第二金属衬里的顶部共面（co-planar）。所述方法还包括在所述第二金属化层级上形成第二帽层。所述方法还包括从所述第二ILD层的所述顶面去除所述第二金属衬里。
在本发明的又一方面中，一种器件包括衬底。所述器件还包括在所述衬底上的至少一个金属化层级。所述器件还包括在所述金属化层级上选择性沉积的介电帽。
在本发明的再一方面中，一种器件包括衬底。所述器件包括形成在所述衬底上方的第一ILD层，其中所述第一ILD层具有顶面和第一开口。所述器件包括沉积在所述第一开口中的第一金属衬里。所述器件包括形成在所述第一开口中的第一金属化层级。所述器件包括形成在所述第一ILD层的所述顶面上的第一帽层。所述器件包括形成在所述第一帽层上方的第二ILD层，其中所述第二ILD层具有顶面和延伸到所述第一金属化层级中的第二开口。所述器件包括沉积在所述第二开口中的第二金属衬里。所述器件还包括形成在所述第二开口中的第二金属化层级，其中所述第二金属化层级与所述第二ILD层的所述顶面共面。所述器件还包括形成在所述第二金属化层级上的第二帽层。
附图说明
参考附图在下面的详细说明中说明本发明，其中附图示出了本发明的示例性实施例的非限制性实例。
图1示出了根据本发明的实施例的起始互连结构；
图2示出了根据本发明的实施例的处理步骤和中间互连结构；
图3示出了根据本发明的实施例的处理步骤和最终互连结构；
图4示出了根据本发明的第二实施例的最终互连结构；
图5示出了根据本发明的第三实施例的最终互连结构；以及
图6示出了根据本发明的第四实施例的最终互连结构。
具体实施方式
图1示出了根据本发明的实施例的起始互连结构10。可以使用常规工艺在衬底15上形成互连结构10。互连结构10可包括下伏的（underlying）金属化层级或器件层级20、帽层25、层级间介电层（ILD）30、金属衬里31以及铜金属化层级32。下伏的金属化层级20可包括但不限于铜（Cu）、铝（Al）、钨（W）和其它低电阻率半导体兼容金属。帽层25可包括但不限于碳氮化硅（SiCN）、氮化硅（SiN）和碳化硅（SiC）。ILD层30可包括但不限于：碳掺杂的氧化硅（SiCOH）、多孔SiCOH以及氧化硅（SiO）。金属衬里31可包括但不限于氮化钽（TaN）和钽（Ta）的叠层。执行化学机械平面化（CMP）以去除铜，CMP在场衬里区域停止。将衬里31a保持在所述场区域中。衬里31a不被抛光。在衬里抛光之前停止CMP。
参考图2，可在铜金属化层级32上选择性沉积介电帽35。发现等离子体增强化学气相沉积（PECVD）碳氮化硅（SiCN）（例如nBLoK）具有选择特性。观察到nBLoK在TaN和/或Ta上不会大量沉积。由于介电帽沉积的选择性本质，nBLoK仅在铜金属化层级32上沉积，且不会在衬里31a上沉积。通过PECVD、化学气相沉积（CVD）或原子层沉积（ALD）或任何已知的或后来开发的工艺进行沉积的其它介电帽材料（例如SiN和SiC）可被调整为具有该选择性沉积特性。介电帽35的厚度可近似为5nm至100nm。
参考图3，在场区域中回蚀刻且去除衬里31a。可使用低偏置（bias）含氟等离子体或任何已知的或后来开发的工艺。可使用氟基化学物质（例如四氟化碳（CF4））反应离子蚀刻（RIE）来去除衬里31a。该化学物质还可去除介电帽35的一部分。这可作为影响介电帽35的初始沉积厚度的因素。还可使用氟化氙（XeF）气体去除衬里31a。XeF气体将衬里31a选择性地去除到介电帽35。随后可沉积下一层级ILD且使用常规工艺继续进行该构造。
图4示出了根据本发明的第二实施例的互连结构400。对图3所示的结构执行ILD 30的选择性蚀刻。这导致在铜金属化层级32的侧壁衬里31之间形成沟槽38。该沟槽可具有范围为约50nm至500nm的深度。该沟槽可具有约2:1的纵横比（深度:宽度比）。自对准介电帽35用作该选择性蚀刻的蚀刻硬掩膜。ILD 30可为碳掺杂的氧化硅（SiCOH）、多孔SiCOH或氧化硅（SiO）。对于SiCOH，可执行灰化蚀刻。对于SiO，可执行DHF。可执行非保形的（non-conformal）下一层级ILD沉积，从而产生气隙（air-gap）形状。铜金属化层级32受到保护。可使用如在共同受让的、名称为“Sub-lithographic Dimensioned Air Gap Formation and RelatedStructure”、序列号为US20090200636A1的美国专利公开中所述的工艺来形成气隙形状，通过引用将该美国专利公开的全部内容并入本文中。
图5示出了根据本发明的第三实施例的互连结构500。可沉积包括但不限于氮化硅（SiN）的非选择性保形介电材料，且随后使用常规工艺对该保形介电材料进行回蚀刻，产生间隔物（spacer）39。间隔物厚度（所沉积的）可大于或等于侧壁衬里31的厚度。间隔物39在ILD蚀刻期间为侧壁衬里31提供保护。
图6示出了根据本发明的第四实施例的互连结构600。在选择性介电帽35的沉积之前，可在铜金属化层级32中形成凹陷（recess）40。凹陷40可具有范围为约5nm至100nm的深度。介电帽35的厚度可近似为5nm至100nm。可在仅铜CMP之后形成凹陷40（如图1所示）。这产生跨过不同线宽的均匀的介电帽厚度，且提供增加的互连可靠性。在介电帽35的选择性沉积之后，可以使用相同工艺进行衬里回蚀刻（如图3所示）。可使用如在共同受让的、名称为“Copper Recess Process with Applicationto Selective Capping and Electroless Plating”的序列号为6,975,032的美国专利中所述的工艺来形成铜凹陷，通过引用将该美国专利的全部内容并入本文中。
如上所述的方法被用于集成电路芯片的制造。所产生的集成电路芯片可由制造者以裸晶片（raw wafer）形式（即，作为具有多个未封装的芯片的单个晶片）、作为裸管芯（bare die）或以封装形式进行分配。在后一种情况下，芯片被安装在单芯片封装（例如，具有被附到母板的引线的塑料载体，或其它较高级载体）或多芯片封装（例如，具有表面互连和掩埋互连中的一者或两者的陶瓷载体）中。在任何情况下，芯片随后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为（a）诸如母板的中间产品或者（b）最终产品的任一者的部分。最终产品可为包括集成电路芯片的任何产品，其范围为从玩具和其它低端应用到具有显示器、键盘或其它输入装置和中央处理器的高级计算机产品。
对本发明的描述是为了示例和说明的目的而给出的，但并不旨在穷举或以所公开的形式对发明进行限制。在不脱离本发明的范围和精神的情况下，许多修改和变更对于本领域技术人员而言是显而易见的。选择且描述该实施例以便最好地解释本发明的原理和实际应用，且使本领域其他普通技术人员理解具有各种修改的各种实施例的本发明，这些修改适于设想的具体使用。

Claims (18)

1.一种形成器件的方法，包括：
提供衬底；
在所述衬底上方形成第一ILD层，其中所述第一ILD层具有顶面和第一开口；
在所述第一开口中沉积第一金属衬里；
在所述第一开口中形成第一金属化层级；
在所述第一ILD层的所述顶面上形成第一帽层；
在所述第一帽层上方形成第二ILD层，其中所述第二ILD层具有顶面和延伸到所述第一金属化层级中的第二开口；
在所述顶面上和所述第二开口中沉积第二金属衬里；
在所述第二开口中形成第二金属化层级；
执行对所述第二金属化层级的CMP，其中所述第二金属化层级的顶部与所述第二金属衬里的顶部共面；
在所述第二金属化层级上形成第二帽层；以及
从所述第二ILD层的所述顶面去除所述第二金属衬里。
2.根据权利要求1的方法，其中所述在所述第二金属化层级上形成第二帽层的步骤包括选择性沉积介电帽。
3.根据权利要求2的方法，其中通过化学气相沉积(CVD)和原子层沉积(ALD)中的一者选择性沉积所述介电帽。
4.根据权利要求3的方法，其中所述介电帽选自碳氮化硅(SiCN)、氮化硅(SiN)和碳化硅(SiC)。
5.根据权利要求1的方法，其中所述从所述第二ILD层的所述顶面去除所述第二金属衬里的步骤包括执行四氟化碳(CF4)反应离子蚀刻(RIE)及氟化氙(XeF)气体蚀刻中的一者。
6.根据权利要求1的方法，其中所述第二ILD层选自碳掺杂的氧化硅(SiCOH)、多孔SiCOH和氧化硅(SiO)。
7.根据权利要求1的方法，其中所述第二金属衬里为氮化钽(TaN)和钽(Ta)的叠层中的一种。
8.根据权利要求1的方法，其中所述第二金属化层级为铜。
9.根据权利要求1的方法，还包括邻近所述第二帽层形成间隔物。
10.根据权利要求1的方法，还包括在所述在所述第二金属化层级上形成第二帽层的步骤之前在所述第二ILD层的所述顶面下方的所述第二金属化层级中形成凹陷。
11.根据权利要求1的方法，还包括在所述第二ILD层中形成至少一个沟槽。
12.根据权利要求11的方法，其中所述在所述第二ILD层中形成至少一个沟槽的步骤包括执行对所述第二ILD层的选择性蚀刻。
13.一种器件，包括：
衬底；
第一ILD层，其形成在所述衬底上方，其中所述第一ILD层具有顶面和第一开口；
第一金属衬里，其沉积在所述第一开口中；
第一金属化层级，其形成在所述第一开口中；
第一帽层，其形成在所述第一ILD层的所述顶面上；
第二ILD层，其形成在所述第一帽层上方，其中所述第二ILD层具有顶面和延伸到所述第一金属化层级中的第二开口；
第二金属衬里，其沉积在所述第二开口中；
第二金属化层级，其形成在所述第二开口中，其中所述第二金属化层级与所述第二ILD层的所述顶面共面；以及
第二帽层，其形成在所述第二金属化层级上。
14.根据权利要求13的器件，其中所述第二金属化层级包括铜。
15.根据权利要求13的器件，还包括邻近所述第二帽层形成的间隔物。
16.根据权利要求13的器件，其中所述第二金属化层级在所述第二ILD层的所述顶面下方凹陷。
17.根据权利要求13的器件，还包括在所述第二ILD层中形成的至少一个沟槽。
18.根据权利要求13的器件，其中所述第二帽层选自碳氮化硅(SiCN)、氮化硅(SiN)和碳化硅(SiC)。
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