TW200737227A - Memory device and method having multiple address, data and command buses - Google Patents

Memory device and method having multiple address, data and command buses

Info

Publication number
TW200737227A
TW200737227A TW095127051A TW95127051A TW200737227A TW 200737227 A TW200737227 A TW 200737227A TW 095127051 A TW095127051 A TW 095127051A TW 95127051 A TW95127051 A TW 95127051A TW 200737227 A TW200737227 A TW 200737227A
Authority
TW
Taiwan
Prior art keywords
data
buses
address
internal
multiplexer
Prior art date
Application number
TW095127051A
Other languages
English (en)
Inventor
James Cullum
Jeffrey Wright
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200737227A publication Critical patent/TW200737227A/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/107Serial-parallel conversion of data or prefetch
TW095127051A 2005-07-26 2006-07-25 Memory device and method having multiple address, data and command buses TW200737227A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/190,270 US7283418B2 (en) 2005-07-26 2005-07-26 Memory device and method having multiple address, data and command buses

Publications (1)

Publication Number Publication Date
TW200737227A true TW200737227A (en) 2007-10-01

Family

ID=37694116

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095127051A TW200737227A (en) 2005-07-26 2006-07-25 Memory device and method having multiple address, data and command buses

Country Status (7)

Country Link
US (2) US7283418B2 (zh)
EP (1) EP1913597A4 (zh)
JP (1) JP4852692B2 (zh)
KR (1) KR100973629B1 (zh)
CN (1) CN101401166B (zh)
TW (1) TW200737227A (zh)
WO (1) WO2007015773A2 (zh)

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US8904109B2 (en) 2011-01-28 2014-12-02 Freescale Semiconductor, Inc. Selective cache access control apparatus and method thereof
US8533400B2 (en) 2011-01-28 2013-09-10 Freescale Semiconductor, Inc. Selective memory access to different local memory ports and method thereof
US8756405B2 (en) 2011-05-09 2014-06-17 Freescale Semiconductor, Inc. Selective routing of local memory accesses and device thereof
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US9190133B2 (en) 2013-03-11 2015-11-17 Micron Technology, Inc. Apparatuses and methods for a memory die architecture including an interface memory
US9064562B2 (en) * 2013-04-03 2015-06-23 Hewlett-Packard Development Company, L.P. Memory module having multiple memory banks selectively connectable to a local memory controller and an external memory controller
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US10387046B2 (en) 2016-06-22 2019-08-20 Micron Technology, Inc. Bank to bank data transfer
US10236038B2 (en) 2017-05-15 2019-03-19 Micron Technology, Inc. Bank to bank data transfer
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US11017128B2 (en) * 2018-05-22 2021-05-25 Seagate Technology Llc Data security using bit transposition during memory accesses
US11347860B2 (en) 2019-06-28 2022-05-31 Seagate Technology Llc Randomizing firmware loaded to a processor memory
TWI762852B (zh) * 2020-01-03 2022-05-01 瑞昱半導體股份有限公司 記憶體裝置及其操作方法
US11080219B1 (en) 2020-01-15 2021-08-03 Micron Technology, Inc. Addressing scheme for a memory system
CN114420173B (zh) * 2022-01-19 2024-02-06 长鑫存储技术有限公司 一种存储结构和半导体存储器

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Also Published As

Publication number Publication date
US7283418B2 (en) 2007-10-16
US7548483B2 (en) 2009-06-16
EP1913597A2 (en) 2008-04-23
US20070025173A1 (en) 2007-02-01
EP1913597A4 (en) 2009-08-05
CN101401166B (zh) 2012-02-29
CN101401166A (zh) 2009-04-01
KR100973629B1 (ko) 2010-08-02
JP2009503682A (ja) 2009-01-29
KR20080030112A (ko) 2008-04-03
JP4852692B2 (ja) 2012-01-11
US20080043565A1 (en) 2008-02-21
WO2007015773A3 (en) 2008-08-14
WO2007015773A2 (en) 2007-02-08

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