TW200632992A - Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide - Google Patents

Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Info

Publication number
TW200632992A
TW200632992A TW095100286A TW95100286A TW200632992A TW 200632992 A TW200632992 A TW 200632992A TW 095100286 A TW095100286 A TW 095100286A TW 95100286 A TW95100286 A TW 95100286A TW 200632992 A TW200632992 A TW 200632992A
Authority
TW
Taiwan
Prior art keywords
bonding
bonded
hydrophilic
orientation
interfacial
Prior art date
Application number
TW095100286A
Other languages
English (en)
Chinese (zh)
Inventor
Souza Joel P De
John A Ott
Alexander Reznicek
Devendra K Sadana
Katherine L Saenger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200632992A publication Critical patent/TW200632992A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
TW095100286A 2005-01-07 2006-01-04 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide TW200632992A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/031,165 US8138061B2 (en) 2005-01-07 2005-01-07 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Publications (1)

Publication Number Publication Date
TW200632992A true TW200632992A (en) 2006-09-16

Family

ID=36653805

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095100286A TW200632992A (en) 2005-01-07 2006-01-04 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Country Status (4)

Country Link
US (3) US8138061B2 (https=)
JP (1) JP5043333B2 (https=)
CN (1) CN1818154A (https=)
TW (1) TW200632992A (https=)

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FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
WO2008096194A1 (en) 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
JP5256625B2 (ja) * 2007-03-05 2013-08-07 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの評価方法
JP5433927B2 (ja) * 2007-03-14 2014-03-05 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
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FR2918792B1 (fr) * 2007-07-10 2010-04-23 Soitec Silicon On Insulator Procede de traitement de defauts d'interface dans un substrat.
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FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
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FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
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Also Published As

Publication number Publication date
US20060154442A1 (en) 2006-07-13
US8138061B2 (en) 2012-03-20
CN1818154A (zh) 2006-08-16
US20090298258A1 (en) 2009-12-03
JP2006191029A (ja) 2006-07-20
US8053330B2 (en) 2011-11-08
US20120156861A1 (en) 2012-06-21
JP5043333B2 (ja) 2012-10-10

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