SG161151A1 - Soi substrate and method for manufacturing the same - Google Patents

Soi substrate and method for manufacturing the same

Info

Publication number
SG161151A1
SG161151A1 SG200906654-9A SG2009066549A SG161151A1 SG 161151 A1 SG161151 A1 SG 161151A1 SG 2009066549 A SG2009066549 A SG 2009066549A SG 161151 A1 SG161151 A1 SG 161151A1
Authority
SG
Singapore
Prior art keywords
substrate
single crystal
semiconductor layer
crystal semiconductor
soi substrate
Prior art date
Application number
SG200906654-9A
Other languages
English (en)
Inventor
Hideto Ohnuma
Eiji Higa
Original Assignee
Semiconductor Energy Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of SG161151A1 publication Critical patent/SG161151A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
SG200906654-9A 2008-10-22 2009-10-05 Soi substrate and method for manufacturing the same SG161151A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008271676 2008-10-22

Publications (1)

Publication Number Publication Date
SG161151A1 true SG161151A1 (en) 2010-05-27

Family

ID=42107980

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200906654-9A SG161151A1 (en) 2008-10-22 2009-10-05 Soi substrate and method for manufacturing the same

Country Status (6)

Country Link
US (1) US8313989B2 (ja)
JP (1) JP5613397B2 (ja)
KR (1) KR101631456B1 (ja)
CN (1) CN101728312B (ja)
SG (1) SG161151A1 (ja)
TW (1) TWI483295B (ja)

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CN105428302A (zh) * 2014-09-17 2016-03-23 中国科学院上海微系统与信息技术研究所 利用低温剥离技术制备绝缘体上材料的方法
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CN106409650B (zh) * 2015-08-03 2019-01-29 沈阳硅基科技有限公司 一种硅片直接键合方法
US10280504B2 (en) 2015-09-25 2019-05-07 Apple Inc. Ion-implanted, anti-reflective layer formed within sapphire material
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US10943813B2 (en) 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
US11232975B2 (en) * 2018-09-26 2022-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate having dielectric structures that increase interface bonding strength
CN110098145B (zh) * 2019-04-03 2021-08-17 京东方科技集团股份有限公司 单晶硅薄膜及其制作方法
CN110349843B (zh) * 2019-07-26 2021-12-21 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、生物识别器件、显示装置
US10950631B1 (en) 2019-09-24 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor-on-insulator wafer having a composite insulator layer
CN114447257B (zh) * 2022-01-17 2023-11-28 深圳市华星光电半导体显示技术有限公司 柔性基板剥离方法

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Also Published As

Publication number Publication date
JP2010123931A (ja) 2010-06-03
US20100096720A1 (en) 2010-04-22
TWI483295B (zh) 2015-05-01
KR101631456B1 (ko) 2016-06-17
KR20100044706A (ko) 2010-04-30
CN101728312A (zh) 2010-06-09
US8313989B2 (en) 2012-11-20
JP5613397B2 (ja) 2014-10-22
TW201030817A (en) 2010-08-16
CN101728312B (zh) 2014-04-09

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