SG148930A1 - Process for fabricating a structure for epitaxy without an exclusion zone - Google Patents

Process for fabricating a structure for epitaxy without an exclusion zone

Info

Publication number
SG148930A1
SG148930A1 SG200804104-8A SG2008041048A SG148930A1 SG 148930 A1 SG148930 A1 SG 148930A1 SG 2008041048 A SG2008041048 A SG 2008041048A SG 148930 A1 SG148930 A1 SG 148930A1
Authority
SG
Singapore
Prior art keywords
seed layer
crystalline growth
epitaxy
fabricating
growth seed
Prior art date
Application number
SG200804104-8A
Other languages
English (en)
Inventor
Chantal Arena
Fabrice Letertre
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG148930A1 publication Critical patent/SG148930A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1002—Methods of surface bonding and/or assembly therefor with permanent bending or reshaping or surface deformation of self sustaining lamina
    • Y10T156/1043—Subsequent to assembly
    • Y10T156/1044—Subsequent to assembly of parallel stacked sheets only
SG200804104-8A 2007-06-06 2008-05-29 Process for fabricating a structure for epitaxy without an exclusion zone SG148930A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0755512A FR2917232B1 (fr) 2007-06-06 2007-06-06 Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion.

Publications (1)

Publication Number Publication Date
SG148930A1 true SG148930A1 (en) 2009-01-29

Family

ID=38895687

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200804104-8A SG148930A1 (en) 2007-06-06 2008-05-29 Process for fabricating a structure for epitaxy without an exclusion zone

Country Status (8)

Country Link
US (2) US7902045B2 (zh)
EP (1) EP2031654A3 (zh)
JP (1) JP2008303137A (zh)
KR (1) KR101007273B1 (zh)
CN (1) CN101355013B (zh)
FR (1) FR2917232B1 (zh)
SG (1) SG148930A1 (zh)
TW (1) TW200849337A (zh)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5496540B2 (ja) * 2008-04-24 2014-05-21 株式会社半導体エネルギー研究所 半導体基板の作製方法
US7947523B2 (en) * 2008-04-25 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing photoelectric conversion device
FR2943174B1 (fr) * 2009-03-12 2011-04-15 Soitec Silicon On Insulator Adaptation du parametre de maille d'une couche de materiau contraint
MY158571A (en) 2009-03-13 2016-10-14 Saint Gobain Ceramics Chemical mechanical planarization using nanodiamond
EP2246882B1 (en) * 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate
JPWO2011052320A1 (ja) * 2009-10-30 2013-03-14 住友電気工業株式会社 炭化珪素基板の製造方法および炭化珪素基板
WO2011052321A1 (ja) * 2009-10-30 2011-05-05 住友電気工業株式会社 炭化珪素基板の製造方法および炭化珪素基板
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
EP2330697A1 (en) * 2009-12-07 2011-06-08 S.O.I.Tec Silicon on Insulator Technologies Semiconductor device having an InGaN layer
FR2954585B1 (fr) * 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
US8148189B2 (en) * 2010-06-30 2012-04-03 Twin Creeks Technologies, Inc. Formed ceramic receiver element adhered to a semiconductor lamina
KR101492350B1 (ko) * 2010-09-27 2015-02-10 가부시끼가이샤 도시바 GaN 베이스 반도체 결정 성장용 다결정 질화알루미늄 기재 및 그것을 이용한 GaN 베이스 반도체의 제조 방법
FR2968678B1 (fr) 2010-12-08 2015-11-20 Soitec Silicon On Insulator Procédés pour former des matériaux a base de nitrure du groupe iii et structures formées par ces procédés
US9023721B2 (en) 2010-11-23 2015-05-05 Soitec Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
FR2968830B1 (fr) 2010-12-08 2014-03-21 Soitec Silicon On Insulator Couches matricielles ameliorees pour le depot heteroepitaxial de materiaux semiconducteurs de nitrure iii en utilisant des procedes hvpe
US9142412B2 (en) * 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
JP2012106907A (ja) * 2011-08-11 2012-06-07 Sumitomo Electric Ind Ltd ＧａＮ系膜の製造方法
JP2012106906A (ja) * 2011-08-11 2012-06-07 Sumitomo Electric Ind Ltd ＧａＮ系膜の製造方法
JP6019928B2 (ja) * 2011-10-07 2016-11-02 住友電気工業株式会社 ＧａＮ系膜の製造方法およびそれに用いられる複合基板
JP6130995B2 (ja) * 2012-02-20 2017-05-17 サンケン電気株式会社 エピタキシャル基板及び半導体装置
WO2014004079A1 (en) 2012-06-29 2014-01-03 Corning Incorporated Glass-ceramic substrates for semiconductor processing
EP2933824B1 (en) * 2014-04-14 2021-08-18 Nxp B.V. Substrate arrangement
CN107406335B (zh) * 2016-03-22 2020-12-08 住友电气工业株式会社 陶瓷基板、层叠体和saw器件
CN109716508B (zh) * 2016-06-24 2023-08-15 克罗米斯有限公司 多晶陶瓷衬底及其制造方法
EP3516002B1 (en) 2016-09-23 2022-01-05 Saint-Gobain Ceramics & Plastics, Inc. Chemical mechanical planarization slurry and method for forming same
US10622468B2 (en) * 2017-02-21 2020-04-14 QROMIS, Inc. RF device integrated on an engineered substrate
JP7237464B2 (ja) * 2018-05-24 2023-03-13 キオクシア株式会社 半導体装置の製造方法
JP6583897B1 (ja) * 2018-05-25 2019-10-02 ▲らん▼海精研股▲ふん▼有限公司 セラミック製静電チャックの製造方法
CN109183146B (zh) * 2018-10-17 2020-08-07 哈尔滨工业大学 一种利用电感耦合等离子体技术消除单晶金刚石籽晶表面缺陷的方法
CN111183513A (zh) * 2019-04-19 2020-05-19 福建晶安光电有限公司 一种用于制作光电半导体芯片的方法及其所使用的键合晶圆
KR102506449B1 (ko) * 2020-04-23 2023-03-07 삼성전자주식회사 표시 장치
US11705537B2 (en) 2020-04-23 2023-07-18 Samsung Electronics Co.,. Ltd. Display device and method of manufacturing light emitting device
CN111962149A (zh) * 2020-08-11 2020-11-20 长沙新材料产业研究院有限公司 一种生长金刚石厚膜的籽晶及其制备方法与应用
CN112071741B (zh) * 2020-08-13 2023-03-24 深圳市奥谱太赫兹技术研究院 一种iii族氮化物层结构及其制备方法、晶体管
FR3114910A1 (fr) * 2020-10-06 2022-04-08 Soitec Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
EP4297066A1 (en) * 2021-02-22 2023-12-27 Samsung Electronics Co., Ltd. Display device and method for manufacturing light-emitting element
CN113223928B (zh) * 2021-04-16 2024-01-12 西安电子科技大学 一种基于转移键合的氧化镓外延生长方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6328796B1 (en) 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
JP4031910B2 (ja) * 1999-04-20 2008-01-09 直江津電子工業株式会社 シリコンエピタキシャルウェーハの製造方法
JP2001031494A (ja) * 1999-07-21 2001-02-06 Nippon Steel Corp シリコン単結晶ウエーハの製造方法
US6690043B1 (en) * 1999-11-26 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
DE10045539A1 (de) * 2000-09-13 2002-03-21 Halfen Gmbh & Co Kg Verbindungsteil für Montageschienen
FR2817394B1 (fr) 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US7407869B2 (en) * 2000-11-27 2008-08-05 S.O.I.Tec Silicon On Insulator Technologies Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
US6497763B2 (en) 2001-01-19 2002-12-24 The United States Of America As Represented By The Secretary Of The Navy Electronic device with composite substrate
JP2002356398A (ja) * 2001-06-01 2002-12-13 Sumitomo Electric Ind Ltd 窒化ガリウムウエハ
JP2003165798A (ja) * 2001-11-28 2003-06-10 Hitachi Cable Ltd 窒化ガリウム単結晶基板の製造方法、窒化ガリウム単結晶のエピタキシャル成長自立基板、及びその上に形成したデバイス素子
FR2835097B1 (fr) 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
FR2842651B1 (fr) * 2002-07-17 2005-07-08 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support
JP2004075500A (ja) * 2002-08-22 2004-03-11 Seiko Instruments Inc サファイア、偏光板付きサファイヤ、表示装置及びサファイアの製造方法
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
FR2857983B1 (fr) 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2857982B1 (fr) 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US6794760B1 (en) * 2003-09-05 2004-09-21 Intel Corporation Integrated circuit interconnect
FR2860248B1 (fr) * 2003-09-26 2006-02-17 Centre Nat Rech Scient Procede de realisation de substrats autosupportes de nitrures d'elements iii par hetero-epitaxie sur une couche sacrificielle
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
US7767541B2 (en) * 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods

Also Published As

Publication number Publication date
KR20080107256A (ko) 2008-12-10
JP2008303137A (ja) 2008-12-18
TW200849337A (en) 2008-12-16
EP2031654A3 (fr) 2009-06-17
CN101355013B (zh) 2011-09-14
EP2031654A2 (fr) 2009-03-04
KR101007273B1 (ko) 2011-01-13
US20110037075A1 (en) 2011-02-17
US20080303118A1 (en) 2008-12-11
US7902045B2 (en) 2011-03-08
FR2917232A1 (fr) 2008-12-12
US8154022B2 (en) 2012-04-10
CN101355013A (zh) 2009-01-28
FR2917232B1 (fr) 2009-10-09

Similar Documents

Publication Publication Date Title
SG148930A1 (en) Process for fabricating a structure for epitaxy without an exclusion zone
TW200608455A (en) Semiconductor film manufacturing method and substrate manufacturing method
TW200746262A (en) Method of manufacturing nitride semiconductor substrate and composite material substrate
TW200729343A (en) Method for fabricating controlled stress silicon nitride films
SG166717A1 (en) A method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of sige deposited on the front side
GB2434687B (en) Thin film transistor array substrate system and method for manufacturing
WO2012057517A3 (ko) 화합물 반도체 장치 및 화합물 반도체 제조방법
WO2015027080A3 (en) Selective deposition of diamond in thermal vias
EP2080823A4 (en) GROUP III ELEMENT NITRIDE BASE SUBSTRATE, SUBSTRATE HAVING AN EPITAXIAL LAYER, METHOD FOR MANUFACTURING SUCH SUBSTRATES, AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT
WO2008063337A3 (en) Semiconductor-on-diamond devices and associated methods
WO2009131363A3 (ko) 점착 필름 및 이를 사용한 백그라인딩 방법
EP2514858A4 (en) GROUP III NITRIDE CRYSTAL SUBSTRATE, GROUP III NITRIDE CRYSTAL SUBSTRATE HAVING AN EPITAXIAL LAYER, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF
EP3879011A4 (en) SIC SEMICONDUCTOR SUBSTRATE, METHOD AND DEVICE FOR MAKING IT
TW200723364A (en) Process for transfer of a thin layer formed in a substrate with vacancy clusters
WO2009116830A3 (ko) 반도체 소자 및 그 제조방법
TW200943393A (en) A semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
MX2010007723A (es) Dispositivos fotovoltaicos tratados con plasma.
GB2541146A (en) Method of manufacturing a germanium-on-insulator substrate
EP3886161A4 (en) SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR PRODUCTION THEREOF
TW200725818A (en) Wafer-level chip package process
EP3879010A4 (en) SIC SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCTION THEREOF AND DEVICE FOR PRODUCTION THEREOF
EP3936644A4 (en) METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE IN SIC AND DEVICE FOR MANUFACTURING THEREOF
EP3862134A4 (en) INDIUM PHOSPHIDE SUBSTRATE, EPITACTIC SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING INDIUM PHOSPHIDE SUBSTRATE
EP3862133A4 (en) INDIUM PHOSPHIDE SUBSTRATE, EPITACTIC SEMICONDUCTOR WAFER AND METHOD OF MAKING AN INDIUM PHOSPHIDE SUBSTRATE
EP3862132A4 (en) INDIUM PHOSPHIDE SUBSTRATE, EPITACTIC SEMICONDUCTOR WAFER AND METHOD OF MAKING AN INDIUM PHOSPHIDE SUBSTRATE