SG11201709420PA - Method for producing soi wafer - Google Patents

Method for producing soi wafer

Info

Publication number
SG11201709420PA
SG11201709420PA SG11201709420PA SG11201709420PA SG11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA
Authority
SG
Singapore
Prior art keywords
soi wafer
producing soi
producing
wafer
soi
Prior art date
Application number
SG11201709420PA
Other languages
English (en)
Inventor
Isao Yokokawa
Hiroji Aga
Norihiro Kobayashi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201709420PA publication Critical patent/SG11201709420PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
SG11201709420PA 2015-06-15 2016-03-08 Method for producing soi wafer SG11201709420PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015120424A JP6380245B2 (ja) 2015-06-15 2015-06-15 Ｓｏｉウェーハの製造方法
PCT/JP2016/001235 WO2016203677A1 (ja) 2015-06-15 2016-03-08 Ｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG11201709420PA true SG11201709420PA (en) 2017-12-28

Family

ID=57545735

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201709420PA SG11201709420PA (en) 2015-06-15 2016-03-08 Method for producing soi wafer

Country Status (8)

Country Link
US (1) US10204824B2 (enrdf_load_stackoverflow)
EP (1) EP3309820B1 (enrdf_load_stackoverflow)
JP (1) JP6380245B2 (enrdf_load_stackoverflow)
KR (1) KR102327330B1 (enrdf_load_stackoverflow)
CN (1) CN107615445B (enrdf_load_stackoverflow)
SG (1) SG11201709420PA (enrdf_load_stackoverflow)
TW (1) TWI685019B (enrdf_load_stackoverflow)
WO (1) WO2016203677A1 (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN109037031B (zh) * 2018-07-11 2021-11-19 华东师范大学 一种掺镍氧化铜薄膜晶体管及制备方法
CN110739285A (zh) * 2019-10-30 2020-01-31 北京工业大学 硅基金属中间层化合物半导体晶圆的结构及制备方法
KR102456461B1 (ko) 2020-11-26 2022-10-19 현대제철 주식회사 딥러닝을 이용한 철강 미세 조직 분석 방법 및 시스템
CN112582332A (zh) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
JP4123861B2 (ja) * 2002-08-06 2008-07-23 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP4603865B2 (ja) * 2004-12-01 2010-12-22 信越化学工業株式会社 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
JP2007317988A (ja) * 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2008028070A (ja) * 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
JP5245380B2 (ja) * 2007-06-21 2013-07-24 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP5135935B2 (ja) * 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5531642B2 (ja) * 2010-01-22 2014-06-25 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5477277B2 (ja) * 2010-12-20 2014-04-23 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法
JP5673572B2 (ja) * 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Also Published As

Publication number Publication date
TW201643938A (zh) 2016-12-16
EP3309820B1 (en) 2020-01-29
EP3309820A1 (en) 2018-04-18
CN107615445A (zh) 2018-01-19
KR20180016394A (ko) 2018-02-14
WO2016203677A1 (ja) 2016-12-22
US20180144975A1 (en) 2018-05-24
CN107615445B (zh) 2020-10-30
TWI685019B (zh) 2020-02-11
JP2017005201A (ja) 2017-01-05
KR102327330B1 (ko) 2021-11-17
US10204824B2 (en) 2019-02-12
JP6380245B2 (ja) 2018-08-29
EP3309820A4 (en) 2019-01-23

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