NL1009351C2 - Werkwijze voor het vormen van contactpennen van een halfgeleiderinrichting. - Google Patents

Werkwijze voor het vormen van contactpennen van een halfgeleiderinrichting. Download PDF

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Publication number
NL1009351C2
NL1009351C2 NL1009351A NL1009351A NL1009351C2 NL 1009351 C2 NL1009351 C2 NL 1009351C2 NL 1009351 A NL1009351 A NL 1009351A NL 1009351 A NL1009351 A NL 1009351A NL 1009351 C2 NL1009351 C2 NL 1009351C2
Authority
NL
Netherlands
Prior art keywords
insulating layer
layer
etching
conductive layer
forming
Prior art date
Application number
NL1009351A
Other languages
English (en)
Dutch (nl)
Other versions
NL1009351A1 (nl
Inventor
Bo-Un Yoon
In-Kwon Jeong
Won-Seong Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL1009351A1 publication Critical patent/NL1009351A1/xx
Application granted granted Critical
Publication of NL1009351C2 publication Critical patent/NL1009351C2/nl

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
NL1009351A 1997-06-11 1998-06-09 Werkwijze voor het vormen van contactpennen van een halfgeleiderinrichting. NL1009351C2 (nl)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR19970024146 1997-06-11
KR19970024146 1997-06-11
KR19980014850 1998-04-25
KR1019980014850A KR100266749B1 (ko) 1997-06-11 1998-04-25 반도체 장치의 콘택 플러그 형성 방법

Publications (2)

Publication Number Publication Date
NL1009351A1 NL1009351A1 (nl) 1998-12-14
NL1009351C2 true NL1009351C2 (nl) 2000-02-23

Family

ID=26632828

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1009351A NL1009351C2 (nl) 1997-06-11 1998-06-09 Werkwijze voor het vormen van contactpennen van een halfgeleiderinrichting.

Country Status (9)

Country Link
US (1) US6121146A (de)
JP (1) JPH1131745A (de)
KR (1) KR100266749B1 (de)
CN (1) CN1127123C (de)
DE (1) DE19826031C2 (de)
FR (1) FR2764734B1 (de)
GB (1) GB2326281B (de)
NL (1) NL1009351C2 (de)
TW (1) TW396576B (de)

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US6727170B2 (en) * 1998-02-16 2004-04-27 Renesas Technology Corp. Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
JPH11233621A (ja) * 1998-02-16 1999-08-27 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6218306B1 (en) * 1998-04-22 2001-04-17 Applied Materials, Inc. Method of chemical mechanical polishing a metal layer
KR100268459B1 (ko) * 1998-05-07 2000-10-16 윤종용 반도체 장치의 콘택 플러그 형성 방법
JP2000294640A (ja) 1999-04-09 2000-10-20 Oki Electric Ind Co Ltd 半導体装置の製造方法
FR2795236B1 (fr) * 1999-06-15 2002-06-28 Commissariat Energie Atomique Procede de realisation d'interconnexions notamment en cuivre pour dispositifs micro-electroniques
US6225226B1 (en) * 1999-12-13 2001-05-01 Taiwan Semiconductor Manufacturing Company Method for processing and integrating copper interconnects
US6420267B1 (en) * 2000-04-18 2002-07-16 Infineon Technologies Ag Method for forming an integrated barrier/plug for a stacked capacitor
KR100399064B1 (ko) * 2000-06-30 2003-09-26 주식회사 하이닉스반도체 반도체 소자 제조방법
KR100373356B1 (ko) * 2000-06-30 2003-02-25 주식회사 하이닉스반도체 반도체장치 제조방법
DE10208714B4 (de) * 2002-02-28 2006-08-31 Infineon Technologies Ag Herstellungsverfahren für einen Kontakt für eine integrierte Schaltung
JP4034115B2 (ja) * 2002-05-14 2008-01-16 富士通株式会社 半導体装置の製造方法
TW519858B (en) * 2002-05-20 2003-02-01 Via Tech Inc Printing method for manufacturing through hole and circuit of circuit board
JP3918933B2 (ja) * 2002-12-06 2007-05-23 Ｊｓｒ株式会社 化学機械研磨ストッパー、その製造方法および化学機械研磨方法
CN1315189C (zh) * 2003-05-06 2007-05-09 旺宏电子股份有限公司 字符线交接点布局结构
US6909131B2 (en) * 2003-05-30 2005-06-21 Macronix International Co., Ltd. Word line strap layout structure
DE102006030265B4 (de) * 2006-06-30 2014-01-30 Globalfoundries Inc. Verfahren zum Verbessern der Planarität einer Oberflächentopographie in einer Mikrostruktur
KR100955838B1 (ko) 2007-12-28 2010-05-06 주식회사 동부하이텍 반도체 소자 및 그 배선 제조 방법
DE102010028460B4 (de) 2010-04-30 2014-01-23 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zum Herstellen eines Halbleiterbauelements mit einer reduzierten Defektrate in Kontakten, das Austauschgateelektrodenstrukturen unter Anwendung einer Zwischendeckschicht aufweist
CN103160781B (zh) * 2011-12-16 2015-07-01 中国科学院兰州化学物理研究所 模具钢表面多层梯度纳米复合类金刚石薄膜的制备方法
CN104233222B (zh) * 2014-09-26 2016-06-29 厦门大学 一种直接在Si衬底上生长六方氮化硼二维薄膜的方法
KR102406583B1 (ko) * 2017-07-12 2022-06-09 삼성전자주식회사 반도체 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0305691A1 (de) * 1987-08-17 1989-03-08 International Business Machines Corporation Verfahren zur Ausbildung einer Vielzahl leitender Zapfen in einer Isolierschicht
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
EP0540444A1 (de) * 1991-10-30 1993-05-05 International Business Machines Corporation Diamant- oder diamantähnliche Ätzstopschicht für chemisch-mechanisches Polieren
EP0660393A1 (de) * 1993-12-23 1995-06-28 STMicroelectronics, Inc. Verfahren und Dielektricumstruktur zur Erleichterung des Metalüberätzung ohne Beschädigung des Zwischendielektricum
JPH07221292A (ja) * 1994-02-04 1995-08-18 Citizen Watch Co Ltd 半導体装置およびその製造方法
EP0774777A1 (de) * 1995-11-14 1997-05-21 International Business Machines Corporation Verfahren zum chemisch mechanischen Polieren eines Elektronikteils

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WO1989000503A1 (en) * 1987-07-21 1989-01-26 Storage Technology Corporation Control of printer functions via band id
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5124780A (en) * 1991-06-10 1992-06-23 Micron Technology, Inc. Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
DE4311484A1 (de) * 1992-04-09 1993-10-14 Micron Technology Inc Verfahren zur Bildung einer leitfähigen Struktur auf der Oberfläche eines Substrats
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5573633A (en) * 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
US5773314A (en) * 1997-04-25 1998-06-30 Motorola, Inc. Plug protection process for use in the manufacture of embedded dynamic random access memory (DRAM) cells
US5915189A (en) * 1997-08-22 1999-06-22 Samsung Electronics Co., Ltd. Manufacturing method for semiconductor memory device having a storage node with surface irregularities

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0305691A1 (de) * 1987-08-17 1989-03-08 International Business Machines Corporation Verfahren zur Ausbildung einer Vielzahl leitender Zapfen in einer Isolierschicht
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
EP0540444A1 (de) * 1991-10-30 1993-05-05 International Business Machines Corporation Diamant- oder diamantähnliche Ätzstopschicht für chemisch-mechanisches Polieren
EP0660393A1 (de) * 1993-12-23 1995-06-28 STMicroelectronics, Inc. Verfahren und Dielektricumstruktur zur Erleichterung des Metalüberätzung ohne Beschädigung des Zwischendielektricum
JPH07221292A (ja) * 1994-02-04 1995-08-18 Citizen Watch Co Ltd 半導体装置およびその製造方法
EP0774777A1 (de) * 1995-11-14 1997-05-21 International Business Machines Corporation Verfahren zum chemisch mechanischen Polieren eines Elektronikteils

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"DIAMOND-LIKE FILMS AS A BARRIER TO CHEMICAL-MECHANICAL POLISH", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 35, no. 1B, 1 June 1992 (1992-06-01), pages 211 - 213, XP000309034, ISSN: 0018-8689 *
PATENT ABSTRACTS OF JAPAN vol. 199, no. 511 26 December 1995 (1995-12-26) *

Also Published As

Publication number Publication date
GB2326281A (en) 1998-12-16
CN1127123C (zh) 2003-11-05
TW396576B (en) 2000-07-01
JPH1131745A (ja) 1999-02-02
KR100266749B1 (ko) 2000-09-15
NL1009351A1 (nl) 1998-12-14
FR2764734A1 (fr) 1998-12-18
DE19826031A1 (de) 1998-12-17
GB9812552D0 (en) 1998-08-05
US6121146A (en) 2000-09-19
FR2764734B1 (fr) 2002-11-08
DE19826031C2 (de) 2002-12-05
KR19990006403A (ko) 1999-01-25
CN1203444A (zh) 1998-12-30
GB2326281B (en) 2000-07-12

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AD1A A request for search or an international type search has been filed
RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)

Effective date: 19991022

PD2B A search report has been drawn up
MK Patent expired because of reaching the maximum lifetime of a patent

Effective date: 20180608