MXPA01008580A - Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos. - Google Patents
Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos.Info
- Publication number
- MXPA01008580A MXPA01008580A MXPA01008580A MXPA01008580A MXPA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A
- Authority
- MX
- Mexico
- Prior art keywords
- sub
- substrate
- integrated circuit
- filler material
- package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
- H10W76/42—Fillings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/261,849 US20020014688A1 (en) | 1999-03-03 | 1999-03-03 | Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials |
| PCT/US2000/003242 WO2000052756A1 (en) | 1999-03-03 | 2000-02-08 | A controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MXPA01008580A true MXPA01008580A (es) | 2002-04-24 |
Family
ID=22995146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MXPA01008580A MXPA01008580A (es) | 1999-03-03 | 2000-02-08 | Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos. |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US20020014688A1 (https=) |
| JP (1) | JP2002538626A (https=) |
| KR (1) | KR100522383B1 (https=) |
| CN (1) | CN1191627C (https=) |
| AU (1) | AU2986000A (https=) |
| MX (1) | MXPA01008580A (https=) |
| WO (1) | WO2000052756A1 (https=) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020014688A1 (en) * | 1999-03-03 | 2002-02-07 | Suresh Ramalingam | Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials |
| US20090279275A1 (en) * | 2008-05-09 | 2009-11-12 | Stephen Peter Ayotte | Method of attaching an integrated circuit chip to a module |
| CN102105971B (zh) * | 2009-04-24 | 2013-05-22 | 松下电器产业株式会社 | 半导体封装元器件的安装方法和安装结构体 |
| US8686749B2 (en) * | 2010-04-30 | 2014-04-01 | International Business Machines Corporation | Thermal interface material, test structure and method of use |
| JP2012049175A (ja) * | 2010-08-24 | 2012-03-08 | Toshiba Corp | 半導体装置の製造方法 |
| KR20120040536A (ko) | 2010-10-19 | 2012-04-27 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| US9559064B2 (en) * | 2013-12-04 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in package-on-package structures |
| US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
| US9524956B2 (en) | 2014-10-31 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure and method |
| WO2017180482A1 (en) * | 2016-04-11 | 2017-10-19 | Paradromics, Inc. | Neural-interface probe and methods of packaging the same |
| WO2018183967A1 (en) | 2017-03-30 | 2018-10-04 | Paradromics, Inc. | Patterned microwire bundles and methods of producing the same |
| EP3682471B1 (en) * | 2017-09-15 | 2023-11-08 | Cryptography Research, Inc. | Packaging techniques for backside mesh connectivity |
| CN110660752A (zh) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | 半导体装置封装体及其制造方法 |
| US11075133B2 (en) | 2018-06-29 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill structure for semiconductor packages and methods of forming the same |
| US12171995B1 (en) | 2021-10-07 | 2024-12-24 | Paradromics, Inc. | Methods for improved biocompatibility for human implanted medical devices |
| JP7594195B2 (ja) | 2022-07-13 | 2024-12-04 | 日亜化学工業株式会社 | 発光装置の製造方法及び発光装置 |
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| US6238948B1 (en) * | 1999-03-03 | 2001-05-29 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material |
| US20020014688A1 (en) * | 1999-03-03 | 2002-02-07 | Suresh Ramalingam | Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials |
-
1999
- 1999-03-03 US US09/261,849 patent/US20020014688A1/en not_active Abandoned
-
2000
- 2000-02-08 JP JP2000603092A patent/JP2002538626A/ja active Pending
- 2000-02-08 KR KR10-2001-7011227A patent/KR100522383B1/ko not_active Expired - Lifetime
- 2000-02-08 AU AU29860/00A patent/AU2986000A/en not_active Abandoned
- 2000-02-08 MX MXPA01008580A patent/MXPA01008580A/es not_active IP Right Cessation
- 2000-02-08 CN CNB00804578XA patent/CN1191627C/zh not_active Expired - Fee Related
- 2000-02-08 WO PCT/US2000/003242 patent/WO2000052756A1/en not_active Ceased
-
2001
- 2001-06-05 US US09/874,666 patent/US7141448B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO2000052756A1 (en) | 2000-09-08 |
| CN1350702A (zh) | 2002-05-22 |
| CN1191627C (zh) | 2005-03-02 |
| KR100522383B1 (ko) | 2005-10-19 |
| KR20010108306A (ko) | 2001-12-07 |
| US20020014688A1 (en) | 2002-02-07 |
| US20020017728A1 (en) | 2002-02-14 |
| AU2986000A (en) | 2000-09-21 |
| JP2002538626A (ja) | 2002-11-12 |
| US7141448B2 (en) | 2006-11-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG | Grant or registration | ||
| MM | Annulment or lapse due to non-payment of fees |