JP3235454B2 - 電子部品の接合方法 - Google Patents

電子部品の接合方法

Info

Publication number
JP3235454B2
JP3235454B2 JP07611196A JP7611196A JP3235454B2 JP 3235454 B2 JP3235454 B2 JP 3235454B2 JP 07611196 A JP07611196 A JP 07611196A JP 7611196 A JP7611196 A JP 7611196A JP 3235454 B2 JP3235454 B2 JP 3235454B2
Authority
JP
Japan
Prior art keywords
electronic component
adhesive
substrate
conductive adhesive
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07611196A
Other languages
English (en)
Other versions
JPH09266232A (ja
Inventor
省二 酒見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP07611196A priority Critical patent/JP3235454B2/ja
Priority to US08/824,054 priority patent/US5817542A/en
Publication of JPH09266232A publication Critical patent/JPH09266232A/ja
Application granted granted Critical
Publication of JP3235454B2 publication Critical patent/JP3235454B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
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    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/8159—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、接着剤を用いて電
子部品に備えられたバンプを基板の回路パターンに接合
する電子部品の接合方法に関するものである。
【０００２】
【従来の技術】近年、電子部品には金属からなるバンプ
を備えたものが出現し、この電子部品のバンプを導電性
を有する接着剤を用いて基板の回路パターンに接合する
工法が実用化するに至っている。
【０００３】次に図３を参照しながら、従来の電子部品
の接合方法について説明する。図３（ａ）において、１
はガラスエポキシ又はセラミックスなどからなる基板、
２，３は基板１の表面に形成された回路パターンであ
り、これらの回路パターン２，３には導電性を有する接
着剤４が塗布される。また５は半導体チップを主体とす
る電子部品であり、その下面には複数のバンプ６，７が
突設されている。
【０００４】そして、従来の電子部品の接合方法では、
図３（ｂ）に示すように、バンプ６，７を接着剤４に接
触させ、１５０°Ｃ以上に加温して接着剤４を硬化させ
る。これにより、バンプ６，７を回路パターン２，３に
固着させると共に、両者を電気的に接続するというもの
である。
【０００５】このため、図３（ｂ）に示すように、硬化
温度に達して接着剤４が硬化した後、室温に戻すと、電
子部品５はほとんど変形しないが基板１はかなり変形し
て反ってしまう。したがって図３（ｃ）あるいは図３
（ｃ）のＡ部を拡大した図３（ｄ）に示すように、基板
１と電子部品５の接合部にあたるところの、硬化した接
着剤４と回路パターン２との界面付近に大きな応力が作
用し、接着剤４が破断してしまい、接合不良を発生する
ことがあった。
【０００６】
【発明が解決しようとする課題】そこで本発明は、接合
不良を抑制できる電子部品の接合方法を提供することを
目的とする。
【０００７】
【課題を解決するための手段】本発明の電子部品の接合
方法は、バンプと回路パターンとの間に導電性接着剤を
介在させ、導電性接着剤が硬化する温度以上に加熱し室
温に戻すまでの間に、電子部品と基板との間に絶縁性接
着剤を注入し、絶縁性接着剤を硬化させるものである。
【０００８】
【発明の実施の形態】請求項１に記載の電子部品の接合
方法は、バンプと回路パターンとの間に導電性接着剤を
介在させ、導電性接着剤が硬化する温度以上に加熱し室
温に戻すまでの間に、電子部品と基板との間に絶縁性接
着剤を注入し、絶縁性接着剤を硬化させることとしてい
るので、高温時において、バンプと回路パターンとが導
電性接着剤で固着されるだけでなく、電子部品自体が絶
縁性接着剤によって基板に固着される。したがって、こ
の後、室温に戻しても、電子部品は基板に固着されたま
まの状態となるから、基板が電子部品に対して変形する
ことはなく、またバンプや導電性接着剤の周囲が絶縁性
接着剤によって補強されていることになる。
【０００９】このため、導電性接着剤に基板の変形に伴
う応力が集中することはなく、接合不良を回避すること
ができる。
【００１０】次に図面を参照しながら、本発明の実施の
形態を説明する。図１は、本発明の第１の実施の形態に
おける電子部品の接合方法の工程説明図である。なお図
中、従来の構成を示す図３と同様の構成要素について
は、同一符号を付すことにより説明を省略する。
【００１１】第１の実施の形態では、まず図１（ａ）に
示すように、電子部品５にバンプ６，７を形成する。
【００１２】次に、基板１の回路パターン２，３又はバ
ンプ６，７の先端に導電性接着剤９を塗布し、加熱手段
を備えた位置決めテーブル８に基板１を載置し、基板１
を加熱しておく。また、バンプ６，７が下向きになるよ
うに、電子部品５を移載ヘッド１０で保持し、バンプ
６，７を導電性接着剤９上に載せ、下向きに加圧する。
【００１３】そして、導電性接着剤９が硬化する温度
（通常１５０〜１８０°Ｃ）まで加熱する。この加熱手
段として、本形態では位置決めテーブル８と移載ヘッド
１０にヒータを備えているが、導電性接着剤９を上述の
ように加熱できるものであれば、どのような加熱手段を
用いてもよい。
【００１４】次に図１（ｃ）に示すように、室温に戻す
前に、ディスペンサ１１を用いて、基板１と電子部品５
との間に絶縁性接着剤１２を注入する。そして、上述し
た加熱手段によって、絶縁性接着剤１２を硬化させる。
【００１５】このように、絶縁性接着剤１２が硬化する
と、導電性接着剤９の周囲が補強されると共に、電子部
品５自体が基板１に固着される。したがってこの後、室
温に戻しても、基板１は電子部品５に対して変形するこ
とができず、接合不良を回避できる。
【００１６】次に本発明の第２の実施の形態について説
明する。この形態では、まず第１の実施の形態と同様
に、バンプ６，７を形成する（図２（ａ））。
【００１７】また図２（ｂ）に示すように、基板１のう
ち、回路パターン２，３がない箇所にバンプ６，７より
もやや厚く形成され、未だ硬化していない絶縁性接着剤
１３を載置する。又は、絶縁性接着剤１３を電子部品５
に載置しておき、電子部品５の移載時に絶縁性接着剤１
３を基板に搭載する。この絶縁性接着剤１３は、通常ブ
ロック状あるいはシート状に形成されるが、ペースト状
であっても良い。
【００１８】そして、第１の実施の形態と同様に、電子
部品５の移載と加熱を行う。即ち、図２（ｃ）に示すよ
うに、このとき絶縁性接着剤１３は、基板１と電子部品
２との両方に密着的に挟まれる。そして加熱により、高
温時に、導電性接着剤９と絶縁性接着剤１３は、硬化
し、電子部品５は基板１に固着される。
【００１９】したがって、第１の実施の形態と同様に、
室温に戻しても基板１は電子部品５に対して変形するこ
とができず、接合不良を回避できる。
【００２０】
【発明の効果】本発明の電子部品の接合方法は、バンプ
と回路パターンとの間に導電性接着剤を介在させ、導電
性接着剤が硬化する温度以上に加熱し室温に戻すまでの
間に、電子部品と基板との間に絶縁性接着剤を注入し、
絶縁性接着剤を硬化させるものであるから、高温時に電
子部品が基板に固着されてしまい、その後室温に戻した
際に基板は、ほとんど変形できず、導電性接着剤の破断
による接合不良を抑制することができる。
【図面の簡単な説明】
【図１】（ａ）本発明の第１の実施の形態における電子
部品の接合方法の工程説明図 （ｂ）本発明の第１の実施の形態における電子部品の接
合方法の工程説明図 （ｃ）本発明の第１の実施の形態における電子部品の接
合方法の工程説明図
【図２】（ａ）本発明の第２の実施の形態における電子
部品の接合方法の工程説明図 （ｂ）本発明の第２の実施の形態における電子部品の接
合方法の工程説明図 （ｃ）本発明の第２の実施の形態における電子部品の接
合方法の工程説明図
【図３】（ａ）従来の電子部品の接合方法の工程説明図 （ｂ）従来の電子部品の接合方法の工程説明図 （ｃ）従来の電子部品の接合方法の工程説明図 （ｄ）従来の電子部品の接合方法の工程説明図
【符号の説明】
１ 基板 ２，３ 回路パターン ５ 電子部品 ６，７ バンプ ９ 導電性接着剤
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 H05K 3/34 H05K 3/36

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】電子部品に形成されたバンプを基板の回路
    パターンに接合する電子部品の接合方法であって、前記
    バンプと前記回路パターンとの間に導電性接着剤を介在
    させ、前記導電性接着剤が硬化する温度以上に加熱し室
    温に戻すまでの間に、前記電子部品と前記基板との間に
    絶縁性接着剤を注入し、前記絶縁性接着剤を硬化させる
    ことを特徴とする電子部品の接合方法。
  2. 【請求項２】電子部品に形成されたバンプを基板の回路
    パターンに接合する電子部品の接合方法であって、前記
    基板のうち前記回路パターンを除く箇所に加熱により硬
    化する絶縁性接着剤を載せ、前記バンプと前記回路パタ
    ーンとの間に導電性接着剤を介在させ、前記導電性接着
    剤が硬化する温度以上に加熱し室温に戻すまでの間に、
    前記導電性接着剤と前記絶縁性接着剤とを硬化させるこ
    とを特徴とする電子部品の接合方法。
JP07611196A 1996-03-29 1996-03-29 電子部品の接合方法 Expired - Fee Related JP3235454B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP07611196A JP3235454B2 (ja) 1996-03-29 1996-03-29 電子部品の接合方法
US08/824,054 US5817542A (en) 1996-03-29 1997-03-21 Method for bonding electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07611196A JP3235454B2 (ja) 1996-03-29 1996-03-29 電子部品の接合方法

Publications (2)

Publication Number Publication Date
JPH09266232A JPH09266232A (ja) 1997-10-07
JP3235454B2 true JP3235454B2 (ja) 2001-12-04

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998242A (en) * 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US6528345B1 (en) 1999-03-03 2003-03-04 Intel Corporation Process line for underfilling a controlled collapse
US20020014688A1 (en) 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
JP2001257239A (ja) * 2000-03-13 2001-09-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3918098B2 (ja) * 2002-11-14 2007-05-23 株式会社村田製作所 回路モジュールの製造方法
US20050121806A1 (en) * 2003-12-04 2005-06-09 White Electronic Designs Corporation Method for attaching circuit elements
US8657992B2 (en) 2008-06-27 2014-02-25 Odbond, Llc Method and apparatus for layer bonding of display assembly
CN103085437B (zh) * 2011-11-02 2016-04-06 宸鸿科技(厦门)有限公司 贴合结构、具有该贴合结构之电子装置及其贴合方法
EP2747129A1 (en) * 2012-12-18 2014-06-25 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Curing a heat-curable material in an embedded curing zone

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EP0393206B1 (en) * 1988-10-14 1996-05-08 Matsushita Electric Industrial Co., Ltd. Image sensor and method of producing the same
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5482896A (en) * 1993-11-18 1996-01-09 Eastman Kodak Company Light emitting device comprising an organic LED array on an ultra thin substrate and process for forming same
US5579573A (en) * 1994-10-11 1996-12-03 Ford Motor Company Method for fabricating an undercoated chip electrically interconnected to a substrate
US5627108A (en) * 1995-06-21 1997-05-06 Compaq Computer Corporation Solder paste and glue dot-based methods of securing components to a printed circuit board

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