JP3918098B2 - 回路モジュールの製造方法 - Google Patents
回路モジュールの製造方法 Download PDFInfo
- Publication number
- JP3918098B2 JP3918098B2 JP2003326638A JP2003326638A JP3918098B2 JP 3918098 B2 JP3918098 B2 JP 3918098B2 JP 2003326638 A JP2003326638 A JP 2003326638A JP 2003326638 A JP2003326638 A JP 2003326638A JP 3918098 B2 JP3918098 B2 JP 3918098B2
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- Prior art keywords
- resin
- chip component
- substrate
- circuit module
- dispenser needle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 229920005989 resin Polymers 0.000 claims description 116
- 239000011347 resin Substances 0.000 claims description 116
- 239000000758 substrate Substances 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 19
- 239000000126 substance Substances 0.000 claims description 8
- 239000005871 repellent Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 5
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 230000002940 repellent Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
2 チップ部品
3 接合電極
4 台座
5 ディスペンサニードル
6 樹脂
7 樹脂溜まり
8 容器
9 減圧装置
Claims (8)
- チップ部品をフリップチップ実装した基板上に、ディスペンサニードルから樹脂を供給して、前記チップ部品の側面と前記ディスペンサニードルとの側面との間に樹脂溜りを形成する工程と、
前記樹脂溜りの樹脂を前記チップ部品と前記基板との隙間に充填する工程と、を含み、
前記ディスペンサニードルの側面が、撥水性の物質によりコーティングされていることを特徴とする回路モジュールの製造方法。 - チップ部品をフリップチップ実装した基板を、熱源を内蔵する台座に設置して加熱する工程と、
前記基板上にディスペンサニードルから樹脂を供給して、前記チップ部品の側面と前記ディスペンサニードルの側面との間に樹脂溜りを形成する工程と、
前記樹脂溜りの樹脂を前記チップ部品と前記基板との隙間に充填する工程と、を含み、
前記ディスペンサニードルの側面が、撥水性の物質によりコーティングされていることを特徴とする回路モジュールの製造方法。 - 前記チップ部品の側面と前記ディスペンサニードルの側面との間に毛細管現象によって樹脂が溜まる速度が、前記チップ部品と前記基板との隙間に前記樹脂が充填される速度よりも速いことを特徴とする、請求項1あるいは請求項2に記載の回路モジュールの製造方法。
- 前記樹脂溜まりの樹脂を前記チップ部品と前記基板との隙間に充填する工程において、
前記樹脂溜まりの樹脂が前記隙間に充填されるまで前記ディスペンサニードルの位置が固定されつづけていることを特徴とする、請求項1ないし請求項3のいずれか一項に記載の回路モジュールの製造方法。 - 前記樹脂溜まりを形成する工程において、前記チップ部品の側面と前記ディスペンサニードルの側面との距離が0.15mmよりも小さいことを特徴とする、請求項1ないし請求項4のいずれか一項に記載の回路モジュールの製造方法。
- 前記チップ部品が、ベアチップであることを特徴とする、請求項1ないし請求項5のいずれか一項に記載の回路モジュールの製造方法。
- 前記回路モジュールが、高周波回路モジュールであることを特徴とする、請求項1ないし請求項6のいずれか一項に記載の回路モジュールの製造方法。
- 前記樹脂が、エポキシ系樹脂であることを特徴とする、請求項1ないし請求項7のいずれか一項に記載の回路モジュールの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003326638A JP3918098B2 (ja) | 2002-11-14 | 2003-09-18 | 回路モジュールの製造方法 |
US10/705,823 US7022554B2 (en) | 2002-11-14 | 2003-11-13 | Method for fabricating circuit module |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002330686 | 2002-11-14 | ||
JP2003326638A JP3918098B2 (ja) | 2002-11-14 | 2003-09-18 | 回路モジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004179623A JP2004179623A (ja) | 2004-06-24 |
JP3918098B2 true JP3918098B2 (ja) | 2007-05-23 |
Family
ID=32301829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003326638A Expired - Fee Related JP3918098B2 (ja) | 2002-11-14 | 2003-09-18 | 回路モジュールの製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7022554B2 (ja) |
JP (1) | JP3918098B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4871093B2 (ja) * | 2006-11-01 | 2012-02-08 | 武蔵エンジニアリング株式会社 | 液体材料の充填方法、装置およびプログラム |
US8193036B2 (en) * | 2010-09-14 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming mold underfill using dispensing needle having same width as semiconductor die |
JP5962285B2 (ja) * | 2012-07-19 | 2016-08-03 | 日亜化学工業株式会社 | 発光装置およびその製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5120678A (en) * | 1990-11-05 | 1992-06-09 | Motorola Inc. | Electrical component package comprising polymer-reinforced solder bump interconnection |
JPH08241900A (ja) | 1995-03-02 | 1996-09-17 | Matsushita Electric Ind Co Ltd | フリップチップ実装体の樹脂封止方法 |
JPH08306717A (ja) | 1995-05-09 | 1996-11-22 | Matsushita Electric Ind Co Ltd | 樹脂封止方法 |
US5766982A (en) * | 1996-03-07 | 1998-06-16 | Micron Technology, Inc. | Method and apparatus for underfill of bumped or raised die |
JP3235454B2 (ja) * | 1996-03-29 | 2001-12-04 | 松下電器産業株式会社 | 電子部品の接合方法 |
US5821456A (en) * | 1996-05-01 | 1998-10-13 | Motorola, Inc. | Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same |
US5866442A (en) * | 1997-01-28 | 1999-02-02 | Micron Technology, Inc. | Method and apparatus for filling a gap between spaced layers of a semiconductor |
US5998242A (en) * | 1997-10-27 | 1999-12-07 | Lsi Logic Corporation | Vacuum assisted underfill process and apparatus for semiconductor package fabrication |
KR100643105B1 (ko) * | 1998-05-06 | 2006-11-13 | 텍사스 인스트루먼츠 인코포레이티드 | 플립-칩 전자 디바이스를 언더필링하는 저응력 방법 및 장치 |
US6207475B1 (en) * | 1999-03-30 | 2001-03-27 | Industrial Technology Research Institute | Method for dispensing underfill and devices formed |
JP3423897B2 (ja) * | 1999-04-01 | 2003-07-07 | 宮崎沖電気株式会社 | 半導体装置の製造方法 |
US6475828B1 (en) * | 1999-11-10 | 2002-11-05 | Lsi Logic Corporation | Method of using both a non-filled flux underfill and a filled flux underfill to manufacture a flip-chip |
US6391762B1 (en) * | 1999-11-12 | 2002-05-21 | Motorola, Inc. | Method of forming a microelectronic assembly with a particulate free underfill material and a microelectronic assembly incorporation the same |
US6498054B1 (en) * | 2000-06-02 | 2002-12-24 | Siliconware Precision Industries Co., Ltd. | Method of underfilling a flip-chip semiconductor device |
US6391683B1 (en) * | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package structure and process for fabricating the same |
US6391682B1 (en) * | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Method of performing flip-chip underfill in a wire-bonded chip-on-chip ball-grid array integrated circuit package module |
US6632690B2 (en) * | 2001-09-10 | 2003-10-14 | Advanced Micro Devices, Inc. | Method of fabricating reliable laminate flip-chip assembly |
JP3865606B2 (ja) * | 2001-09-28 | 2007-01-10 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6724091B1 (en) * | 2002-10-24 | 2004-04-20 | Intel Corporation | Flip-chip system and method of making same |
US6610559B2 (en) * | 2001-11-16 | 2003-08-26 | Indium Corporation Of America | Integrated void-free process for assembling a solder bumped chip |
-
2003
- 2003-09-18 JP JP2003326638A patent/JP3918098B2/ja not_active Expired - Fee Related
- 2003-11-13 US US10/705,823 patent/US7022554B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20040097095A1 (en) | 2004-05-20 |
JP2004179623A (ja) | 2004-06-24 |
US7022554B2 (en) | 2006-04-04 |
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