CN103117229B - 制作电子组件的方法 - Google Patents

制作电子组件的方法 Download PDF

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Publication number
CN103117229B
CN103117229B CN201210427823.3A CN201210427823A CN103117229B CN 103117229 B CN103117229 B CN 103117229B CN 201210427823 A CN201210427823 A CN 201210427823A CN 103117229 B CN103117229 B CN 103117229B
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China
Prior art keywords
circuit element
nude film
substrate
liquid
underfill
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Expired - Fee Related
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CN201210427823.3A
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English (en)
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CN103117229A (zh
Inventor
大卫·K·富特
詹姆士·D·格蒂
赵建钢
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Nordson Corp
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Nordson Corp
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

本发明涉及制作电子组件的方法。在本发明的实施例中，提供一种用于制作具有衬底和多个电路元件的电子组件的方法。所述方法包括：在所述衬底上形成液体屏障；在所述液体屏障一侧放置第一电路元件；以及在所述液体屏障的相对侧放置第二电路元件。向所述第一电路元件施加液体。所述方法还包括：使用所述液体屏障防止施加至所述第一电路元件的所述液体污染所述第二电路元件，使得能够最小化所述第一和第二电路元件之间的间隔。

Description

制作电子组件的方法
技术领域
本发明总体上涉及制作电子组件的方法。
背景技术
电子组件可能包括一个或更多个芯片以及每个芯片所附接的封装载体（诸如衬底、电路板或引线框架）。事实上，电子组件存在于如今构造的每个电子装置中。每个芯片都包括使用晶片和促进装置与外部环境的连接的互连结构制作的一个或更多个集成电路。互连结构包括称为接合焊盘的导电触头阵列，以及使装置和接合焊盘耦合的居间金属平面。将从晶片切割而成的裸片安装在封装载体上，以形成电子组件。
每个裸片均包括与封装载体上的接合焊盘连接的接合焊盘，以提供外部电连接。在通过倒装芯片安装形成的电子组件中，通过焊球或焊块将裸片上的接合焊盘电连接和物理连接至衬底诸如封装载体上的相应的接合焊盘阵列。通常，焊块与裸片和/或衬底上的接合焊盘对准，并且施加回流工艺，以产生焊接头形式的物理和电连接。倒装芯片安装工艺导致裸片和衬底之间的间隙，该间隙反映焊接头的存在。
经常地，将底部填料引入到裸片和衬底之间的间隙中，并且使其包围焊块。底部填料为电绝缘材料，其加强裸片和衬底之间的机械连接，并且保护焊接头。通常邻近一个或更多个裸片边缘分配底部填料，并且通过毛细管作用将其吸到裸片下。然而，经分配的底部填料具有迁移离开邻近裸片的分配位置的倾向，并且可能污染邻近的裸片。作为底部填料运输的结果，其可能导致电子组件的过早失效。随着邻近裸片之间的间隔缩小，由于底部填料的迁移而污染邻近裸片的可能性增大。因此，在确定电子组件中的邻近裸片之间的最小间隔时，底部填料迁移可以是限制因素。
在称为线焊组件的其它类型电子组件中，将裸片粘接至衬底上的裸片附接焊盘。然后使用线焊工艺使裸片顶部表面上的接合焊盘和在裸片附接焊盘周围分布的接合焊盘之间的金属线耦合。围绕裸片附接焊盘的外周布置接合焊盘。将裸片附接粘合剂分配到裸片接合焊盘上。由于其尺寸小，所以接合焊盘对作为在裸片附接焊盘上物理放置裸片的结果的粘合剂从裸片接合焊盘迁移而导致污染是高度敏感的。
因此，需要这样的制作电子组件的方法，其允许物理上尽可能靠近地定位邻近电路元件，而邻近电路元件不受底部填料或粘合剂的污染。
发明内容
在本发明的一个实施例中，提供一种用于制作具有衬底和多个电路元件的电子组件的方法。该方法包括：在衬底上形成液体屏障；将第一电路元件放置在液体屏障的一侧；以及将第二电路元件放置在液体屏障的相对侧。向第一电路元件施加液体。该方法还包括：利用液体屏障防止施加至第一电路元件的液体污染第二电路元件，使得能够最小化第一电路元件和第二电路元件之间的间隔。
附图说明
包含在本说明书中并且组成本说明书的一部分的附图与上文给出的本发明的大致描述以及以下的详细描述一起例证了本发明的各种实施例。
图1示出根据本发明的实施例加工的电子组件的部分的顶视图，并且其中为了清晰说明，省略了裸片。
图2示出已将裸片附接至接合焊盘并且已将底部填充材料引入裸片下方之后的大致沿图1中的线2-2截取的横截面图。
图3示出根据本发明的原理的用于等离子体加工衬底的等离子体处理系统的示意图。
图4示出根据本发明的一个可替代实施例的类似于图1的顶视图。
图5示出根据本发明的一个可替代实施例的类似于图2的横截面图。
图6示出根据本发明的一个可替代实施例的类似于图4的顶视图。
具体实施方式
参考图1和2，电子组件12包括衬底10（例如，电路板或引脚框架），该衬底10具有两组14、16接合焊盘21。每个接合焊盘21均包括电子组件的电路元件。在代表性实施例中，每一个组14、16中的接合焊盘21均布置为行和列的阵列。组14的接合焊盘21被设置在附接部位的外边界15内侧，并且类似地，组14的接合焊盘21被设置在另一附接部位的外边界17内侧。虽然仅示出由不同接合焊盘21的组14、16组成的两个附接部位，但是根据对待被附接以形成特定电子组件12的电子部件的需要，衬底10可以包括任何数量的附接部位。在代表性实施例中，例如，电子组件12可以是倒装芯片、芯片尺寸封装（CSP）、球栅阵列（BGA）或封装体叠层组件（PoP）。
每组14、16接合焊盘21都代表在衬底10上的指定用于附接裸片的名义区域。外边界15、17的尺寸可能变化，并且其至少部分地取决于电子组件12的期望尺寸。通常，包围接合焊盘21的外边界15、17的长度和宽度均小于25mm。每个接合焊盘21或至少接合焊盘21的最上层由材料(诸如铜)层组成，用于形成电连接。
层30在外部边界15、17的外部区域中施加至衬底10的表面，所述层30包括焊料掩膜材料或在裸片附接工艺中使用的另一类型有机基材料。焊料掩膜层30被施加至衬底10的表面并且被改性或被施加使得接合焊盘21不被焊料掩膜材料覆盖，所述焊料掩膜层30可以包括处于有机聚合物基体中的二氧化硅（SiO2）颗粒。可在制造衬底10期间将焊料掩膜层30施加至衬底10。
在施加后，对焊料掩膜层30进行改性以改变焊料掩膜层30对液体或流体材料诸如底部填充材料的施加的响应。在代表性实施例中，将衬底10放置到等离子体处理系统40中，诸如图3中所示的等离子体处理系统，以对焊料掩膜层30进行表面处理。
图3示出一种等离子体处理系统40，其适用于改变焊料掩膜层30的表面能量的表面改性加工。该等离子体处理系统40包括处理室46，该处理室46由封闭加工空间48的壁体构成。在等离子体加工、诸如下文更详细描述的表面改性加工期间，将处理室46从周围外界环境液密密封、将其抽孔成适当的部分真空、并且向其提供至少一种适于期望的等离子体处理的加工气体。使用真空泵50通过装有阀的真空端口52抽空处理室的加工空间。真空泵50可以具有一个或更多个具有可控泵送速度的真空泵送装置，如真空技术领域的普通技术人员所识别的。
在调整流速下通过进气端口56将一种或更多种加工气体从加工气体源54导入至加工空间。从加工气体源54到加工空间48的加工气体的流量通常是由质量流控制器计量的。根据需要调节来自加工气体源54的气体流速以及真空泵50的泵送速率，以产生适于等离子体58的生成和期望处理工艺的等离子体加工压力。这样，当存在等离子体58时，新鲜加工气体被持续地供应至加工空间48，并且清除了任何废加工气体和/或从在衬底支撑件60上的已被加工的衬底10移除的挥发性物质。
电源62与在仓室46内侧的电极64电耦合，并且向其输送电能。从电源62输送至电极64的能量对于从被禁闭在加工空间48中的加工气体形成等离子体58是有效的。电源62还可以为与衬底支撑件60相联的电极（本这里称为“偏压电极”）提供能量。从电源62输送至偏压电极的功率对于相对于等离子体58电偏压衬底10和促进衬底10的等离子加工是有效的。电源62可以是一个或更多个控制直流（DC）偏压的电源和/或可以是射频（RF）电源，所述射频（RF）电源在约40kHz至约13.56MHz之间的频率并且在范围从约50瓦特至约10,000的瓦特级下运行。还可以使用其它适当的频率和功率范围。本领域普通技术人员应明白，不同的处理室设计可能允许或需要不同的偏压功率。控制器耦合至等离子体处理系统40的各个部件，以促进等离子体加工的控制。应进一步理解，等离子体处理系统40包括图3中未示出的部件，并且所述部件可以是运行系统40所必需的，诸如设置在加工空间48和真空泵50之间的闸阀。
现在回到表面改性加工，将加工气体例如氩气（Ar）引入到加工空间48中，视浸蚀清洗的需要而包括或不包括另一种气体，诸如氢气（H2）。从电源62向电极64供应范围从约0.02W/cm2至约0.65W/cm2的RF功率，这将在加工空间48内的加工气体激发成等离子体58。将加工气体转换为四氟化碳（CF4），或可替代地，可将CF4注入到加工空间中，并且在将其激发的同时注入Ar、H2或其它加工气体。含氟的其它加工气体诸如CHF3、C2F6、NF3、SF6可以在加工气体中作为氟化剂使用。
通过在仓室48中形成的等离子体58，电源62向偏压电极供应直流电能，以吸引来自等离子体58的离子，并且将其引向现在已偏压的衬底10。因此，焊料掩膜层30的表面被CF4等离子体处理，该CF4等离子体氟化了组成焊料掩膜层30的材料中的有机聚合物，并且因此修改了焊料掩膜层30的特性。
等离子体改性降低了组成焊料掩膜层30的有机材料的表面能量。具体地，氟化作用提高了焊料掩膜层30的疏水性，这导致焊料掩膜层30对液体浸湿的耐性在由焊料掩膜层30覆盖的衬底10的全部表面区域中得到提高。能够通过焊料掩膜层30对水的亲合力来测量疏水性，并且疏水性也可以被称为可湿性。能够通过水滴在焊料掩膜层30的表面上产生的接触角来测量焊料掩膜层30的疏水表面的疏水性。在一个实施例中，如果接触角度大于或等于90°，则认为该等离子体改性焊料掩膜层30是疏水的。
重新参考图1和2，通过焊接头将电路元件电附接并且机械附接至接合焊盘21，所述电路元件的代表性形式是裸片22、24。每个裸片22、24均包括一个或更多个集成电路，所述集成电路带有有源装置诸如CMOS场效应晶体管。还在衬底10上的附接部位处设置作为电子组件12的可选部件的电路元件19。电路元件19可以是无源装置，诸如电阻器、电容器或电感器。
将焊块18、20施加至裸片22、24上的接合焊盘26、28，施加至衬底10上的接合焊盘21，或施加至这两者。执行裸片附接加工以形成接头，该接头限定在裸片22、24的接合焊盘26、28和衬底10上的接合焊盘21的组14、16之间延伸的电和机械连接部。在所示倒装芯片附接方法中，将承载由焊料组成的焊块18、20的模盘与接合焊盘21的组14、16和在裸片22、24上的接合焊盘28对齐。当施加足够的压力和/或温度时，焊块18、20中的焊料可能回流以形成接头，该接头将裸片22、24物理和电粘合至接合焊盘21的组14、16。可替代地，焊块18、20可由焊料以外的材料诸如铜组成，并且该附接加工能够是热超声而非软熔。
在将裸片22、24分别附接至焊盘21的组14、16之后，执行底部填充操作。底部填充操作将底部填充材料44、45引入到在裸片22、24下方并且包围焊块18、20的敞开空间中。底部填充材料44、45为液体，诸如可能填充有二氧化硅颗粒的可固化非导体环氧树脂，当被施加至衬底10时，其为液体，并且通过毛细管作用流入到敞开空间中。
通过喷射装置，将底部填充材料44、45分配为在接触区域42、43上的一条或更多条沉积液体点线。该点在紧邻每个裸片22、24的一个或更多外部边缘32、34处沉积在焊料掩膜层30上。然而，可使用多个不同类型的分配器以及以多种不同方式将底部填充材料44、45施加至衬底10。通常，底部填充材料44、45的分配量近似等于在每个裸片22、24下方的敞开空间的体积加上填角的体积，该填角在已完成底部填充操作后沿裸片边缘32、34形成。
接触区域42、43起到形成在衬底上的液体屏障的作用，并且因此当将底部填充材料44、45最初分配到衬底10上时，限定底部填充材料44、45接触焊料掩膜层30的程度。等离子体处理提高了焊料掩膜层30对被底部填充材料44、45浸湿的耐性，并且防止或显著降低底部填充材料44、45流动离开裸片22、24。具体地，底部填充材料44、45并不迁移超过接触区域42、43并且不横跨邻近的裸片22、24之间的空间以造成污染。接触区域42、43具有数值为w1的宽度，其反映了等离子体改性提高了：焊料掩膜层30的疏水性；底部填充材料44、45最初在焊料掩膜层30上分配时的尺寸；以及底部填充材料44、45在其分配状态中的特性（例如，粘性）。
接触区域42被限定为在焊料掩膜层30的表面上的某一区域，并且该区域代表等离子体改性的焊料掩膜层30被分配的底部填充材料44浸湿的相对于外边界15测量的最小宽度w1。接触区域42包围接合焊盘21的组14的外边界15。在可替代实施例中，可相对于不同参考测量接触区域42，诸如在裸片22已经被附接至接合焊盘21的组14之后的裸片22的最近边缘32。外边界15和裸片22的边缘32可垂直对齐，或如果没有垂直对齐，则可参考外边界15或边缘32中的一个或另一个测量接触区域42。由于焊料掩膜层30增强的疏水性，所以邻近裸片22的边缘32施加的底部填充材料44不迁移到接触区域42外侧以转移至裸片24，并且因此不导致裸片24的污染。接触区域42可代表在邻近裸片22、24之间的最小分离间隔，该最小分离间隔用于使底部填充材料44不会流动至达到裸片24。
接触区域43被限定为在焊料掩膜层30的表面上的某一区域，并且该区域代表等离子体改性的焊料掩膜层30被分配的底部填充材料45浸湿的相对于外部边界17测量的最小宽度w1。接触区域43包围接合焊盘21的组16的外边界17。在可替代实施例中，可相对于不同参考测量接触区域43，诸如在裸片24已被附接至接合焊盘21的组16之后的裸片24的最近边缘34。外部边界17和裸片22的边缘34可垂直对齐，或如果没有垂直对齐，则可参考外部边界17或边缘34中的一个或另一个测量接触区域43。由于焊料掩膜层30增强的疏水性，所以邻近裸片24的边缘34施加的底部填充材料45不迁移到接触区域43外侧以转移至裸片22，并且因此不导致裸片22的污染。接触区域43可代表在邻近裸片22、24之间的最小分离间隔，该最小分离间隔用于使底部填充材料45不会流动至达到裸片22。
对于不同的接合焊盘21的组14、16，可通过焊料掩膜层30增强的疏水性而减小外边界15、17之间的最小间隔d1。在一个实施例中，最小间隔d1可以近似等于接触区域42、43各自的宽度w1的和。该最小间隔d1和接触区域42、43的下限涉及作为邻近外部边界15、17分配的底部填充材料的停放区的所需空间。具体地，除了底部填充材料44、45从分配位置移走的任何倾向外，分配的底部填充材料的尺寸（点尺寸或线宽）还可提供关于接触区域42、43各自的宽度w1以及外边界15、17之间的最小间隔d1的确定性因素。类似地，可以将使外边界17与电子元件19分开的最小间隔d2减小为近似等于接触区域43的宽度w1。焊料掩膜层30增强的疏水性作为关于最小间隔d1、d2的限制因素而消除或至少减小底部填充材料44、45的迁移。
在设计用于电子组件12的接合焊盘21的组14、16的布局时，可考虑接触区域42、43的尺寸。最小间隔d1、d2可为450μm或更小，其显著小于900μm或更大的常规最小间隔。最小间隔的缩小允许彼此更加邻近地布置不同的接合焊盘21的组14、16的外边界15、17，这节约了在衬底10的表面上的空间。
在底部填充材料44、45在裸片22、24下方移动之后，就通过定时加热处理使底部填充材料44、45固化和硬化。可在流体分配器后同轴定位的一些类型的对流式烤炉、辐射炉或微波固化炉中使底部填充材料44、45固化。当被固化和硬化时，底部填充材料形成坚固粘接的粘性团。固化的底部填充材料44、45保护焊接头抵抗各种不利环境因素，再分布冲击造成的机械应力，并且在热循环期间防止焊接头不在应变的作用下移动。
在可替代实施例中，可使用助焊（非流动）底部填充加工来供应底部填充材料44、45。在组装加工期间，在放置裸片之前，向附接部位实施将非流动底部填充。在回流期间，底部填料起焊剂的作用，允许形成金属互连，并且在回流炉中完成底部填料固化。
参考图4，其中相同标附图标记指代图1-3中的相同部件，并且根据本发明的可替代实施例，用于形成电子组件的衬底80包括裸片附接焊盘82，该裸片附接焊盘82代表具有外边界84的附接部位。多个接合焊盘86分布在裸片附接焊盘82的边界84的外周周围的各个位置处。至少包围裸片附接焊盘82的区域被焊料掩膜层30覆盖。每个接合焊盘86均包括电子组件的电路元件。
裸片附接焊盘82代表衬底80上的名义区域，其指定用于附接裸片以形成类似于组件12（图1、2）的组件。附接过程包括在裸片附接焊盘82的表面区域上分配作为液体的裸片附接粘合剂，并且使用拾取和布置机器来将裸片定位成与裸片附接焊盘82上的粘合剂成接触关系。裸片附接粘合剂在裸片和裸片附接焊盘82之间提供热界面和机械界面。当裸片附接焊盘80被放置成与裸片附接粘合剂成接触关系并且被挤压朝向衬底10的顶表面时，裸片附接粘合剂朝外边界84向外移位并且通常移位超过外边界84。一部分移位的粘合剂可能形成邻近裸片边缘并且延伸到裸片边缘上的边片。
接合焊盘86相对小，并且因此对裸片附接粘合剂的污染高度敏感。为了防止裸片附接粘合剂迁移到接合焊盘86，如上所述对焊料掩膜层30进行等离子体处理。由于等离子体处理的焊料掩膜层30增加的疏水性，所以可显著减小在接合焊盘86和裸片附接焊盘82的外边缘84之间的最小间隔d4。与在常规电子组件中相比，最小间隔d4的缩小允许更邻近裸片附接焊盘82地放置接合焊盘86，这就保存了衬底10的表面上的空间。
然后，使用线焊工艺来耦合在裸片的顶部表面上的接合焊盘和分布在裸片附接焊盘82周围的接合焊盘86之间的金属线。焊料掩膜层30增强的疏水性防止接合焊盘86受裸片附接粘合剂的迁移污染。
参考图5，其中相同附图标记指代图1-4中的相同部件，并且根据本发明的可替代实施例，在衬底10上形成坝形体66，其中不存在焊料掩膜材料30。将坝形体66沿裸片22、24的最为相邻的侧边缘32、34定位在接合焊盘21的组14的外边界15和接合焊盘21的组16的外边界17之间。坝形体66在裸片22、24的边缘32、34之间的位置处形成为线性体。在可替代实施例中，坝形体66可包围裸片22、24中的一个或另一个。在另一实施例中，可存在多个类似坝形体66的坝形体。在另一实施例中，可将类似于坝形体66的坝形体定位在裸片24的侧边缘34和电路元件19之间（图1）。
坝形体66起到在衬底10上形成的液体屏障的作用。为了该目的，可将坝形体66构建成具有足以防止经分配的底部填充材料44迁移至裸片24或防止经分配的底部填充材料45迁移至裸片22的高度。该坝形体66包括抵抗底部填充材料44、45的浸润的疏水性材料。在特定实施例中，坝形体66由疏水的、等离子体聚合材料诸如四甲基二硅氧烷（“TMDSO”）组成。
根据本发明的一个实施例，坝形体66是通过将掩模诸如铝掩模定位在衬底10上或定位成与衬底10处于接触关系而形成的。然后，将经掩膜的衬底10放置在加工室内，诸如上文参考图3所述的处理室46。控制器调节真空泵50的运行以及气体引入，以维持期望的加工压力。从电源62向电极64提供范围从约0.02W/cm2至约0.65W/cm2的RF功率，这将加工空间48内的加工气体激励成等离子体58。在一个实施例中，加工气体可以是Ar和单体气体诸如硅氧烷或在一个实施例中TMDSO的混合物。可通过在与加工空间48流体耦合的单独蒸发室（未示出，但是包括在气体源54内）中供应液体TMDSO而引入TMDSO。由于TMDSO的蒸气压在20°C为112.5mTorr，所以一旦在仓室46内侧建立适当的加工压力，TMDSO将容易地蒸发并且以范围从约1sccm至约1000sccm的流速进入加工空间48。在可替代实施例中，如本领域普通技术人员众所周知并且将被考虑为符合本发明的实施例的，可使用载体气体将单体蒸汽运输到加工空间48。在引入TMDSO时，可将仓室46中的加工压力保持在从约20mTorr至约200mTorr的范围内。
等离子体58中的TMDSO选择性地在衬底10的未经掩膜表面上形成聚合物层。随着坝形体66的沉积完成，终止加工气体的引入，等离子体加工结束，并且从等离子体处理系统40移除衬底10。然后可按照上文描述地进行倒装芯片加工。
坝形体66防止底部填充材料44从邻近裸片22的分配位置迁移至裸片24。坝形体66同样防止底部填充材料45从邻近裸片24的分配位置迁移至裸片22。由于坝形体66的存在，所以可显著缩小外边界15、17之间的最小间隔d3。与在常规电子组件中相比，最小间隔d3的缩小允许更接近地封装裸片22、24，这就保存了衬底10表面上的空间。在一个实施例中，坝形体66的高度可以是近似200nm，并且坝形体66的宽度可以是近似100nm。
参考图6，其中相同附图标记指代图1-5中的相同部件，并且根据本发明的可替代实施例，坝形体68被定位在裸片附接焊盘82和接合焊盘86之间。坝形体68包围裸片附接焊盘82。坝形体68以与坝形体66（图5）相同的方式形成，并且具有与坝形体66的结构类似或相同的结构。坝形体68防止裸片附接粘合剂从裸片附接焊盘82迁移至接合焊盘86。由于坝形体68的存在，可显著缩小裸片附接焊盘82和接合焊盘86之间的最小间隔d4。
这里使用的术语仅用于描述具体实施例的目的，并且不旨在限制本发明。除非在上下文中另外明确指出，否则本文使用的单数形式“一…”、“一个…”以及“该…”也旨在包括复数形式。还应理解，当在本说明中使用时，术语“由…组成”和/或“包含”指定存在一定的特征、整数、步骤、操作、元件和/或部件，但是不排除出现或增加一个或更多个其它特征、整数、步骤、操作、元件、部件和/或其组。此外，就在详细说明或权利要求中使用的术语“包括…”、“具有…”“包含…”“带有…”“由…组成”或其变形来说，将这些术语旨在类似术语“包括…”的形式的包括范围。
应理解，当元件被描述为“被连接”或“被耦合”至另一元件或与另一元件“连接”或“耦合”时，其能够是直接连接或耦合至其它元件，或作为代替，可能存在一个或更多个居间元件。相反，当元件被描述为“被直接连接”或“被直接耦合”至另一元件时，不存在居间元件。当元件被描述为“被间接连接”或“被间接耦合”至另一元件时，存在至少一个居间元件。
虽然已通过描述各个实施例而例证了本发明，并且虽然已相当详细地描述了这些实施例，但是申请人不旨在约束或以任何方式限制所附权利要求的范围到这样的细节。本领域技术人员将容易地看到另外的优势和变型。因而，本发明的更广泛方面不限于所示出和所描述的特定细节、代表性设备和方法以及例证性实施例。

Claims (8)

1.一种制作电子组件的方法，所述电子组件具有衬底和多个电路元件，所述方法包括：
将焊料掩膜材料的层施加至所述衬底；
将所述层暴露至含氟的等离子体，以氟化所述焊料掩膜，并由此增加所述焊料掩膜材料的疏水性；
在所述衬底上放置第一电路元件；
在所述衬底上放置第二电路元件；以及
将液体施加至所述第一电路元件，
其中，所述层至所述含氟的等离子体的暴露防止施加至所述第一电路元件的液体流动以污染所述第二电路元件，使得能够最小化所述第一电路元件和第二电路元件之间的间隔，
其中，所述液体为底部填充材料，所述第一电路元件为裸片，并且，将液体施加至所述第一电路元件包括：在邻近所述裸片的边缘的接触区域上，将所述底部填充材料分配到所述层上，以及
其中，所述层被施加至所述衬底的表面并且被改性使得所述表面除了接合焊盘被布置在其中的区域都被焊料掩膜材料覆盖。
2.根据权利要求1所述的方法，其中，所述第二电路元件为裸片。
3.根据权利要求1所述的方法，其中，所述液体为粘合剂，所述第一电路元件为裸片，并且，将液体施加至所述第一电路元件包括：
将所述粘合剂分配到在所述衬底上的裸片附接焊盘上。
4.根据权利要求3所述的方法，其中，所述第二电路元件为接合焊盘。
5.根据权利要求1所述的方法，其中，所述液体为粘合剂，所述第一电路元件为裸片，并且，将液体施加至所述第一电路元件包括：
将所述粘合剂分配至在所述衬底上的裸片附接焊盘上；以及
使所述裸片接触在所述裸片附接焊盘上的所述粘合剂。
6.根据权利要求1所述的方法，其中，所述液体为底部填充材料，所述第一电路元件为裸片，并且，将液体施加至所述第一电路元件还包括：
邻近所述裸片的边缘分配所述底部填充材料。
7.根据权利要求1所述的方法，其中，所述第一电路元件为第一裸片，并且，所述第二电路元件为第二裸片。
8.根据权利要求1所述的方法，其中，所述第一电路元件为第一裸片，并且，所述第二电路元件为在所述衬底上的接合焊盘。
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