JP5971868B2 - 真空補助によるアンダーフィル形成方法 - Google Patents
真空補助によるアンダーフィル形成方法 Download PDFInfo
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- JP5971868B2 JP5971868B2 JP2013549416A JP2013549416A JP5971868B2 JP 5971868 B2 JP5971868 B2 JP 5971868B2 JP 2013549416 A JP2013549416 A JP 2013549416A JP 2013549416 A JP2013549416 A JP 2013549416A JP 5971868 B2 JP5971868 B2 JP 5971868B2
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- 238000000034 method Methods 0.000 title claims description 31
- 230000015572 biosynthetic process Effects 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims description 86
- 229910000679 solder Inorganic materials 0.000 claims description 28
- 238000001816 cooling Methods 0.000 claims description 11
- 239000007787 solid Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000000704 physical effect Effects 0.000 claims description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
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Description
Claims (13)
- 電子デバイスが導電性接合により基板に取り付けられて、前記導電性接合により占有されていない開放部を有する空間によって前記電子デバイスが前記基板から離隔されるようになった前記基板上に、アンダーフィルを形成する方法であって、前記方法が、
前記アンダーフィルを冷却する段階と、
前記アンダーフィルを冷却後、電子デバイスの少なくとも1つの外縁部に近接して前記基板上にアンダーフィルを形成する段階と、
前記空間を真空排気して該空間の開放部に真空状態を形成する段階と、
前記空間を真空状態に排気した後で且つ前記排気状態を維持している間、前記少なくとも1つの外縁部から前記空間の開放部への前記アンダーフィルの流れを引き起こすようにする段階と、
を含む、方法。 - 前記アンダーフィルが前記基板上に分配される前に、前記基板を冷却して、該アンダーフィルが前記基板上に分配されたときに前記アンダーフィルが室温より低く冷却されるようにする段階を更に含む、請求項1に記載の方法。
- 前記アンダーフィルは、室温より低く冷却される、請求項1に記載の方法。
- 前記アンダーフィルは、30度から120度の範囲で冷却される、請求項1に記載の方法。
- 前記真空状態が、前記アンダーフィルの物理的特性を顕著に又は有害に修正させることのない準大気圧であることを特徴とする、請求項1に記載の方法。
- 前記真空状態が、95Torrより高いか又は等しい準大気圧であることを特徴とする、請求項1に記載の方法。
- 前記アンダーフィルが固体アンダーフィルであり、該アンダーフィルがその融点を超えて毛管アンダーフィルを開始する温度にされる、請求項1に記載の方法。
- 少なくとも1つのギャップが前記アンダーフィルの内部に形成され、前記空間が前記少なくとも1つのギャップを通って真空排気される、請求項1に記載の方法。
- 前記アンダーフィルの内部にギャップが形成されず、真空状態が与えられたときに、前記空間内のガスが泡状になって前記アンダーフィルを通過する、請求項1に記載の方法。
- 前記導電性接合が、リフローされた半田ボールである、請求項1に記載の方法。
- 前記導電性接合が、銅ピラーである、請求項1に記載の方法。
- 前記空間を前記真空状態に排気した後、前記アンダーフィルを室温より高い第一の温度まで加熱する段階を更に含む、請求項1に記載の方法。
- 前記アンダーフィルは、前記第1温度よりも低い第2温度まで冷却される、請求項12に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/004,198 | 2011-01-11 | ||
US13/004,198 US20120178219A1 (en) | 2011-01-11 | 2011-01-11 | Methods for vacuum assisted underfilling |
PCT/US2011/064373 WO2012096743A1 (en) | 2011-01-11 | 2011-12-12 | Methods for vacuum assisted underfilling |
Publications (2)
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US (1) | US20120178219A1 (ja) |
EP (1) | EP2663997A4 (ja) |
JP (1) | JP5971868B2 (ja) |
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JP5261255B2 (ja) * | 2009-03-27 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2016043779A1 (en) * | 2014-09-19 | 2016-03-24 | Intel Corporation | Semiconductor packages with embedded bridge interconnects |
US10547350B2 (en) * | 2016-05-05 | 2020-01-28 | Texas Instruments Incorporated | Contactless interface for mm-wave near field communication |
DE102017209461A1 (de) | 2017-06-06 | 2018-12-06 | Zf Friedrichshafen Ag | Anordnung zur Abstützung eines integrierten Schaltungsträgers |
CN110072347A (zh) * | 2019-04-09 | 2019-07-30 | 南昌嘉研科技有限公司 | 一种bga封装芯片的防护结构及其加工方法 |
CN112216617B (zh) * | 2020-09-04 | 2023-09-15 | 苏州通富超威半导体有限公司 | 一种底封胶填充控制方法、装置、电子设备及介质 |
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JPS63262867A (ja) * | 1987-04-20 | 1988-10-31 | Nec Corp | 半導体記憶装置 |
US5203076A (en) * | 1991-12-23 | 1993-04-20 | Motorola, Inc. | Vacuum infiltration of underfill material for flip-chip devices |
JPH09260432A (ja) * | 1996-03-22 | 1997-10-03 | Nitto Denko Corp | 半導体装置の製法 |
US5866442A (en) * | 1997-01-28 | 1999-02-02 | Micron Technology, Inc. | Method and apparatus for filling a gap between spaced layers of a semiconductor |
JPH11121484A (ja) * | 1997-10-16 | 1999-04-30 | Toshiba Corp | 半導体装置及びその製造方法と製造装置 |
US5998242A (en) * | 1997-10-27 | 1999-12-07 | Lsi Logic Corporation | Vacuum assisted underfill process and apparatus for semiconductor package fabrication |
US7547579B1 (en) * | 2000-04-06 | 2009-06-16 | Micron Technology, Inc. | Underfill process |
US7015066B2 (en) * | 2001-09-05 | 2006-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly |
US6610559B2 (en) * | 2001-11-16 | 2003-08-26 | Indium Corporation Of America | Integrated void-free process for assembling a solder bumped chip |
JP3818268B2 (ja) * | 2003-03-05 | 2006-09-06 | セイコーエプソン株式会社 | アンダーフィル材の充填方法 |
US6978540B2 (en) * | 2003-05-23 | 2005-12-27 | National Starch And Chemical Investment Holding Corporation | Method for pre-applied thermoplastic reinforcement of electronic components |
US7026376B2 (en) * | 2003-06-30 | 2006-04-11 | Intel Corporation | Fluxing agent for underfill materials |
US7351784B2 (en) * | 2005-09-30 | 2008-04-01 | Intel Corporation | Chip-packaging composition of resin and cycloaliphatic amine hardener |
JP2007141935A (ja) * | 2005-11-15 | 2007-06-07 | Toray Eng Co Ltd | ディスペンス装置及び実装システム |
EP2135276A2 (en) * | 2007-03-13 | 2009-12-23 | Lord Corporation | Die attachment method with a covex surface underfill |
FR2919426B1 (fr) * | 2007-07-23 | 2009-12-11 | Commissariat Energie Atomique | Procede d'enrobage de deux elements hybrides entre eux au moyen d'un materiau de brasure |
US7745321B2 (en) * | 2008-01-11 | 2010-06-29 | Qimonda Ag | Solder contacts and methods of forming same |
JP2010034504A (ja) * | 2008-07-02 | 2010-02-12 | Panasonic Corp | 基板間の接続方法、フリップチップ実装体及び基板間接続構造 |
JP2010245341A (ja) * | 2009-04-07 | 2010-10-28 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
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2011
- 2011-01-11 US US13/004,198 patent/US20120178219A1/en not_active Abandoned
- 2011-12-12 JP JP2013549416A patent/JP5971868B2/ja not_active Expired - Fee Related
- 2011-12-12 EP EP11855462.5A patent/EP2663997A4/en not_active Withdrawn
- 2011-12-12 CN CN201180064777.9A patent/CN103299407B/zh not_active Expired - Fee Related
- 2011-12-12 WO PCT/US2011/064373 patent/WO2012096743A1/en active Application Filing
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CN103299407A (zh) | 2013-09-11 |
WO2012096743A1 (en) | 2012-07-19 |
EP2663997A4 (en) | 2016-01-13 |
JP2014506010A (ja) | 2014-03-06 |
EP2663997A1 (en) | 2013-11-20 |
US20120178219A1 (en) | 2012-07-12 |
CN103299407B (zh) | 2016-09-14 |
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