TWI672782B - 半導體晶片之製造方法 - Google Patents

半導體晶片之製造方法 Download PDF

Info

Publication number
TWI672782B
TWI672782B TW107107068A TW107107068A TWI672782B TW I672782 B TWI672782 B TW I672782B TW 107107068 A TW107107068 A TW 107107068A TW 107107068 A TW107107068 A TW 107107068A TW I672782 B TWI672782 B TW I672782B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
micro
microbumps
bumps
pressure
Prior art date
Application number
TW107107068A
Other languages
English (en)
Other versions
TW201836103A (zh
Inventor
折笠誠
清家英之
堀川雄平
阿部寿之
Original Assignee
日商 Tdk 股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商 Tdk 股份有限公司 filed Critical 日商 Tdk 股份有限公司
Publication of TW201836103A publication Critical patent/TW201836103A/zh
Application granted granted Critical
Publication of TWI672782B publication Critical patent/TWI672782B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67121Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81002Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81014Thermal cleaning, e.g. decomposition, sublimation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/81022Cleaning the bonding area, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8103Reshaping the bump connector in the bonding apparatus, e.g. flattening the bump connector
    • H01L2224/81035Reshaping the bump connector in the bonding apparatus, e.g. flattening the bump connector by heating means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8103Reshaping the bump connector in the bonding apparatus, e.g. flattening the bump connector
    • H01L2224/81047Reshaping the bump connector in the bonding apparatus, e.g. flattening the bump connector by mechanical means, e.g. severing, pressing, stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/81048Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81054Composition of the atmosphere
    • H01L2224/81065Composition of the atmosphere being reducing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81143Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95143Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H01L2224/95146Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明之半導體晶片之製造方法係使複數片半導體晶片積層而成之半導體晶片之製造方法,該半導體晶片具有基板、形成於基板上之導電部及形成於導電部之微凸塊,且該製造方法具備加熱步驟,即,於惰性環境內使還原性氣體流入至配置有半導體晶片之空間,以微凸塊之熔點以上之溫度進行加熱,於加熱步驟中,於微凸塊上載置壓力賦予構件。

Description

半導體晶片之製造方法
本發明係關於半導體晶片之製造方法。
一直以來,於半導體封裝之三維安裝中,使用引線接合進行半導體晶片與半導體晶片、或中介板之連接。替代該引線接合而開發有經由貫通電極與凸塊將半導體晶片彼此連接之三維安裝技術。貫通電極通常成為較短之連接線長(例如50 μm),且將電極間相連之凸塊亦要求為微細者。與此種低於50 μm之凸塊間距相對應之技術被稱作微凸塊。如美國專利第9136159號說明書,藉由將半導體晶片與半導體晶片以貫通電極與微凸塊連接,而能夠顯著地縮短半導體晶片間之配線長度。因此,能夠降低伴隨微細化而增大之配線延遲時間。 於此,微凸塊之形成製程可列舉焊料印刷法、焊料球搭載、鍍覆法等,但因有機物或水等於反應過程中產生之氣體等而產生之空泡成為問題。由此,日本專利第5807221號說明書中,記載有於惰性環境內進行回流焊、於氫或羧酸等還原性環境中進行回流焊。
於此,當如微凸塊般凸塊變小時,即便為微小之空泡(例如10 μm以下)亦可能導致連接不良或配線電阻之增加。然而,空泡越小則浮力越小,越難以排出,尤其是障壁金屬層與凸塊之界面因熱而形成有合金層。因此,難以將流動性較低之合金層附近之空泡排出。 本發明之目的在於提供能夠容易地將微凸塊內之空泡除去之半導體晶片之製造方法。 本發明之一方面之半導體晶片之製造方法係具有基板、形成於基板上之導電部、及形成於導電部之微凸塊的半導體晶片之製造方法,且具備加熱步驟,即,於惰性環境內使還原性氣體流入至配置有半導體晶片之空間,且以微凸塊之熔點以上之溫度進行加熱,加熱步驟中,於微凸塊上載置壓力賦予構件。 該半導體晶片之製造方法中,於加熱步驟中,於惰性環境內使還原性氣體流入至配置有半導體晶片之空間而進行加熱。藉此,形成於微凸塊之表面之氧化膜被還原除去。又,加熱步驟中,藉由以微凸塊之熔點以上之溫度進行加熱而使微凸塊熔融具有流動性。於此,加熱步驟中,於微凸塊上載置壓力賦予構件。因此,伴隨微凸塊熔融具有流動性,微凸塊藉由壓力賦予構件之壓力而以壓潰之方式變形。藉由該變形而於微凸塊內產生流動,空泡於微凸塊內流動。藉此,於微凸塊內流動之空泡自該微凸塊內朝外部排出而被除去。藉由以上方法而能夠容易地將微凸塊內之空泡除去。 可應用羧酸作為還原性氣體。藉此,能夠良好地將微凸塊表面之氧化膜除去。 壓力賦予構件之重量就微凸塊之剖面積平均為0.0005 μg/μm2 以上且0.1 μg/μm2 以下。藉此,壓力賦予構件能夠對微凸塊賦予用以將空泡除去之適當之壓力。 可於基板上配置具有固定厚度之間隔片,壓力賦予構件被壓入至與間隔片接觸為止。藉此,由於以間隔片阻止壓力賦予構件,因此能夠防止微凸塊過度壓潰。 根據本發明,能夠提供可容易地將微凸塊內之空泡除去之半導體晶片之製造方法。
以下,參照附圖詳細說明本發明之一方面之半導體晶片之製造方法之較佳實施形態。再者,於以下之說明中,對同一要素或具有同一功能之要素使用同一符號,並省略重複之說明。 圖1係表示包含半導體晶片之半導體封裝之一實施形態之概略剖面圖。如圖1所示,半導體封裝100具備使3片以上(於此為3片)之半導體晶片1積層而構成之積層體2、經由焊料球3與積層體2電性連接之有機基板4、藉由以塑模樹脂覆蓋安裝於有機基板4上之積層體2而形成之塑模部6。再者,塑模部6之內部空間以填埋積層體2之半導體晶片1之間之方式被填充有底部填料7。於本實施形態中,積層體2係藉由使半導體晶片1A、半導體晶片1B、及半導體晶片1C於上下方向上積層而構成。半導體晶片1A與半導體晶片1B經由藉由使微凸塊熔融接合而成之接合部8進行接合。半導體晶片1C與半導體晶片1B經由藉由使微凸塊熔融接合而成之接合部8進行接合。 例如,如圖4A所示,接合前之半導體晶片1具有基板11、形成於基板11上之導電部12、及形成於導電部12之微凸塊13。基板11由例如矽(Si)晶片等半導體晶片、矽(Si)中介板等構成。再者,於半導體晶片1A及半導體晶片1C,僅於一主面形成有導電部12。於半導體晶片1B,於兩主面形成有導電部12。又,形成於半導體晶片1B之兩主面之導電部12經由沿基板11之厚度方向延伸之通孔電極19而相互連接。 導電部12於基板11之主面上形成有複數個。導電部12以特定之間距排列於基板11之主面上。導電部12具備形成於基板11之主面上之電極墊14、及形成於電極墊14之上表面之障壁金屬層16。再者,基板11之主面中未形成導電部12之部分由絕緣層17覆蓋(參照圖5)。作為障壁金屬層16之構成材料,可使用例如Ni及Ni化合物(例如NiP)等。作為絕緣層17之構成材料,可使用例如SiO、SiN、聚醯亞胺等。 微凸塊13形成於導電部12之障壁金屬層16上。微凸塊13可含有Sn、Ag、Cu、Ag-Cu、Bi、In等作為構成材料,亦可使用包含該些中之任意兩種以上之材料之合金。特別是,微凸塊13亦可含有Sn作為主成分。微凸塊13例如亦可利用鍍覆法來形成。或者,微凸塊13可藉由使用包含焊料合金之微小球而形成,亦可印刷漿料而形成。再者,將俯視觀察時之直徑小於50 μm之凸塊稱作微凸塊。 如圖5所示,微凸塊13於剛形成於基板11之後不久具有球面。藉由對此種微凸塊13實施特定之處理,而於微凸塊13形成平滑面13a。平滑面13a由在微凸塊13之上端部沿水平方向擴展之平面構成。再者,下文敍述用以形成平滑面13a之處理內容之一例。微凸塊13之高度、即平滑面13a與導電部12之上表面之間之尺寸可於5~50 μm之範圍設定。 其次,參照圖2~圖9說明本實施形態之包含半導體晶片1之半導體封裝100之製造方法。 如圖2所示,首先,執行藉由於基板11上形成微凸塊13而準備半導體晶片1之半導體晶片準備步驟(步驟S1)。藉此,準備半導體晶片1A、1B、1C。其中,於該階段,未於微凸塊13形成平滑面13a。 其次,執行於微凸塊13形成平滑面13a之平滑面形成步驟(步驟S2)。又,平滑面形成步驟S2亦相當於自微凸塊13之內部除去空泡22之空泡除去步驟。 於此,參照圖6說明平滑面形成步驟(空泡除去步驟)S2之詳細內容。 如圖6及圖7A所示,執行相對於微凸塊13設置壓力賦予構件21之壓力賦予構件設置步驟(步驟S20)。如此,於載置有壓力賦予構件21之狀態下,將半導體晶片1配置於加熱爐之內部。再者,於以後之說明中,適當參照圖9所示之加熱爐內之溫度與壓力之分佈進行說明。再者,圖9中,實線表示加熱爐內之溫度,虛線表示加熱爐內之壓力。 作為載置於微凸塊13上之壓力賦予構件21之構成材料,較佳為採用不與微凸塊13反應之材料。例如,作為壓力賦予構件21之構成材料,可採用Si、SiO2 、SiN等。又,壓力賦予構件21之主面中、與微凸塊13相接之主面21a較佳為構成為平面。例如,於在主面21a形成有突起等之情形時,由於與微凸塊13牽絆,因此於除去壓力賦予構件21時不易脫落。壓力賦予構件21對微凸塊13賦予之壓力較佳為僅為壓力賦予構件21自身之自重。具體而言,壓力較佳為就微凸塊之剖面積平均為0.0005 μg/μm2 以上且0.1 μg/μm2 以下。例如,若以倒裝晶片安裝般之方法來控制壓力賦予構件21之壓力、或高度,則於微凸塊13自固體變化為液體時(自圖7B向圖7C變化時)施加於壓力賦予構件21之壓力降低,因此,於壓力賦予構件21之位置產生偏移。會因輕微之偏移而對如微凸塊13般較小之凸塊過度地施加壓力。 其次,執行將配置有半導體晶片1之加熱爐之空間減壓之減壓步驟(步驟S21)。於減壓步驟S21中,將加熱爐內抽真空而形成減壓環境。殘留於加熱爐內之氧會引起微凸塊13氧化。因此,較佳為將加熱爐內排氣至大氣壓狀態(自1.01×10^5 Pa至1×10^3 Pa以下,特別是5 Pa以下)之減壓狀態。由此,加熱爐內之壓力降低(參照圖9之曲線P1之部分)。對此種減壓環境之加熱爐內導入惰性氣體。由此,加熱爐內之壓力上升(參照圖9之曲線P2之部分)。惰性氣體於使加熱爐內上升至微凸塊13之熔融溫度以上(熔點以上)之溫度域時,一面防止微凸塊13之表面之進一步氧化,一面實現微凸塊13之熔融,作為加熱爐內之熱媒介發揮功能。作為此種惰性氣體,可使用例如氮(N2 )氣或氬(Ar)氣等。 其次,執行於惰性環境內對加熱爐流入還原性氣體,並以微凸塊13之熔點以上之溫度加熱之加熱步驟(步驟S22)。加熱步驟S22係於對加熱爐內導入惰性氣體之後、或者與導入惰性氣體大致同時執行。於加熱步驟S22中,以特定之升溫速度(例如35~45℃/分鐘)將加熱爐內升溫,使導入有惰性氣體之狀態之加熱爐內之溫度上升至微凸塊13之熔點以上之溫度域為止。例如,於由Sn-Ag-Cu合金構成凸塊之情形時,熔點雖然根據合金之組成而不同,但大致為220~230℃,因此,使加熱爐內之溫度上升至此種溫度以上之溫度域為止。 還原性氣體之導入較佳為於氧化膜23開始還原反應之溫度之前後實施。一面將加熱爐內之溫度(圖9之溫度T1)維持於開始還原反應之溫度以上,一面持續供給適當之溫度與流量之還原性氣體。由此,能夠將存在於微凸塊13之表面之氧化膜23還原除去。作為還原性氣體,例如可應用羧酸(甲酸)。作為羧酸之例子,可舉出甲酸、乙酸、丙烯酸、丙酸等低級羧酸。於使用甲酸作為還原氣體之情形時,較佳為於加熱爐內之溫度成為110℃左右時導入甲酸。即便於開始還原反應之溫度以下導入甲酸,反應亦不進行,而若溫度過高,由於係於殘留有表面之氧化膜23之狀態下加熱微凸塊13,因此,空泡22內部之壓力上升。當於空泡22之內部之壓力過度提高之狀態下除去氧化膜23時,空泡22之壓力被一下子釋放,液化之微凸塊13亦可能飛散。因此,可於開始還原反應之溫度T1維持特定時間,於氧化膜23被充分除去之階段將加熱爐之溫度維持於微凸塊13之熔點以上之溫度T2(參照圖9)。 當微凸塊13熔融而將空泡22除去,形成平滑面13a後,執行將加熱爐之溫度降溫之降溫步驟(步驟S23)。具體而言,於維持於微凸塊13之熔融溫度以上之溫度T2之加熱爐內將微凸塊13暴露於甲酸中特定時間(例如0.5~3分鐘)後,將導入至加熱爐內之甲酸抽真空排出。於將加熱爐內之甲酸排氣後、或者與甲酸之排氣同時地,以特定之降溫速度(例如-5~-40℃/分鐘)將加熱爐內降溫。再者,圖9中,於加熱爐之溫度下降之前進行抽真空。然而,於加熱爐內之溫度降溫至熔融之凸塊固化某種程度之溫度域為止後,可對加熱爐內導入氮氣或氬氣等惰性氣體而恢復至大氣壓。 藉由執行上述般之加熱步驟S22及降溫步驟S23,如圖7B~圖7G所示,能自微凸塊13除去空泡22,並且於微凸塊13形成平滑面13a。即,藉由於還原性氣體之環境下進行加熱,而可將形成於微凸塊13之表面之氧化膜23還原除去(參照圖7B)。而且,藉由以微凸塊13之熔點以上之溫度進行加熱而微凸塊13熔融。藉此,藉由壓力賦予構件21之壓力而使微凸塊13以壓潰之方式變形。由此,對應於壓力賦予構件21之主面21a之形狀,而於微凸塊13形成與平滑面13a相對應之形狀(參照圖7C~圖7F)。又,藉由熔融之微凸塊13被壓力賦予構件21按壓而流動,從而微凸塊13內之空泡22上升被排出到外部(參照圖7C~圖7F)。藉由加熱爐之溫度恢復而微凸塊13被冷卻固化。由此,於微凸塊13形成平滑面13a(參照圖7G)。 返回至圖2,針對各半導體晶片1之平滑面形成步驟S2完成後,執行於一半導體晶片1之微凸塊13重合另一半導體晶片1之微凸塊13,藉此積層3片以上之半導體晶片1之積層步驟(步驟S3)。於本實施形態中,於積層步驟S3中,於一半導體晶片1與另一半導體晶片1之微凸塊13形成有平滑面13a。而且,一半導體晶片1之微凸塊13於平滑面13a與另一微凸塊13接觸。於積層步驟S3中,對於所有半導體晶片1,相互之微凸塊13以不接合之狀態重合。 具體而言,如圖3A及圖3B所示,於最下方之半導體晶片1C之微凸塊13重合半導體晶片1B之微凸塊13。此時,於半導體晶片1C之微凸塊13之平滑面13a之上載置半導體晶片1B之微凸塊13之平滑面13a。又,半導體晶片1C之微凸塊13與半導體晶片1B之微凸塊13為相互不接合而僅簡單接觸之狀態。 其次,如圖3B及圖4A所示,於自下數第2個半導體晶片1B之微凸塊13重合最上方之半導體晶片1C之微凸塊13。此時,於半導體晶片1B之微凸塊13之平滑面13a之上載置半導體晶片1C之微凸塊13之平滑面13a。又,半導體晶片1B之微凸塊13與半導體晶片1C之微凸塊13為相互不接合而僅簡單接觸之狀態。 積層步驟S3完成後,執行藉由加熱微凸塊13使其熔融,而經由該微凸塊13將半導體晶片1彼此接合之接合步驟(步驟S4)。於接合步驟S4中,藉由一次之加熱將所有微凸塊13一併熔融而將所有半導體晶片1一併接合。又,於接合步驟S4中,於還原環境內使各半導體晶片1之微凸塊13熔融。 具體而言,如圖4A所示,將隔著微凸塊13積層半導體晶片1A、1B、1C之狀態之積層體配置於加熱爐內。然後,藉由以加熱爐加熱該積層體而積層體內之所有微凸塊13熔融,並且相互接觸之微凸塊13一併接合。由此,如圖4B所示,半導體晶片1A、1B、1C經由2個微凸塊13熔融而相互結合而成之接合部8接合。 於接合步驟S4完成後,執行製作半導體封裝100之半導體封裝製作步驟(步驟S5)。於半導體封裝製作步驟S5中,將於接合步驟S5得到之積層體2與有機基板4連接,並且,以塑模部6覆蓋積層體2。藉由如上步驟而完成半導體封裝100,圖2所示之製造方法結束。 其次,對本實施形態之半導體晶片1之製造方法之作用及效果進行說明。 於半導體晶片1之製造方法中,於加熱步驟S22中,於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間而進行加熱。藉此,形成於微凸塊13之表面之氧化膜23被還原除去。又,藉由以微凸塊13之熔點以上之溫度進行加熱而微凸塊13熔融,由此具有流動性。於此,於加熱步驟S22中,於微凸塊13上載置壓力賦予構件21。因此,伴隨微凸塊13熔融而具有流動性,藉由壓力賦予構件21之壓力而微凸塊13以壓潰之方式變形。藉由該變形,於微凸塊13內產生流動,從而空泡22於微凸塊13內流動。由此,於微凸塊13內流動之空泡22自該微凸塊13內排出至外部而被除去。藉由如上步驟,能夠容易地除去微凸塊13內之空泡22。 作為還原性氣體,可應用羧酸。由此,能夠良好地除去微凸塊13表面之氧化膜23。 就壓力賦予構件21之重量而言,就微凸塊13之剖面積,平均可為0.0005 μg/μm2 以上且0.1 μg/μm2 以下。由此,壓力賦予構件21能夠對微凸塊13賦予用以除去空泡22之適當之壓力。 於半導體封裝100之製造方法中,於積層步驟S3中,於一半導體晶片1與另一半導體晶片1中之至少一者之微凸塊13形成平滑面13a,其中一者之微凸塊13於平滑面13a與另一者之微凸塊13接觸。如此,藉由利用平滑面13a使相互之微凸塊13重合,從而能夠將一半導體晶片1與另一半導體晶片1位置精度較高地積層。由此,即便於將3片以上之多個半導體晶片1積層之情形時,亦能夠以相互之半導體晶片1之間之位置精度較高之狀態進行積層。藉由於如此之狀態下執行接合步驟S4,能夠將半導體晶片1與半導體晶片1位置精度較高地接合。 於積層步驟S3中,對於所有半導體晶片1,相互之微凸塊13以不接合之狀態重合,於接合步驟S4中,可藉由一次之加熱使所有微凸塊13一併熔融,從而將所有半導體晶片1一併接合。由此,能夠防止微凸塊13一次熔融接合而成之接合部8被重複加熱。因此,能夠防止接合部8之強度降低。 一半導體晶片1之微凸塊13、及另一半導體晶片1之微凸塊13均含有Sn,於接合步驟S4中,可於還原環境內使一半導體晶片1之微凸塊13、及另一半導體晶片1之微凸塊13熔融。由此,形成於相互之微凸塊13之表面之氧化膜23被還原除去。又,因為相互之微凸塊13含有Sn,因此伴隨熔融而相互混合並一體化。伴隨此,藉由液化之微凸塊13之表面張力之作用,而修正一半導體晶片1與另一半導體晶片1之間之位置偏移(自對準效果)。 平滑面形成步驟S2具備加熱步驟S22,即,於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間,且以微凸塊13之熔點以上之溫度進行加熱,藉此除去微凸塊13之表面之氧化膜23,於加熱步驟S22中,可於微凸塊13上載置壓力賦予構件21。於加熱步驟S22中,於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間,以微凸塊13之熔點以上之溫度進行加熱,藉此除去微凸塊13之表面之氧化膜23。由此,與形成於微凸塊13之表面之氧化膜23被還原除去同時地,該微凸塊13藉由熔融而具有流動性。於此,於加熱步驟S22中,於微凸塊13上載置有壓力賦予構件21。因此,伴隨微凸塊13熔融而具有流動性,微凸塊13藉由壓力賦予構件21之壓力而以壓潰之方式變形。藉由該變形而於微凸塊13內產生流動,空泡22於微凸塊13內流動。由此,於微凸塊13內流動之空泡22自該微凸塊13內排出至外部而被除去。進而,熔融之微凸塊13內被壓力賦予構件21按壓之部分跟隨該壓力賦予構件21之形狀而形成為平滑面13a。 本發明不限於上述之實施形態。 例如,如圖8所示,於基板11上配置具有固定厚度之間隔片26,壓力賦予構件21可被壓入直至與間隔片26接觸為止。由此,由於以間隔片26阻止壓力賦予構件21,因此能夠防止微凸塊13過度壓潰。例如,於加熱前,於微凸塊13之兩側配置間隔片26,且於微凸塊13載置壓力賦予構件21(參照圖8A)。於該狀態下以還原環境加熱而除去氧化膜(參照圖8B)。而且,當使微凸塊13熔融時,壓力賦予構件21下降,與間隔片26之上表面接觸(參照圖8C)。由此,壓力賦予構件21被間隔片26支持,不會進一步下降。另一方面,於熔融之微凸塊13內,因壓力賦予構件21之影響而產生流動,空泡22上升而被除去(參照圖8D~圖8G)。 又,於上述之實施形態中,下側之半導體晶片1之微凸塊13具有平滑面13a,上側之半導體晶片1之微凸塊13具有平滑面13a。因此,於下側之微凸塊13之平滑面13a上載置上側之微凸塊13之平滑面13a。然而,亦可僅於上側之微凸塊13與下側之微凸塊13之任一者形成平滑面13a,而於另一者不形成平滑面13a。 再者,半導體晶片1之積層片數並未特別限定,亦可為2片。 又,只要能夠使用壓力賦予構件21將空泡22自微凸塊13排出即可。即,根據壓力賦予構件21之形狀,亦可不於微凸塊13形成平滑面13a。 再者,作為半導體晶片1之使用例,例示使半導體晶片1積層而成之半導體封裝100。其中,成為半導體晶片1之接合對象之對象構件並未特別限定。 [實施例] 接下來,對本發明之實施例進行說明。但是,本發明並不限定於以下實施例。 (實施例1~7) 作為實施例1,製造具有如下微凸塊之半導體晶片。首先,以電解鍍覆法對基板進行鍍Cu、鍍Ni、及鍍Sn。將該基板配置於加熱爐內之後,調整加熱爐內之環境壓力,且調整對加熱爐供給之氮或甲酸氣之濃度及流量。由此,鍍覆膜熔融而製作形成有微凸塊之半導體晶片之樣品。鍍Cu層之高度為17 μm,鍍Ni層之高度為3 μm,微凸塊之高度為15 μm,微凸塊之直徑為35 μm。當以透過X射線觀察該樣品時,於微凸塊內觀察到空泡。準備該樣品與壓力賦予構件。壓力賦予構件係具有SiO2 膜之Si晶圓。以SiO2 面與凸塊相接之方式將Si晶圓載置於微凸塊之上。壓力賦予構件之重量就微凸塊之剖面積平均為0.0005 μg/μm2 。再者,未設置圖8所示之間隔片。於將載置有壓力賦予構件之狀態之半導體晶片配置於加熱爐內後,將加熱爐內抽真空至5 Pa以下為止。調整其後之加熱爐內之環境壓力,且調整對加熱爐供給之氮或甲酸氣之濃度、及流量。具體而言,以升溫速度45℃/min、預熱195℃(6分鐘)、最大260℃(1分鐘)之條件進行加熱。微凸塊被壓力賦予構件賦予壓力而形成有平滑面。如此獲得實施例1之微凸塊。 將使用就微凸塊之剖面積平均為0.002 μg/μm2 之壓力賦予構件而形成之微凸塊設為實施例2。將使用就微凸塊之剖面積平均為0.003 μg/μm2 之壓力賦予構件而形成之微凸塊設為實施例3。將使用就微凸塊之剖面積平均為0.01 μg/μm2 之壓力賦予構件而形成之微凸塊設為實施例4。將使用就微凸塊之剖面積平均為0.03 μg/μm2 之壓力賦予構件而形成之微凸塊設為實施例5。將使用就微凸塊之剖面積平均為0.06 μg/μm2 之壓力賦予構件而形成之微凸塊設為實施例6。實施例2~6之其他條件均與實施例1相同。又,設將30 μm之SUS(Steel Use Stainless,不鏽鋼)316製間隔片插入於壓力賦予構件與基板之間而形成之微凸塊為實施例7。實施例7中,使用就微凸塊之剖面積平均為0.03 μg/μm2 之壓力賦予構件。實施例7之其他條件均與實施例1相同。 (比較例1~7) 藉由於大氣中進行加熱而形成比較例1~7之微凸塊。比較例1中,使用就微凸塊之剖面積平均為0.001 μg/μm2 之壓力賦予構件。比較例2中,使用就微凸塊之剖面積平均為0.002 μg/μm2 之壓力賦予構件。比較例3中,使用就微凸塊之剖面積平均為0.003 μg/μm2 之壓力賦予構件。比較例4中,使用就微凸塊之剖面積平均為0.010 μg/μm2 之壓力賦予構件。比較例5中,使用就微凸塊之剖面積平均為0.03 μg/μm2 之壓力賦予構件。比較例6中,使用就微凸塊之剖面積平均為0.06g/ μm2 之壓力賦予構件。比較例7中,使用就微凸塊之剖面積平均為0.10 μg/μm2 之壓力賦予構件。比較例1~7之其他條件均與實施例1相同。 (評估) 將各實施例及各比較例之微凸塊之高度示於圖10之「微凸塊高度(μm)」。又,對於各實施例及各比較例中於回流焊後空泡減少者,於圖10之「空泡」示為「○」,對於空泡未減少者示為「×」。對於各實施例及各比較例中於回流焊後將壓力賦予構件自微凸塊除去而微凸塊不倒塌者,於圖10之「電極之倒塌」示為「○」,對於微凸塊倒塌者示為「×」。 如圖10所示,實施例1~6中確認到空泡減少之效果,亦無微凸塊之倒塌。但是,實施例6中,由於熔融之Sn流入至電極墊,故而示為「△」。實施例7中,由於藉由放入間隔片而使凸塊之高度與間隔片之厚度相同,故而有防止過度壓入之效果。因此,實施例7中,與實施例6相比,能夠確認到防止熔融之Sn流動至電極墊。另一方面,比較例1~6中,確認到未獲得空泡減少之效果。推測其原因在於,因於微凸塊之表面形成之氧化膜之影響而使得微凸塊難以變形,及表面較硬之氧化膜妨礙內部之流動性。又,比較例7中,因壓力賦予構件之重量過重而確認到微凸塊之倒塌。
1‧‧‧半導體晶片
1A‧‧‧半導體晶片
1B‧‧‧半導體晶片
1C‧‧‧半導體晶片
2‧‧‧積層體
3‧‧‧焊料球
4‧‧‧有機基板
6‧‧‧塑模部
7‧‧‧底部填料
8‧‧‧接合部
11‧‧‧基板
12‧‧‧導電部
13‧‧‧微凸塊
13a‧‧‧平滑面
14‧‧‧電極墊
16‧‧‧障壁金屬層
17‧‧‧絕緣層
19‧‧‧通孔電極
21‧‧‧壓力賦予構件
21a‧‧‧主面
22‧‧‧空泡
23‧‧‧氧化膜
26‧‧‧間隔片
100‧‧‧半導體封裝
P1‧‧‧曲線
P2‧‧‧曲線
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
S5‧‧‧步驟
S20‧‧‧步驟
S21‧‧‧步驟
S22‧‧‧步驟
S23‧‧‧步驟
T1‧‧‧溫度
T2‧‧‧溫度
圖1係表示包含半導體晶片之半導體封裝之一實施形態之概略剖面圖。 圖2係表示包含半導體晶片之半導體封裝之製造方法之順序之流程圖。 圖3A及圖3B係表示使半導體晶片積層之情況之概略剖面圖。 圖4A係表示使半導體晶片積層之情況之概略剖面圖,圖4B係表示將半導體晶片彼此接合之情況之概略剖面圖。 圖5係表示執行平滑面形成步驟之前之微凸塊、及執行平滑面形成步驟之後之微凸塊之概略剖面圖。 圖6係表示平滑面形成步驟(空泡除去步驟)之順序之流程圖。 圖7A~圖7G係表示平滑面形成步驟(空泡除去步驟)之順序之概略剖面圖。 圖8A~圖8G係表示變化例之平滑面形成步驟(空泡除去步驟)之順序之概略剖面圖。 圖9係表示加熱爐內之溫度與壓力之分佈之曲線圖。 圖10係表示實施例及比較例之試驗結果之表。

Claims (4)

  1. 一種半導體晶片之製造方法,其係具有基板、形成於上述基板上之導電部、及形成於上述導電部之微凸塊之半導體晶片之製造方法,且具備加熱步驟,即,於惰性環境內使還原性氣體流入至配置有上述半導體晶片之空間,以上述微凸塊之熔點以上之溫度進行加熱,使上述微凸塊熔融,上述加熱步驟中,於上述微凸塊上載置有壓力賦予構件。
  2. 如請求項1之半導體晶片之製造方法,其中,應用羧酸作為上述還原性氣體。
  3. 如請求項1之半導體晶片之製造方法,其中,上述壓力賦予構件之重量就上述微凸塊之剖面積平均為0.0005μg/μm2以上且0.1μg/μm2以下。
  4. 如請求項1之半導體晶片之製造方法,其中,於上述基板上配置具有固定厚度之間隔片,上述壓力賦予構件被壓入至與上述間隔片接觸為止。
TW107107068A 2017-03-03 2018-03-02 半導體晶片之製造方法 TWI672782B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/449,361 US10163847B2 (en) 2017-03-03 2017-03-03 Method for producing semiconductor package
US15/449,361 2017-03-03

Publications (2)

Publication Number Publication Date
TW201836103A TW201836103A (zh) 2018-10-01
TWI672782B true TWI672782B (zh) 2019-09-21

Family

ID=63355805

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107107068A TWI672782B (zh) 2017-03-03 2018-03-02 半導體晶片之製造方法

Country Status (4)

Country Link
US (2) US10163847B2 (zh)
KR (1) KR102181706B1 (zh)
CN (1) CN108538824B (zh)
TW (1) TWI672782B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102268390B1 (ko) * 2019-12-09 2021-06-23 삼성전기주식회사 전자 부품

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW404158B (en) * 1998-02-26 2000-09-01 Ibiden Co Ltd Multiple layer printed wiring plate with package conductive hole structure
TW200618685A (en) * 2004-08-20 2006-06-01 Ibm Compressible films surrounding solder connectors
TW200945528A (en) * 2008-03-17 2009-11-01 Ngk Spark Plug Co Wiring board having solder bump and method for manufacturing the same
TW201630970A (zh) * 2015-02-06 2016-09-01 富士通股份有限公司 助熔劑及電子裝置的製造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1013007A (ja) 1996-03-29 1998-01-16 Ngk Spark Plug Co Ltd 半田バンプを有する配線基板及びその製造方法及び平坦化治具
SG74729A1 (en) 1998-05-29 2000-08-22 Hitachi Ltd Method of forming bumps
EP1327264A1 (en) * 2000-10-17 2003-07-16 3M Innovative Properties Company Solvent assisted burnishing of pre-underfilled solder-bumped wafers for flipchip bonding
JP2004134645A (ja) * 2002-10-11 2004-04-30 Seiko Epson Corp バンプ付き半導体素子の実装方法、バンプ付き半導体素子の実装構造、及び電気光学装置、並びに電子機器
JP2005205418A (ja) 2004-01-20 2005-08-04 Denso Corp 接合構造体の製造方法
JP2005271059A (ja) 2004-03-26 2005-10-06 Toyota Motor Corp 接合構造体および接合構造体の製造方法
JP4373851B2 (ja) * 2004-05-28 2009-11-25 株式会社ディスコ 板状物に形成された電極の加工方法
KR20060134603A (ko) * 2005-06-23 2006-12-28 삼성전자주식회사 볼 범프를 평탄화한 적층 패키지 제조 방법
US20080164300A1 (en) 2007-01-08 2008-07-10 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with solder balls having roughened surfaces, method of making electrical assembly including said circuitized substrate, and method of making multiple circuitized substrate assembly
JP5031677B2 (ja) 2008-06-18 2012-09-19 シャープ株式会社 接合構造体の製造方法
WO2010061428A1 (ja) 2008-11-28 2010-06-03 富士通株式会社 電子装置の製造方法、電子部品搭載用基板及びその製造方法
JP5378078B2 (ja) 2009-06-19 2013-12-25 株式会社東芝 半導体装置の製造方法
US11134598B2 (en) * 2009-07-20 2021-09-28 Set North America, Llc 3D packaging with low-force thermocompression bonding of oxidizable materials
JP4901933B2 (ja) * 2009-09-29 2012-03-21 株式会社東芝 半導体装置の製造方法
JP5807221B2 (ja) 2010-06-28 2015-11-10 アユミ工業株式会社 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム
TWI453845B (zh) 2011-01-05 2014-09-21 Toshiba Kk 半導體裝置之製造方法
JP2013083619A (ja) 2011-09-27 2013-05-09 Elpida Memory Inc 半導体チップ、半導体装置、及びその測定方法
JP5870261B2 (ja) * 2011-10-03 2016-02-24 パナソニックIpマネジメント株式会社 半導体素子の実装方法
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
JP6547745B2 (ja) 2014-06-27 2019-07-24 ソニー株式会社 半導体装置およびその製造方法
JP6602544B2 (ja) * 2015-03-06 2019-11-06 三菱重工業株式会社 接合方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW404158B (en) * 1998-02-26 2000-09-01 Ibiden Co Ltd Multiple layer printed wiring plate with package conductive hole structure
TW200618685A (en) * 2004-08-20 2006-06-01 Ibm Compressible films surrounding solder connectors
TW200945528A (en) * 2008-03-17 2009-11-01 Ngk Spark Plug Co Wiring board having solder bump and method for manufacturing the same
TW201630970A (zh) * 2015-02-06 2016-09-01 富士通股份有限公司 助熔劑及電子裝置的製造方法

Also Published As

Publication number Publication date
CN108538824B (zh) 2021-08-17
TW201836103A (zh) 2018-10-01
US10354973B2 (en) 2019-07-16
KR20180101247A (ko) 2018-09-12
US20190013293A1 (en) 2019-01-10
CN108538824A (zh) 2018-09-14
KR102181706B1 (ko) 2020-11-23
US20180254255A1 (en) 2018-09-06
US10163847B2 (en) 2018-12-25

Similar Documents

Publication Publication Date Title
TWI668817B (zh) 半導體封裝之製造方法
US8530360B2 (en) Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US9263426B2 (en) PoP structure with electrically insulating material between packages
US7867842B2 (en) Method and apparatus for forming planar alloy deposits on a substrate
US8409919B2 (en) Method for manufacturing semiconductor device
JP6004441B2 (ja) 基板接合方法、バンプ形成方法及び半導体装置
US20120077312A1 (en) Flip-chip bonding method to reduce voids in underfill material
US20070182019A1 (en) Semiconductor device and manufacturing method for the same
CN111095508A (zh) 半导体元件的安装构造以及半导体元件与基板的组合
TWI669792B (zh) 半導體晶片之製造方法
JP5035134B2 (ja) 電子部品実装装置及びその製造方法
JP4569605B2 (ja) 半導体装置のアンダーフィルの充填方法
TWI672782B (zh) 半導體晶片之製造方法
JP2003318363A (ja) 突起電極接合型半導体装置およびその製造方法
JP2014082526A (ja) 電子機器の製造方法
WO2023153163A1 (ja) フリップチップ実装構造およびフリップチップ実装方法
JP2010232671A (ja) 半導体装置のアンダーフィル充填方法