TWI668817B - 半導體封裝之製造方法 - Google Patents

半導體封裝之製造方法 Download PDF

Info

Publication number
TWI668817B
TWI668817B TW107107052A TW107107052A TWI668817B TW I668817 B TWI668817 B TW I668817B TW 107107052 A TW107107052 A TW 107107052A TW 107107052 A TW107107052 A TW 107107052A TW I668817 B TWI668817 B TW I668817B
Authority
TW
Taiwan
Prior art keywords
microbumps
micro
bumps
semiconductor wafer
semiconductor
Prior art date
Application number
TW107107052A
Other languages
English (en)
Other versions
TW201838109A (zh
Inventor
折笠誠
清家英之
堀川雄平
阿部寿之
Original Assignee
日商 Tdk 股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商 Tdk 股份有限公司 filed Critical 日商 Tdk 股份有限公司
Publication of TW201838109A publication Critical patent/TW201838109A/zh
Application granted granted Critical
Publication of TWI668817B publication Critical patent/TWI668817B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明之半導體封裝之製造方法係使複數片半導體晶片積層而成之半導體封裝之製造方法，該半導體晶片具有基板、形成於基板上之導電部及形成於導電部之微凸塊，且該製造方法具備：平滑面形成步驟，其係於微凸塊形成平滑面；積層步驟，其係藉由於一半導體晶片之微凸塊重合另一半導體晶片之微凸塊，而積層3片以上之半導體晶片；接合步驟，其係藉由將微凸塊加熱使之熔融，而經由該微凸塊將半導體晶片彼此接合；且於積層步驟中，於一半導體晶片與另一半導體晶片中之至少一者之微凸塊形成平滑面，其中一者之微凸塊於平滑面與另一者之微凸塊接觸。

Description

半導體封裝之製造方法
本發明涉及半導體封裝之製造方法。
一直以來，於半導體封裝之三維安裝中，使用引線接合進行半導體晶片與半導體晶片、或中介板之連接。替代該引線接合而開發有經由貫通電極與凸塊將半導體晶片彼此連接之三維安裝技術。貫通電極通常成為較短之連接線長(例如50 μm)，且將電極間相連之凸塊亦要求為微細者。與此種低於50 μm之凸塊間距相對應之技術被稱作微凸塊。如美國專利第9136159號說明書，藉由將半導體晶片與半導體晶片以貫通電極與微凸塊連接，而能夠顯著地縮短半導體晶片間之配線長度。因此，能夠降低伴隨微細化而增大之配線延遲時間。
於此，半導體晶片與半導體晶片之積層藉由倒裝晶片安裝來進行。然而，於將半導體晶片與半導體晶片積層複數片並進行接合時，產生半導體晶片間之位置偏移等問題。 如此本發明係鑒於此種情況而完成者，其目的在於，提供一種能夠位置精度較高地將半導體晶片與半導體晶片接合之半導體封裝之製造方法。 本發明之一方面之半導體封裝之製造方法係使複數片半導體晶片積層而成之半導體封裝之製造方法，該半導體封裝具有基板、形成於基板上之導電部與形成於導電部之微凸塊，該製造方法具備：平滑面形成步驟，其係於微凸塊形成平滑面；積層步驟，其係藉由於一半導體晶片之微凸塊重合另一半導體晶片之微凸塊，而將半導體晶片積層3片以上；及接合步驟，其係藉由將微凸塊加熱使之熔融，而經由該微凸塊將半導體晶片彼此接合；且於積層步驟中，於一半導體晶片與另一半導體晶片中之至少一者之微凸塊形成平滑面，其中一者之微凸塊於平滑面與另一者之微凸塊接觸。 於該半導體封裝之製造方法中，於積層步驟中，於一半導體晶片與另一半導體晶片中之至少一者之微凸塊形成平滑面，其中一者之微凸塊藉由平滑面與另一者之微凸塊接觸。如此，藉由利用平滑面使相互之微凸塊重合，從而能夠將一半導體晶片與另一半導體晶片位置精度較高地積層。由此，即便於將3片以上之複數個半導體晶片積層之情形時，亦能夠以相互之半導體晶片之間之位置精度較高之狀態進行積層。藉由於如此之狀態下進行接合步驟，能夠將半導體晶片與半導體晶片位置精度較高地接合。 於積層步驟中，對於所有半導體晶片，將相互之微凸塊以未接合之狀態重合，於接合步驟中，可藉由一次之加熱而使所有微凸塊一併熔融，從而將所有半導體晶片一併接合。由此，能夠防止一度將微凸塊熔融接合而成之接合部被重複加熱。因此，能夠防止接合部之強度降低。 亦可為，一半導體晶片之微凸塊、及另一半導體晶片之微凸塊均包含Sn，於接合步驟中，於還原環境內使一半導體晶片之微凸塊以及另一半導體晶片之微凸塊熔融。由此，形成於相互之微凸塊之表面之氧化膜被還原除去。又，因為相互之微凸塊含有Sn，因此伴隨熔融而相互混合並一體化。伴隨此，藉由液化之微凸塊之表面張力之作用而修正一半導體晶片與另一半導體晶片之間之位置偏移(自對準效應)。 亦可為，平滑面形成步驟具備加熱步驟，即，於惰性環境內使還原性氣體流入至配置有半導體晶片之空間，以微凸塊之熔點以上之溫度進行加熱，於加熱步驟中，可於微凸塊上載置壓力賦予構件。於加熱步驟中，於惰性環境內使還原性氣體流入至配置有半導體晶片之空間而進行加熱。由此，形成於微凸塊之表面之氧化膜被還原除去。又，於加熱步驟中，藉由以微凸塊之熔點以上之溫度進行加熱，微凸塊熔融而具有流動性。於此，於加熱步驟中，於微凸塊上載置有壓力賦予構件。因此，伴隨微凸塊熔融而具有流動性，藉由壓力賦予構件之壓力，微凸塊以壓潰之方式變形。藉由該變形，於微凸塊內產生流動，空泡於微凸塊內流動。由此，於微凸塊內流動之空泡自該微凸塊內排出至外部而被除去。進而，熔融之微凸塊內被壓力賦予構件按壓之部分跟隨該壓力賦予構件之形狀而形成為平滑面。 根據本發明，能夠提供一種可將半導體晶片與半導體晶片位置精度較高地接合之半導體封裝之製造方法。
以下，參照附圖詳細說明本發明之一方面之半導體封裝之製造方法之較佳實施形態。再者，於以下之說明中，對同一要素或具有同一功能之要素使用同一符號，並省略重複之說明。 圖1係表示半導體封裝之一實施形態之概略剖面圖。如圖1所示，半導體封裝100具備使3片以上(於此為3片)之半導體晶片1積層而構成之積層體2、經由焊料球3與積層體2電性連接之有機基板4、藉由以塑模樹脂覆蓋安裝於有機基板4上之積層體2而形成之塑模部6。再者，塑模部6之內部空間以填埋積層體2之半導體晶片1之間之方式被填充有底部填料7。於本實施形態中，積層體2係藉由使半導體晶片1A、半導體晶片1B、及半導體晶片1C於上下方向上積層而構成。半導體晶片1A與半導體晶片1B經由藉由使微凸塊熔融接合而成之接合部8進行接合。半導體晶片1C與半導體晶片1B經由藉由使微凸塊熔融接合而成之接合部8進行接合。 例如，如圖4A所示，接合前之半導體晶片1具有基板11、形成於基板11上之導電部12、及形成於導電部12之微凸塊13。基板11由例如矽(Si)晶片等半導體晶片、矽(Si)中介板等構成。再者，於半導體晶片1A及半導體晶片1C，僅於一主面形成有導電部12。於半導體晶片1B，於兩主面形成有導電部12。又，形成於半導體晶片1B之兩主面之導電部12經由沿基板11之厚度方向延伸之通孔電極19而相互連接。 導電部12於基板11之主面上形成有複數個。導電部12以特定之間距排列於基板11之主面上。導電部12具備形成於基板11之主面上之電極墊14、及形成於電極墊14之上表面之障壁金屬層16。再者，基板11之主面中未形成導電部12之部分由絕緣層17覆蓋(參照圖5)。作為障壁金屬層16之構成材料，可使用例如Ni及Ni化合物(例如NiP)等。作為絕緣層17之構成材料，可使用例如SiO、SiN、聚醯亞胺等。 微凸塊13形成於導電部12之障壁金屬層16上。微凸塊13可含有Sn、Ag、Cu、Ag-Cu、Bi、In等作為構成材料，亦可使用包含該些中之任意兩種以上之材料之合金。特別是，微凸塊13亦可含有Sn作為主成分。微凸塊13例如亦可利用鍍覆法來形成。或者，微凸塊13可藉由使用包含焊料合金之微小球而形成，亦可印刷漿料而形成。再者，將俯視觀察時之直徑小於50 μm之凸塊稱作微凸塊。 如圖5所示，微凸塊13於剛形成於基板11之後不久具有球面。藉由對此種微凸塊13實施特定之處理，而於微凸塊13形成平滑面13a。平滑面13a由在微凸塊13之上端部沿水平方向擴展之平面構成。再者，下文敍述用以形成平滑面13a之處理內容之一例。微凸塊13之高度、即平滑面13a與導電部12之上表面之間之尺寸可於5～50 μm之範圍設定。 其次，參照圖2～圖9說明本實施形態之半導體封裝100之製造方法。 如圖2所示，首先，執行藉由於基板11上形成微凸塊13而準備半導體晶片1之半導體晶片準備步驟(步驟S1)。藉此，準備半導體晶片1A、1B、1C。其中，於該階段，未於微凸塊13形成平滑面13a。 其次，執行於微凸塊13形成平滑面13a之平滑面形成步驟(步驟S2)。又，平滑面形成步驟S2亦相當於自微凸塊13之內部除去空泡22之空泡除去步驟。 於此，參照圖6說明平滑面形成步驟(空泡除去步驟)S2之詳細內容。 如圖6及圖7A所示，執行相對於微凸塊13設置壓力賦予構件21之壓力賦予構件設置步驟(步驟S20)。如此，於載置有壓力賦予構件21之狀態下，將半導體晶片1配置於加熱爐之內部。再者，於以後之說明中，適當參照圖9所示之加熱爐內之溫度與壓力之分佈進行說明。再者，圖9中，實線表示加熱爐內之溫度，虛線表示加熱爐內之壓力。 作為載置於微凸塊13上之壓力賦予構件21之構成材料，較佳為採用不與微凸塊13反應之材料。例如，作為壓力賦予構件21之構成材料，可採用Si、SiO2 、SiN等。又，壓力賦予構件21之主面中、與微凸塊13相接之主面21a較佳為構成為平面。例如，於在主面21a形成有突起等之情形時，由於與微凸塊13牽絆，因此於除去壓力賦予構件21時不易脫落。壓力賦予構件21對微凸塊13賦予之壓力較佳為僅為壓力賦予構件21自身之自重。具體而言，壓力較佳為就微凸塊之剖面積平均為0.0005 μg/μm2 以上且0.1 μg/μm2 以下。例如，若以倒裝晶片安裝般之方法來控制壓力賦予構件21之壓力、或高度，則於微凸塊13自固體變化為液體時(自圖7B向圖7C變化時)施加於壓力賦予構件21之壓力降低，因此，於壓力賦予構件21之位置產生偏移。會因輕微之偏移而對如微凸塊13般較小之凸塊過度地施加壓力。 其次，執行將配置有半導體晶片1之加熱爐之空間減壓之減壓步驟(步驟S21)。於減壓步驟S21中，將加熱爐內抽真空而形成減壓環境。殘留於加熱爐內之氧會引起微凸塊13氧化。因此，較佳為將加熱爐內排氣至大氣壓狀態(自1.01×10^5 Pa至1×10^3 Pa以下，特別是5 Pa以下)之減壓狀態。由此，加熱爐內之壓力降低(參照圖9之曲線P1之部分)。對此種減壓環境之加熱爐內導入惰性氣體。由此，加熱爐內之壓力上升(參照圖9之曲線P2之部分)。惰性氣體於使加熱爐內上升至微凸塊13之熔融溫度以上(熔點以上)之溫度域時，一面防止微凸塊13之表面之進一步氧化，一面實現微凸塊13之熔融，作為加熱爐內之熱媒介發揮功能。作為此種惰性氣體，可使用例如氮(N2 )氣或氬(Ar)氣等。 其次，執行於惰性環境內對加熱爐流入還原性氣體，並以微凸塊13之熔點以上之溫度加熱之加熱步驟(步驟S22)。加熱步驟S22係於對加熱爐內導入惰性氣體之後、或者與導入惰性氣體大致同時執行。於加熱步驟S22中，以特定之升溫速度(例如35～45℃/分鐘)將加熱爐內升溫，使導入有惰性氣體之狀態之加熱爐內之溫度上升至微凸塊13之熔點以上之溫度域為止。例如，於由Sn-Ag-Cu合金構成凸塊之情形時，熔點雖然根據合金之組成而不同，但大致為220～230℃，因此，使加熱爐內之溫度上升至此種溫度以上之溫度域為止。 還原性氣體之導入較佳為於氧化膜23開始還原反應之溫度之前後實施。一面將加熱爐內之溫度(圖9之溫度T1)維持於開始還原反應之溫度以上，一面持續供給適當之溫度與流量之還原性氣體。由此，能夠將存在於微凸塊13之表面之氧化膜23還原除去。作為還原性氣體，例如可應用羧酸(甲酸)。作為羧酸之例子，可舉出甲酸、乙酸、丙烯酸、丙酸等低級羧酸。於使用甲酸作為還原氣體之情形時，較佳為於加熱爐內之溫度成為110℃左右時導入甲酸。即便於開始還原反應之溫度以下導入甲酸，反應亦不進行，而若溫度過高，由於係於殘留有表面之氧化膜23之狀態下加熱微凸塊13，因此，空泡22內部之壓力上升。當於空泡22之內部之壓力過度提高之狀態下除去氧化膜23時，空泡22之壓力被一下子釋放，液化之微凸塊13亦可能飛散。因此，可於開始還原反應之溫度T1維持特定時間，於氧化膜23被充分除去之階段將加熱爐之溫度維持於微凸塊13之熔點以上之溫度T2(參照圖9)。 當微凸塊13熔融而將空泡22除去，形成平滑面13a後，執行將加熱爐之溫度降溫之降溫步驟(步驟S23)。具體而言，於維持於微凸塊13之熔融溫度以上之溫度T2之加熱爐內將微凸塊13暴露於甲酸中特定時間(例如0.5～3分鐘)後，將導入至加熱爐內之甲酸抽真空排出。於將加熱爐內之甲酸排氣後、或者與甲酸之排氣同時地，以特定之降溫速度(例如-5～-40℃/分鐘)將加熱爐內降溫。再者，圖9中，於加熱爐之溫度下降之前進行抽真空。然而，於加熱爐內之溫度降溫至熔融之凸塊固化某種程度之溫度域為止後，可對加熱爐內導入氮氣或氬氣等惰性氣體而恢復至大氣壓。 藉由執行上述般之加熱步驟S22及降溫步驟S23，如圖7B～圖7G所示，能自微凸塊13除去空泡22，並且於微凸塊13形成平滑面13a。即，藉由於還原性氣體之環境下進行加熱，而可將形成於微凸塊13之表面之氧化膜23還原除去(參照圖7B)。而且，藉由以微凸塊13之熔點以上之溫度進行加熱而微凸塊13熔融。藉此，藉由壓力賦予構件21之壓力而使微凸塊13以壓潰之方式變形。由此，對應於壓力賦予構件21之主面21a之形狀，而於微凸塊13形成與平滑面13a相對應之形狀(參照圖7C～圖7F)。又，藉由熔融之微凸塊13被壓力賦予構件21按壓而流動，從而微凸塊13內之空泡22上升被排出到外部(參照圖7C～圖7F)。藉由加熱爐之溫度恢復而微凸塊13被冷卻固化。由此，於微凸塊13形成平滑面13a(參照圖7G)。 返回至圖2，針對各半導體晶片1之平滑面形成步驟S2完成後，執行於一半導體晶片1之微凸塊13重合另一半導體晶片1之微凸塊13，藉此積層3片以上之半導體晶片1之積層步驟(步驟S3)。於本實施形態中，於積層步驟S3中，於一半導體晶片1與另一半導體晶片1之微凸塊13形成有平滑面13a。而且，一半導體晶片1之微凸塊13於平滑面13a與另一微凸塊13接觸。於積層步驟S3中，對於所有半導體晶片1，相互之微凸塊13以不接合之狀態重合。 具體而言，如圖3A及圖3B所示，於最下方之半導體晶片1C之微凸塊13重合半導體晶片1B之微凸塊13。此時，於半導體晶片1C之微凸塊13之平滑面13a之上載置半導體晶片1B之微凸塊13之平滑面13a。又，半導體晶片1C之微凸塊13與半導體晶片1B之微凸塊13為相互不接合而僅簡單接觸之狀態。 其次，如圖3B及圖4A所示，於自下數第2個半導體晶片1B之微凸塊13重合最上方之半導體晶片1C之微凸塊13。此時，於半導體晶片1B之微凸塊13之平滑面13a之上載置半導體晶片1C之微凸塊13之平滑面13a。又，半導體晶片1B之微凸塊13與半導體晶片1C之微凸塊13為相互不接合而僅簡單接觸之狀態。 積層步驟S3完成後，執行藉由加熱微凸塊13使其熔融，而經由該微凸塊13將半導體晶片1彼此接合之接合步驟(步驟S4)。於接合步驟S4中，藉由一次之加熱將所有微凸塊13一併熔融而將所有半導體晶片1一併接合。又，於接合步驟S4中，於還原環境內使各半導體晶片1之微凸塊13熔融。 具體而言，如圖4A所示，將隔著微凸塊13積層半導體晶片1A、1B、1C之狀態之積層體配置於加熱爐內。然後，藉由以加熱爐加熱該積層體而積層體內之所有微凸塊13熔融，並且相互接觸之微凸塊13一併接合。由此，如圖4B所示，半導體晶片1A、1B、1C經由2個微凸塊13熔融而相互結合而成之接合部8接合。 於接合步驟S4完成後，執行製作半導體封裝100之半導體封裝製作步驟(步驟S5)。於半導體封裝製作步驟S5中，將於接合步驟S5得到之積層體2與有機基板4連接，並且，以塑模部6覆蓋積層體2。藉由如上步驟而完成半導體封裝100，圖2所示之製造方法結束。 其次，對本實施形態之半導體封裝100之製造方法之作用及效果進行說明。 於半導體封裝100之製造方法中，於加熱步驟S22中，於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間而進行加熱。藉此，形成於微凸塊13之表面之氧化膜23被還原除去。又，藉由以微凸塊13之熔點以上之溫度進行加熱而微凸塊13熔融，由此具有流動性。於此，於加熱步驟S22中，於微凸塊13上載置壓力賦予構件21。因此，伴隨微凸塊13熔融而具有流動性，藉由壓力賦予構件21之壓力而微凸塊13以壓潰之方式變形。藉由該變形，於微凸塊13內產生流動，從而空泡22於微凸塊13內流動。由此，於微凸塊13內流動之空泡22自該微凸塊13內排出至外部而被除去。藉由如上步驟，能夠容易地除去微凸塊13內之空泡22。 作為還原性氣體，可應用羧酸。由此，能夠良好地除去微凸塊13表面之氧化膜23。 就壓力賦予構件21之重量而言，就微凸塊13之剖面積，平均可為0.0005 μg/μm2 以上且0.1 μg/μm2 以下。由此，壓力賦予構件21能夠對微凸塊13賦予用以除去空泡22之適當之壓力。 於半導體封裝100之製造方法中，於積層步驟S3中，於一半導體晶片1與另一半導體晶片1中之至少一者之微凸塊13形成平滑面13a，其中一者之微凸塊13於平滑面13a與另一者之微凸塊13接觸。如此，藉由利用平滑面13a使相互之微凸塊13重合，從而能夠將一半導體晶片1與另一半導體晶片1位置精度較高地積層。由此，即便於將3片以上之多個半導體晶片1積層之情形時，亦能夠以相互之半導體晶片1之間之位置精度較高之狀態進行積層。藉由於如此之狀態下執行接合步驟S4，能夠將半導體晶片1與半導體晶片1位置精度較高地接合。 於積層步驟S3中，對於所有半導體晶片1，相互之微凸塊13以不接合之狀態重合，於接合步驟S4中，可藉由一次之加熱使所有微凸塊13一併熔融，從而將所有半導體晶片1一併接合。由此，能夠防止微凸塊13一次熔融接合而成之接合部8被重複加熱。因此，能夠防止接合部8之強度降低。 一半導體晶片1之微凸塊13、及另一半導體晶片1之微凸塊13均含有Sn，於接合步驟S4中，可於還原環境內使一半導體晶片1之微凸塊13、及另一半導體晶片1之微凸塊13熔融。由此，形成於相互之微凸塊13之表面之氧化膜23被還原除去。又，因為相互之微凸塊13含有Sn，因此伴隨熔融而相互混合並一體化。伴隨此，藉由液化之微凸塊13之表面張力之作用，而修正一半導體晶片1與另一半導體晶片1之間之位置偏移(自對準效果)。 平滑面形成步驟S2具備加熱步驟S22，即，於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間，且以微凸塊13之熔點以上之溫度進行加熱，藉此除去微凸塊13之表面之氧化膜23，於加熱步驟S22中，可於微凸塊13上載置壓力賦予構件21。於加熱步驟S22中，於惰性環境內使還原性氣體流入至配置有半導體晶片1之空間，以微凸塊13之熔點以上之溫度進行加熱，藉此除去微凸塊13之表面之氧化膜23。由此，與形成於微凸塊13之表面之氧化膜23被還原除去同時地，該微凸塊13藉由熔融而具有流動性。於此，於加熱步驟S22中，於微凸塊13上載置有壓力賦予構件21。因此，伴隨微凸塊13熔融而具有流動性，微凸塊13藉由壓力賦予構件21之壓力而以壓潰之方式變形。藉由該變形而於微凸塊13內產生流動，空泡22於微凸塊13內流動。由此，於微凸塊13內流動之空泡22自該微凸塊13內排出至外部而被除去。進而，熔融之微凸塊13內被壓力賦予構件21按壓之部分跟隨該壓力賦予構件21之形狀而形成為平滑面13a。 本發明不限於上述之實施形態。 例如，如圖8所示，於基板11上配置具有固定厚度之間隔片26，壓力賦予構件21可被壓入至與間隔片26接觸為止。由此，由於以間隔片26阻止壓力賦予構件21，因此能夠防止微凸塊13過度壓潰。例如，於加熱前，於微凸塊13之兩側配置間隔片26，且於微凸塊13載置壓力賦予構件21(參照圖8A)。於該狀態下以還原環境加熱而除去氧化膜(參照圖8B)。而且，當使微凸塊13熔融時，壓力賦予構件21下降，與間隔片26之上表面接觸(參照圖8C)。由此，壓力賦予構件21被間隔片26支持，不會進一步下降。另一方面，於熔融之微凸塊13內，因壓力賦予構件21之影響而產生流動，空泡22上升而被除去(參照圖8D～圖8G)。 又，於上述之實施形態中，下側之半導體晶片1之微凸塊13具有平滑面13a，上側之半導體晶片1之微凸塊13具有平滑面13a。因此，於下側之微凸塊13之平滑面13a上載置上側之微凸塊13之平滑面13a。然而，亦可僅於上側之微凸塊13與下側之微凸塊13之任一者形成平滑面13a，而於另一者不形成平滑面13a。 再者，於微凸塊13之平滑面形成步驟中，亦可利用任何方法形成平滑面13a。例如，亦可藉由對微凸塊13進行研磨而形成平滑面13a。然而，於藉由研磨形成平滑面13a之情形時，可能會產生由對微凸塊13及導電部12作用有力所致之損傷。另一方面，如上述之實施形態，於使用壓力賦予構件21形成平滑面13a之情形時，能夠抑制對微凸塊13及導電部12之損傷。 [實施例] 其次，對本發明之實施例進行說明。然而，本發明不限於以下之實施例。 (實施例1～4) 作為實施例1，製造具有如下微凸塊之半導體晶片。首先，以電解鍍覆法對基板進行鍍Cu、鍍Ni、及鍍Sn。將該基板配置於加熱爐內之後，調整加熱爐內之環境壓力，且調整對加熱爐供給之氮或甲酸氣之濃度及流量。由此，鍍覆膜熔融而製作形成有微凸塊之半導體晶片之樣品。鍍Cu層之高度為17 μm，鍍Ni層之高度為3 μm，微凸塊之高度為15 μm，微凸塊之直徑為35 μm。準備該樣品與壓力賦予構件。壓力賦予構件係具有SiO2 膜之Si晶圓。以SiO2 面與微凸塊相接之方式將Si晶圓載置於微凸塊之上。壓力賦予構件之重量就微凸塊之剖面積平均為0.0005 μg/μm2 。再者，未設置圖8所示之間隔片。於將載置有壓力賦予構件之狀態之半導體晶片配置於加熱爐內後，將加熱爐內抽真空至5 Pa以下為止。調整其後之加熱爐內之環境壓力，且調整對加熱爐供給之氮或甲酸氣之濃度、及流量。具體而言，以升溫速度45℃/min、預熱195℃(6分鐘)、最大260℃(1分鐘)之條件進行加熱。微凸塊被壓力賦予構件賦予壓力而形成有平滑面。準備具有此種微凸塊之半導體晶片，將3片半導體晶片積層並相互接合。再者，接合時之回流焊次數設為1次，於大氣中進行回流焊。將如此般得到之半導體晶片之積層體作為實施例1。 以於將半導體晶片彼此接合時，於氮及甲酸之環境中進行回流焊之情形作為實施例2。以將半導體晶片之積層片數設為5片之情形作為實施例3。以將半導體晶片之積層片數設為5片，並於將半導體晶片彼此接合時，於氮及甲酸之環境中進行回流焊之情形作為實施例4。實施例2～4之其他條件與實施例1完全相同。 (比較例1～7) 以將未形成平滑面之微凸塊重合之情形作為比較例1。以將半導體晶片之積層片數設為5片，並將未形成平滑面之微凸塊重合之情形作為比較例2。比較例1、2之其他條件與實施例1完全相同。 (評估) 為了評估微凸塊之搭載精度，於將第3片半導體晶片重合時，測定第1片與第2片半導體晶片之微凸塊之中心之位置偏移。對於實施例1～4及比較例1、2中之位置偏移小於5 μm之情形，於圖10之「積層精度」顯示「○」，對於位置偏移為5 μm以上之情形，於圖10之「積層精度」顯示「×」。為了測定微凸塊之剝離模式，將接合後之基板與基板剝離。對於實施例1～4及比較例1、2中之於微凸塊之內部破斷之情形，於圖10之「凸塊剝離模式」顯示「○」，對於在微凸塊與鍍Ni層之界面產生剝離、或裂紋之情形，於圖10之「凸塊剝離模式」顯示「×」。為了進行接合精度之評估，測定熔融接合後之微凸塊之中心之偏移。對於實施例1～4及比較例1、2中之、偏移小於5 μm之情形，於圖10之「接合精度」顯示「○」，對於偏移為5 μm以上且10 μm以下之情形，於圖10之「接合精度」顯示「Δ」，對於偏移大於10 μm之情形，於圖10之「接合精度」顯示「×」。 比較例1中，於重合第3片晶片時，其下方之晶片偏移。即，確認到比較例1中積層精度較低，因此接合精度亦降低。於比較例2中，藉由一片一片地接合而積層之精度、接合精度亦提高。然而，於比較例2中確認到，藉由重複回流焊而Ni與Sn之合金層成長，接合部之強度降低。於實施例1中確認到，因為微凸塊具有平滑面，因此於重合時偏移較少，接合精度亦提高。於實施例2中確認到，藉由於還原環境內進行回流焊而將氧化膜除去，且藉由利用熔融之Sn之表面張力之自對準效應而接合精度進一步提高。於實施例3、4中，因為將回流焊次數進行一次，因此接合部之強度降低較少。
1‧‧‧半導體晶片
1A‧‧‧半導體晶片
1B‧‧‧半導體晶片
1C‧‧‧半導體晶片
2‧‧‧積層體
3‧‧‧焊料球
4‧‧‧有機基板
6‧‧‧塑模部
7‧‧‧底部填料
8‧‧‧接合部
11‧‧‧基板
12‧‧‧導電部
13‧‧‧微凸塊
13a‧‧‧平滑面
14‧‧‧電極墊
16‧‧‧障壁金屬層
17‧‧‧絕緣層
19‧‧‧通孔電極
21‧‧‧壓力賦予構件
21a‧‧‧主面
22‧‧‧空泡
23‧‧‧氧化膜
26‧‧‧間隔片
100‧‧‧半導體封裝
P1‧‧‧曲線
P2‧‧‧曲線
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
S5‧‧‧步驟
S20‧‧‧步驟
S21‧‧‧步驟
S22‧‧‧步驟
S23‧‧‧步驟
T1‧‧‧溫度
T2‧‧‧溫度
圖1係表示半導體封裝之一實施形態之概略剖面圖。 圖2係表示半導體封裝之製造方法之順序之流程圖。 圖3A及圖3B係表示使半導體晶片積層之情況之概略剖面圖。 圖4A係表示使半導體晶片積層之情況之概略剖面圖，圖4B係表示將半導體晶片彼此接合之情況之概略剖面圖。 圖5係表示執行平滑面形成步驟之前之微凸塊、及執行平滑面形成步驟之後之微凸塊之概略剖面圖。 圖6係表示平滑面形成步驟(空泡除去步驟)之順序之流程圖。 圖7A～圖7G係表示平滑面形成步驟(空泡除去步驟)之順序之概略剖面圖。 圖8A～圖8G係表示變化例之平滑面形成步驟(空泡除去步驟)之順序之概略剖面圖。 圖9係表示加熱爐內之溫度與壓力之分佈之曲線圖。 圖10係表示實施例及比較例之試驗結果之表。

Claims (3)

  1. 一種半導體封裝之製造方法，上述半導體封裝係使具有基板、形成於上述基板上之導電部、及形成於上述導電部之微凸塊之半導體晶片積層複數片而成，上述製造方法具備：平滑面形成步驟，其係於上述微凸塊形成平滑面；積層步驟，其係藉由於一上述半導體晶片之上述微凸塊重合另一上述半導體晶片之上述微凸塊，而將上述半導體晶片積層3片以上；及接合步驟，其係藉由將上述微凸塊加熱使之熔融而經由該微凸塊將上述半導體晶片彼此接合；且於上述積層步驟中，於一上述半導體晶片與另一上述半導體晶片中之至少一者之上述微凸塊形成上述平滑面，其中一者之上述微凸塊於上述平滑面與另一者之上述微凸塊接觸；上述平滑面形成步驟具備加熱步驟，其於惰性環境內使還原性氣體流入至配置有上述半導體晶片之空間，以上述微凸塊之熔點以上之溫度進行加熱；於上述加熱步驟中，於上述微凸塊上載置壓力賦予構件。
  2. 如請求項1之半導體封裝之製造方法，其中，於上述積層步驟中，對於所有上述半導體晶片，相互之上述微凸塊於未接合之狀態下重合，於上述接合步驟中，藉由一次之加熱使所有上述微凸塊一併熔融而將所有上述半導體晶片一併接合。
  3. 如請求項1之半導體封裝之製造方法，其中，一上述半導體晶片之上述微凸塊、及另一上述半導體晶片之上述微凸塊均包含Sn，於上述接合步驟中，於還原環境內使一上述半導體晶片之上述微凸塊及另一上述半導體晶片之上述微凸塊熔融。
TW107107052A 2017-03-03 2018-03-02 半導體封裝之製造方法 TWI668817B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/449,074 2017-03-03
US15/449,074 US9818736B1 (en) 2017-03-03 2017-03-03 Method for producing semiconductor package

Publications (2)

Publication Number Publication Date
TW201838109A TW201838109A (zh) 2018-10-16
TWI668817B true TWI668817B (zh) 2019-08-11

Family

ID=60255698

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107107052A TWI668817B (zh) 2017-03-03 2018-03-02 半導體封裝之製造方法

Country Status (4)

Country Link
US (1) US9818736B1 (zh)
KR (1) KR102121176B1 (zh)
CN (1) CN108538736A (zh)
TW (1) TWI668817B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI831089B (zh) * 2020-11-27 2024-02-01 大陸商上海易卜半導體有限公司 半導體封裝方法、半導體元件以及包含其的電子設備

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102461313B1 (ko) 2020-05-19 2022-11-01 엠케이전자 주식회사 리버스 리플로우용 심재를 이용한 반도체 패키지
US11923307B2 (en) 2020-06-16 2024-03-05 Intel Corporation Microelectronic structures including bridges
US11804441B2 (en) 2020-06-16 2023-10-31 Intel Corporation Microelectronic structures including bridges
US11791274B2 (en) 2020-06-16 2023-10-17 Intel Corporation Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects
US11887962B2 (en) * 2020-06-16 2024-01-30 Intel Corporation Microelectronic structures including bridges
US11373972B2 (en) 2020-06-16 2022-06-28 Intel Corporation Microelectronic structures including bridges
CN117410216B (zh) * 2023-12-15 2024-02-27 江苏快克芯装备科技有限公司 芯片封装系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656750B1 (en) * 1999-04-29 2003-12-02 International Business Machines Corporation Method for testing chips on flat solder bumps
TW201230214A (en) * 2011-01-05 2012-07-16 Toshiba Kk Method for manufacturing semiconductor device
EP2575140A1 (en) * 2011-09-27 2013-04-03 Elpida Memory, Inc. Semiconductor chip, semiconductor device, and method of measuring the same
US8740047B2 (en) * 2008-11-28 2014-06-03 Fujitsu Limited Method of manufacturing electronic apparatus, electronic component-mounting board, and method of manufacturing the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005205418A (ja) 2004-01-20 2005-08-04 Denso Corp 接合構造体の製造方法
JP2005271059A (ja) 2004-03-26 2005-10-06 Toyota Motor Corp 接合構造体および接合構造体の製造方法
KR20060134603A (ko) * 2005-06-23 2006-12-28 삼성전자주식회사 볼 범프를 평탄화한 적층 패키지 제조 방법
JP5031677B2 (ja) 2008-06-18 2012-09-19 シャープ株式会社 接合構造体の製造方法
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
JP4901933B2 (ja) * 2009-09-29 2012-03-21 株式会社東芝 半導体装置の製造方法
JP5807221B2 (ja) 2010-06-28 2015-11-10 アユミ工業株式会社 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム
US8435881B2 (en) * 2011-06-23 2013-05-07 STAT ChipPAC, Ltd. Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation
TWI462194B (zh) * 2011-08-25 2014-11-21 Chipmos Technologies Inc 半導體封裝結構及其製作方法
JP5870261B2 (ja) * 2011-10-03 2016-02-24 パナソニックＩｐマネジメント株式会社 半導体素子の実装方法
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US9559071B2 (en) * 2013-06-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming hybrid bonding structures with elongated bumps
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
KR102506703B1 (ko) * 2014-12-16 2023-03-03 데카 테크놀로지 유에스에이 인코포레이티드 반도체 패키지를 마킹하는 방법
JP6602544B2 (ja) * 2015-03-06 2019-11-06 三菱重工業株式会社 接合方法
US10115703B2 (en) * 2015-03-17 2018-10-30 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof
KR102468773B1 (ko) * 2015-10-19 2022-11-22 삼성전자주식회사 반도체 소자
JP6584939B2 (ja) * 2015-12-10 2019-10-02 新光電気工業株式会社 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
KR20170070434A (ko) * 2015-12-14 2017-06-22 삼성전자주식회사 반도체 장치의 테스트 구조, 테스트 시스템 및 반도체 장치의 웨이퍼 레벨 테스트 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656750B1 (en) * 1999-04-29 2003-12-02 International Business Machines Corporation Method for testing chips on flat solder bumps
US8740047B2 (en) * 2008-11-28 2014-06-03 Fujitsu Limited Method of manufacturing electronic apparatus, electronic component-mounting board, and method of manufacturing the same
TW201230214A (en) * 2011-01-05 2012-07-16 Toshiba Kk Method for manufacturing semiconductor device
EP2575140A1 (en) * 2011-09-27 2013-04-03 Elpida Memory, Inc. Semiconductor chip, semiconductor device, and method of measuring the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI831089B (zh) * 2020-11-27 2024-02-01 大陸商上海易卜半導體有限公司 半導體封裝方法、半導體元件以及包含其的電子設備

Also Published As

Publication number Publication date
TW201838109A (zh) 2018-10-16
US9818736B1 (en) 2017-11-14
CN108538736A (zh) 2018-09-14
KR20180101252A (ko) 2018-09-12
KR102121176B1 (ko) 2020-06-10

Similar Documents

Publication Publication Date Title
TWI668817B (zh) 半導體封裝之製造方法
US8530360B2 (en) Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US7867842B2 (en) Method and apparatus for forming planar alloy deposits on a substrate
US9263426B2 (en) PoP structure with electrically insulating material between packages
US20150214207A1 (en) Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
TWI414049B (zh) 半導體裝置之製造方法
WO2013108323A1 (ja) 半導体装置製造方法および半導体装置
US7679188B2 (en) Semiconductor device having a bump formed over an electrode pad
US20110076801A1 (en) Method for manufacturing semiconductor device
TWI669792B (zh) 半導體晶片之製造方法
CN111095508A (zh) 半导体元件的安装构造以及半导体元件与基板的组合
JP5035134B2 (ja) 電子部品実装装置及びその製造方法
TWI484610B (zh) 半導體結構之製法與導電凸塊
TWI672782B (zh) 半導體晶片之製造方法
JPWO2020090601A1 (ja) 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
JP5187341B2 (ja) 半導体装置の製造方法
JP2012129482A (ja) 半導体装置の製造方法
TW202245559A (zh) 複合配線基板、半導體裝置及複合配線基板的製造方法
JP2022105279A (ja) 方法および装置（基板へのチップの組立て）
JP2013247194A (ja) 半導体装置の製造方法