US7867842B2 - Method and apparatus for forming planar alloy deposits on a substrate - Google Patents

Method and apparatus for forming planar alloy deposits on a substrate Download PDF

Info

Publication number
US7867842B2
US7867842B2 US12/181,852 US18185208A US7867842B2 US 7867842 B2 US7867842 B2 US 7867842B2 US 18185208 A US18185208 A US 18185208A US 7867842 B2 US7867842 B2 US 7867842B2
Authority
US
United States
Prior art keywords
substrate
plugs
solder
openings
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US12/181,852
Other versions
US20100028612A1 (en
Inventor
Peter Alfred Gruber
Paul Alfred Lauro
Jae-Woong Nah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US12/181,852 priority Critical patent/US7867842B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GRUBER, PETER ALFRED, LAURO, PAUL ALFRED, NAH, JAE-WOONG
Priority to US12/627,249 priority patent/US7906420B2/en
Publication of US20100028612A1 publication Critical patent/US20100028612A1/en
Application granted granted Critical
Publication of US7867842B2 publication Critical patent/US7867842B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Definitions

  • the present invention relates generally to electrical and electronic devices, and more particularly relates to semiconductor packaging and interconnection.
  • Flip chip technology first introduced in the 1960's by IBM as the controlled collapse chip connection (C4) process, offers a viable and proven alternative to standard assembly technologies for products requiring enhanced performance.
  • Flip chip is not a specific package (like SOIC), or even a package type (like BGA). Rather, flip chip generally describes the method of electrically connecting an integrated circuit (IC) die, also referred to as a chip, to a package carrier.
  • the package carrier either substrate or leadframe, then provides the connection from the die to the exterior of the package.
  • IC integrated circuit
  • the interconnection between the die and the carrier is made using bond wires, which exhibit disadvantages, particularly in high-frequency applications (e.g., about one gigahertz and above).
  • Flip chip has become popular primarily because it offers good electrical performance, small package size, and the capability of handling a relatively large number of input/output (I/O) connections.
  • Early flip chip processing employed solder bumps formed on chip I/O pads. These solder bumps align with corresponding pad sites on the substrate.
  • the solder bumped die is attached to the substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior.
  • underfill is added between the die and the substrate to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier. Once cured, the underfill absorbs the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package.
  • the die attach and underfill steps are the basics of flip chip interconnect.
  • Illustrative embodiments of the present invention provide techniques for forming substantially coplanar solder bumps on a substrate so as to beneficially increase the tolerance of the chip to substrate warpage compared to conventional solder bump formation approaches. Techniques of the present invention accomplish this in a manner which advantageously eliminates a coining of the solder bumps as a separate step. Furthermore, techniques of the invention achieve transfer of the solder bumps to the substrate without directly applying additional heat to the substrate, or applying heat that is not sufficient to fully melt the solder plugs once they are formed. Because conventional solder reflow is not required to transfer the solder bumps to the substrate, the invention has an advantage of not exposing the substrate to elevated temperature.
  • a method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier comprising at least a first decal including a first plurality of openings formed therein and a second decal including a second plurality of openings formed therein, the first and second decals being arranged in abutting contact with one another such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy in the first and second plurality of openings to thereby form at least first and second plugs, the first plug having a first surface and a second surface, the second surface being substantially parallel to the first surface, the second plug having a third surface and a fourth surface, the fourth surface being substantially parallel to the third surface; removing at least one of the first and second decals to at least partially expose at least the first and second plugs; aligning the alloy carrier
  • an integrated circuit comprising alloy deposits formed at selected areas on a substrate of the integrated circuit.
  • the alloy deposits are foamed on the substrate by a method including the steps of: providing an alloy carrier comprising at least a first decal including a first plurality of openings formed therein and a second decal including a second plurality of openings formed therein, the first and second decals being arranged in abutting contact with one another such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy in the first and second plurality of openings to thereby form at least first and second plugs, the first plug having a first surface and a second surface, the second surface being substantially parallel to the first surface, the second plug having a third surface and a fourth surface, the fourth surface being substantially parallel to the third surface; removing at least one of the first and second decals to at least partially
  • FIGS. 2A through 2G are cross-sectional views depicting an exemplary process for forming solder bumps on a substrate, in accordance with an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view depicting an exemplary packaged integrated circuit comprising coined solder bumps, in accordance with an embodiment of the present invention.
  • Stand-off height is an important factor affecting interconnect reliability. As stand-off height decreases, the tolerance for substrate warpage decreases accordingly, which can result in lower yield. Consequently, reliability of standard flip chip technology is often unacceptable when used in electronic packages employing high density interconnect substrates.
  • solder bumps are interconnection techniques for improving the tolerance of an IC packaging methodology to substrate and/or IC die warpage.
  • Substrate solder bumping helps increase assembly yield and the allowable stand-off height between the IC die and the substrate, and is therefore beneficial.
  • Solder bumps on the substrate compensate for height variation in the solder bumps on the die.
  • One approach to minimize the effects of substrate warpage on device reliability is to “coin” the solder bumps.
  • FIGS. 1A through 1H are cross-sectional views depicting an illustrative process 100 for forming coined solder bumps, or alternative alloy deposits, at selected areas on a receiving substrate using stencil printing followed by solder reflow and coining.
  • a substrate 101 is shown including a plurality of pads 160 formed on at least a portion of an upper surface of the substrate.
  • Substrate 101 may comprise, for example, an organic material, including, but not limited to flame retardant type 4 (FR-4), bismaleimide triazine (BT) resin, etc., or a semiconductor material, such as, for example, silicon, germanium, gallium arsenide, etc.
  • a stencil mask 110 is positioned over the substrate 101 .
  • the stencil mask 110 includes a plurality of openings 165 therein, each of the openings being aligned with a corresponding one of the underlying pads 160 .
  • a solder mask 170 may be employed (as shown) to prevent bridging of solder between adjacent pads 160 .
  • Solder mask 170 when used, is preferably formed on at least a portion of the upper surface of substrate 101 and under the stencil mask 110 .
  • solder mask 170 includes a plurality of openings 165 therein, each of the openings being aligned with a corresponding one of the pads 160 .
  • stencil printing is preferably performed by moving a squeegee 130 , or an alternative applicator, over stencil mask 110 to force a solder paste 120 into the holes in the stencil mask 110 .
  • the stencil mask 110 is then removed, exposing at least a portion of sidewalls and an upper surface of the resulting solder paste structure 120 , as shown in FIG. 1C . Since the solder paste is conductive, the solder paste structures 120 provide electrical connection to the corresponding pads 160 on the substrate 101 .
  • the solder paste By exposing the substrate to the elevated temperature, the solder paste will melt to form molten solder balls 121 against the upper surface of the solder mask 170 . During this process, residual flux 122 may form around part of the molten solder balls 121 . Heat is then removed and the molten solder balls 121 are subsequently cooled to form solid solder bumps 123 , as shown in FIG. 1E . In FIG. 1F , the residual flux 122 is preferably removed.
  • the solder bumps may have different heights (when measured in a vertical direction above the substrate) relative to one another, which can create yield problems during interconnection of the substrate 101 with an IC die (not shown) during the flip chip bonding process.
  • coining is used to flatten an upper surface of the solder bumps and ensures that the plurality of solder coins are substantially planar.
  • a stencil mask printing process of the type exemplified in FIGS. 1A through 1H can be used for fine pitch C4 substrate solder bumping of high density interconnect substrates for electronic packages.
  • this technique is limited in its applicability for future platforms, particularly with requirements of decreasing C4 pitch and solder bump sizes.
  • attempts at printing at very fine pitches e.g., less than about 120 ⁇ m
  • Another disadvantage of the stencil mask printing process is the requirement of an additional solder coining process after bump formation to form a flat surface.
  • FIGS. 2A through 2G are cross-sectional views depicting an exemplary process 200 for forming solder bumps on a substrate, in accordance with an embodiment of the present invention.
  • Techniques of the invention provide, for example, a method and apparatus for making substantially flat-topped solder features on a substrate using a simplified injection molded soldering (IMS) process. Upper surfaces of the respective solder features are substantially coplanar relative to one another.
  • IMS injection molded soldering
  • the illustrative IMS process advantageously eliminates the need for two-step processes of solder reflow step followed by a solder coining step, as required by the stencil printing process depicted in FIGS. 1A through 1H .
  • a decal solder alloy carrier 205 is formed including at least a first decal 210 and a second decal 220 .
  • the term “decal” generally refers to a structure (e.g., a mold) for forming and holding solder, which is initially in molten form when injected into the decal.
  • First and second decals are preferably held together using mechanical means (e.g., clamps, elastic, etc.). Although only two decals are depicted in the figure, it is to be understood that the present invention is not limited to any particular number of decals used to form the solder alloy carrier 205 .
  • Decal solder alloy carrier 205 is preferably formed of a material that is non-wettable by solder alloys typically used in the semiconductor technology field, i.e., a material that has no metallurgical affinity with, and thus does not metallurgically bond to the solder alloy.
  • decal solder alloy carrier 205 is formed of a material having a relatively low thermal expansion coefficient, particularly a thermal expansion coefficient sufficiently lower than that of a target substrate onto which the solder alloy is to be transferred.
  • First decal 210 need not be formed of the same material as that of second decal 220 , although the first and second decals may be formed of the same material.
  • Suitable materials for forming the decal solder alloy carrier 205 include, but are not limited to, polymer, silicon, germanium, gallium arsenide, glass, quartz, and like materials and/or compositions.
  • First decal 210 includes a first plurality of openings 211 therein adapted for carrying solder alloy.
  • second decal 220 includes a second plurality of openings 221 therein adapted for carrying solder alloy.
  • the openings 211 , 221 may be formed, for example, using a conventional laser drilling process and/or a photolithographic process, although alternative means for forming the openings are similarly contemplated (e.g., wet or dry etch, bulk micromachining, surface micromachining).
  • the first and second decals 210 , 220 are preferably arranged in abutting contact with one another such that each of the first plurality of openings 211 is in alignment with a corresponding one of the second plurality of openings 221 , as shown.
  • Openings 211 in the first decal 210 and corresponding opening 221 in the second decal 220 forms a composite opening 222 in the decal solder alloy carrier 205 .
  • Openings 211 and 221 do not have to be the same diameter or shape. In alternative embodiments in which more than two decals are employed, there will be openings in each decal that are aligned such that there are composite openings that are continuous through all the decals.
  • FIG. 2B depicts the first and second decals 210 , 220 after substantially filling composite openings 222 with molten solder 250 .
  • the molten solder 250 may be injected into composite openings according to an IMS process, for example, as described in U.S. Pat. No. 5,673,846, which is incorporated by reference herein, although other means may be employed for filling the composite openings.
  • IMS provides for injecting molten solder into the openings 222 formed in the decals 210 , 220 , and then cooling the solder down, or allowing the solder to cool, so that the solder solidifies within the openings, resulting in the formation of solid solder plugs 251 , as shown in FIG. 2C .
  • solder plugs 251 will not have as flat or as level an upper surface as desired.
  • second decal 220 is removed. Removal of the second decal 220 exposes at least a portion of solder plugs 251 , such as a lower portion, thereby allowing the solder plugs to extend through material intervening between first decal 210 and the target substrate for electrical connection to corresponding pads on the substrate.
  • the intervening material may be solder mask 170 formed on substrate 101 , as shown in FIG. 1A .
  • the solder plugs 251 preferably remain in first decal 210 without falling through since a first width, W 1 , of a given opening at an upper surface of the first decal is preferably larger than a second width, W 2 , of the opening at a bottom surface of the first decal.
  • the reach with which the exposed portions of the respective solder plugs 251 may extend through the intervening material for connection to the substrate will, inherently, be a function of the cross-sectional thickness of the second decal 220 (e.g., about 20 ⁇ m).
  • a layer of flux 270 may be formed on a bottom surface of each of the solder plugs 251 for improving solder wetting on the pads when the solder plugs are placed in contact with corresponding pads on the substrate so as to facilitate adhesion of the solder plugs to the corresponding pads on the substrate.
  • a formic acid vapor may be applied during the solder transfer process, wherein the formic acid vapor is operative to remove oxide layers and improve adhesion of the exposed solder to the pads.
  • solder plugs 251 in first decal 210 are substantially aligned to corresponding pads 160 formed on an upper surface of a substrate 101 .
  • a solder mask 170 may be optionally formed on the upper surface of the substrate 101 to prevent bridging of solder between adjacent pads 160 .
  • Solder mask 170 when used, includes a plurality of openings therein, each of the openings being aligned with a corresponding one of the pads 160 .
  • solder plugs 251 Under prescribed heat 262 and compressive force 261 applied to a bar 240 , or alternative structure suitable for uniformly transferring the compressive force and/or heat to solder plugs 251 , the solder plugs are bonded to the corresponding pads 160 . That is, solder plugs 251 are under sufficient pressure and heat for a sufficient time to bond to pads 160 .
  • the heat is preferably not sufficient to reflow the solder plugs; that is, the solder is not fully melted to form molten solder.
  • sufficient heat is applied to reflow the solder plugs 251 .
  • mechanical vibration may be applied to solder plugs 251 to assist in bonding to corresponding pads 160 .
  • vibrational wetting support can be used to supplement standard oxide removal methods.
  • bonding of the solder plugs 251 to corresponding pads 160 is performed under a compressive force 261 , without the addition of heat to the bar 240 .
  • this step preferably takes place in a heated environment, wherein the temperature of the environment may be slightly above the melting point of the solder material forming the solder plugs 251 (e.g., greater than about 180° C. for eutectic SnPb solder and about 220° C. for lead-free solder).
  • the solder material forming the solder plugs 251 does melt during transfer, the solder material is constrained by the surrounding geometry/structure, including the top compressive force. These constraining forces are applied until the solder material has solidified, and thus the solder plugs retain this shape.
  • FIG. 2E shows heat 262 and compressive force 261 applied to the bar 240 , and FIG.
  • FIG. 2F shows only compressive force 261 applied to the bar 240 , the invention is not so limited.
  • Heat 262 and compressive force 261 can, alternatively or in addition, be applied to the substrate 101 .
  • the compressive force 261 although shown as being applied to an upper surface of the solder plugs 251 , can, alternatively or in addition, be applied to a backside of the substrate 101 .
  • Mechanical vibration can be applied to the bar 240 , the substrate 101 , both the substrate and bar, or neither.
  • bar 240 Another function of bar 240 is to form substantially flat and level upper surfaces of solder plugs 251 , such that the upper surfaces of the solder plugs reside in substantially the same plane, i.e., coplanar.
  • Application of compressive force 261 to the bar 240 and/or the substrate 101 causes pressure between the bar 240 and solder plugs 251 .
  • the pressure between bar 240 and solder plugs 251 causes the upper surfaces of the respective solder plugs 251 to flatten and thereby become substantially coplanar with one another.
  • heat 262 when applied, assists in reshaping (reforming) the upper surfaces of solder plugs 251 so as to be substantially flat and coplanar relative to one another.
  • bar 240 and first decal 210 are preferably removed. Remaining are solder plugs 251 bonded on corresponding pads 160 formed on the upper surface of substrate 101 , and, optionally, solder mask 170 formed on the upper surface of the substrate.
  • compressive force 261 and/or heat 262 applied to the bar 240 preferably causes the solder alloy material forming the lower portion of solder plugs 251 to substantially fill openings in the solder mask 170 aligned with corresponding pads 160 . Accordingly, the lower portions of solder plugs 251 will take on the shape of the openings in solder mask 170 .
  • FIG. 3 is a partial cross-sectional view depicting an exemplary packaged integrated circuit 300 according to an embodiment of the present invention.
  • the packaged integrated circuit 300 comprises a leadframe 310 , or an alternative receiving substrate, a plurality of pads 340 formed on an upper surface of the leadframe, an integrated circuit die 320 , and a molded encapsulation 360 .
  • the die 320 is attached to the leadframe 310 by methods of this invention described herein. For example, bonding pads 330 formed on a bottom surface of die 320 may be electrically connected to corresponding pads 340 formed on the upper surface of leadframe 310 via solder plugs 350 .
  • Encapsulation 360 preferably surrounds the die/leadframe combination, as in a conventional manner.
  • FIG. 3 shows only one type of integrated circuit package, the invention is not so limited. Rather, the invention may comprise an integrated circuit die enclosed in essentially any package type.
  • At least a portion of the techniques of the present invention may be implemented in one or more integrated circuits.
  • die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Individual die are cut or diced from the wafer, then packaged as integrated circuits. In packaging the dies, individual die are attached to a receiving substrate according to methods of the invention. One skilled in the art would know how to dice wafers to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
  • An integrated circuit formed in accordance with interconnection techniques of the present invention can be employed in essentially any application and/or electronic system.
  • Suitable systems for implementing the invention may include, but are not limited to, personal computers, communication networks, portable communications devices (e.g., cell phones), etc. Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.

Abstract

A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.

Description

FIELD OF THE INVENTION
The present invention relates generally to electrical and electronic devices, and more particularly relates to semiconductor packaging and interconnection.
BACKGROUND OF THE INVENTION
Flip chip technology, first introduced in the 1960's by IBM as the controlled collapse chip connection (C4) process, offers a viable and proven alternative to standard assembly technologies for products requiring enhanced performance. Flip chip is not a specific package (like SOIC), or even a package type (like BGA). Rather, flip chip generally describes the method of electrically connecting an integrated circuit (IC) die, also referred to as a chip, to a package carrier. The package carrier, either substrate or leadframe, then provides the connection from the die to the exterior of the package. In “standard” IC packaging, the interconnection between the die and the carrier is made using bond wires, which exhibit disadvantages, particularly in high-frequency applications (e.g., about one gigahertz and above).
Flip chip has become popular primarily because it offers good electrical performance, small package size, and the capability of handling a relatively large number of input/output (I/O) connections. Early flip chip processing employed solder bumps formed on chip I/O pads. These solder bumps align with corresponding pad sites on the substrate. The solder bumped die is attached to the substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior. After the die is attached, underfill is added between the die and the substrate to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier. Once cured, the underfill absorbs the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package. The die attach and underfill steps are the basics of flip chip interconnect.
As flip chip technology is extended for use with chips having higher pin counts, smaller line-pitch and larger size, such as, for example, microprocessor chips and chipsets, the size of the solder bumps on the chip decreases, and thus the amount of tolerance to substrate warpage in the chip decreases accordingly. Consequently, reliability of standard flip chip technology is often unacceptable when used in such applications.
SUMMARY OF THE INVENTION
Illustrative embodiments of the present invention provide techniques for forming substantially coplanar solder bumps on a substrate so as to beneficially increase the tolerance of the chip to substrate warpage compared to conventional solder bump formation approaches. Techniques of the present invention accomplish this in a manner which advantageously eliminates a coining of the solder bumps as a separate step. Furthermore, techniques of the invention achieve transfer of the solder bumps to the substrate without directly applying additional heat to the substrate, or applying heat that is not sufficient to fully melt the solder plugs once they are formed. Because conventional solder reflow is not required to transfer the solder bumps to the substrate, the invention has an advantage of not exposing the substrate to elevated temperature. Moreover, because injection molded soldering only uses molten solder instead of mixed solder powders and flux, and because a decal is used as a fixture to constrain the solder, the invention has an advantage of providing sufficient solder bump volumes for ever smaller pitches without bridging between solder bumps.
In accordance with one aspect of the invention, a method for forming alloy deposits at selected areas on a receiving substrate is provided. The method includes the steps of: providing an alloy carrier comprising at least a first decal including a first plurality of openings formed therein and a second decal including a second plurality of openings formed therein, the first and second decals being arranged in abutting contact with one another such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy in the first and second plurality of openings to thereby form at least first and second plugs, the first plug having a first surface and a second surface, the second surface being substantially parallel to the first surface, the second plug having a third surface and a fourth surface, the fourth surface being substantially parallel to the third surface; removing at least one of the first and second decals to at least partially expose at least the first and second plugs; aligning the alloy carrier with the receiving substrate so that the at least the first and second plugs substantially correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas, wherein contact is made between the first surface and the first selected area and between the third surface and the second selected area, wherein the transferring comprises at least one of applying a compression force, applying heat, and applying mechanical vibration to the second and fourth surfaces of the first and second plugs, respectively, such that the second and fourth surfaces are formed substantially within a same plane.
In accordance with another aspect of the invention, an integrated circuit is provided comprising alloy deposits formed at selected areas on a substrate of the integrated circuit. The alloy deposits are foamed on the substrate by a method including the steps of: providing an alloy carrier comprising at least a first decal including a first plurality of openings formed therein and a second decal including a second plurality of openings formed therein, the first and second decals being arranged in abutting contact with one another such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy in the first and second plurality of openings to thereby form at least first and second plugs, the first plug having a first surface and a second surface, the second surface being substantially parallel to the first surface, the second plug having a third surface and a fourth surface, the fourth surface being substantially parallel to the third surface; removing at least one of the first and second decals to at least partially expose at least the first and second plugs; aligning the alloy carrier with the receiving substrate so that the at least the first and second plugs substantially correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas, wherein contact is made between the first surface and the first selected area and between the third surface and the second selected area, wherein the transferring comprises at least one of applying a compression force, applying heat, and applying mechanical vibration to the second and fourth surfaces of the first and second plugs, respectively, such that the second and fourth surfaces are formed substantially within a same plane.
These and other features, objects and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A through 1H are cross-sectional views depicting an illustrative process for forming solder bumps on a substrate using a technique of stencil printing followed by reflow and coining.
FIGS. 2A through 2G are cross-sectional views depicting an exemplary process for forming solder bumps on a substrate, in accordance with an embodiment of the present invention.
FIG. 3 is a cross-sectional view depicting an exemplary packaged integrated circuit comprising coined solder bumps, in accordance with an embodiment of the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described herein in the context of illustrative embodiments of a flip chip bonding methodology and an IC device employing same. It is to be appreciated, however, that the techniques of the present invention are not limited to the specific methods and device shown and described herein. Rather, embodiments of the invention are directed broadly to improved techniques for interconnecting an IC die to a substrate. For this reason, numerous modifications can be made to these embodiments and the results will still be within the scope of the invention. No limitations with respect to the specific embodiments described herein are intended or should be inferred.
Although combined in a novel manner, several of the processing steps described herein may be performed in conventional semiconductor processing, and, as result, will be familiar to those skilled in that art. Moreover, details of certain individual processing steps used to fabricate semiconductor devices described herein may be found in a number of publications, for example, S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1, Lattice Press, 1986; S. Wolf, Silicon Processing for the VLSI Era, Vol. 4: Deep-Submicron Process Technology, Lattice Press, 2003; and S. M. Sze, VLSI Technology, Second Edition, McGraw-Hill, 1988, which are incorporated herein by reference. It is also emphasized that the descriptions provided herein are not intended to encompass all of the processing steps which may be required to successfully form a functional device. Rather, certain processing steps which are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description. However one skilled in the art will readily recognize those processing steps omitted from this generalized description.
It should also be understood that the various layers and/or regions shown in the accompanying figures may not be drawn to scale, and that one or more semiconductor layers and/or regions of a type commonly used in such ICs may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layers and/or regions not explicitly shown are omitted from the actual IC device.
As previously stated, for chips having higher pin counts, smaller line-pitch and larger size, the size of solder bumps on the chip is decreased, thereby resulting in a reduced stand-off height. Stand-off height is an important factor affecting interconnect reliability. As stand-off height decreases, the tolerance for substrate warpage decreases accordingly, which can result in lower yield. Consequently, reliability of standard flip chip technology is often unacceptable when used in electronic packages employing high density interconnect substrates.
One interconnection technique for improving the tolerance of an IC packaging methodology to substrate and/or IC die warpage is to form additional solder bumps on the substrate. Substrate solder bumping helps increase assembly yield and the allowable stand-off height between the IC die and the substrate, and is therefore beneficial. Solder bumps on the substrate compensate for height variation in the solder bumps on the die. One approach to minimize the effects of substrate warpage on device reliability is to “coin” the solder bumps. Coining solder bumps, as will be described in further detail below, refers to a process of exerting sufficient downward pressure on a plurality of solder bumps for a prescribed amount of time to thereby cause the upper surfaces of the solder bumps to flatten, so as to be substantially within a same plane (i.e., coplanar). (See, e.g., J. W. Nah et al., IEEE Transactions on Electronics Packaging Manufacturing, Vol. 26, No. 2, April 2003, p. 166, the disclosure of which is incorporated herein by reference.) Coining substrate solder bumps enhances coplanarity of solder bump surfaces regardless of the amount of substrate warpage. Coplanarity ensures good flip chip interconnects over relatively large substrate areas. Coined substrate solder bumps also provide enlarged placement targets for the alignment of substrate and die.
One known method of forming solder bumps on substrate pads is to apply solder paste by screening, and then to reflow the screened solder paste to make substantially ball-shaped solder bumps. A low cost method of screening solder paste, which will be described in further detail herein below, is stencil printing. Stencil printing does not require additional lithography or vacuum process steps.
FIGS. 1A through 1H are cross-sectional views depicting an illustrative process 100 for forming coined solder bumps, or alternative alloy deposits, at selected areas on a receiving substrate using stencil printing followed by solder reflow and coining. With reference to FIG. 1A, a substrate 101 is shown including a plurality of pads 160 formed on at least a portion of an upper surface of the substrate. Substrate 101 may comprise, for example, an organic material, including, but not limited to flame retardant type 4 (FR-4), bismaleimide triazine (BT) resin, etc., or a semiconductor material, such as, for example, silicon, germanium, gallium arsenide, etc. A stencil mask 110 is positioned over the substrate 101. The stencil mask 110 includes a plurality of openings 165 therein, each of the openings being aligned with a corresponding one of the underlying pads 160. Optionally, a solder mask 170, or alternative spacer, may be employed (as shown) to prevent bridging of solder between adjacent pads 160. Solder mask 170, when used, is preferably formed on at least a portion of the upper surface of substrate 101 and under the stencil mask 110. Like stencil mask 110, solder mask 170 includes a plurality of openings 165 therein, each of the openings being aligned with a corresponding one of the pads 160.
As depicted in FIG. 1B, stencil printing is preferably performed by moving a squeegee 130, or an alternative applicator, over stencil mask 110 to force a solder paste 120 into the holes in the stencil mask 110. The stencil mask 110 is then removed, exposing at least a portion of sidewalls and an upper surface of the resulting solder paste structure 120, as shown in FIG. 1C. Since the solder paste is conductive, the solder paste structures 120 provide electrical connection to the corresponding pads 160 on the substrate 101.
With reference now to FIG. 1D, the substrate 101 and solder paste structures formed thereon are elevated to a high temperature, typically about 30 to 40 degrees Celsius (° C.) over the melting temperature of the components in the solder paste (e.g., greater than about 210° C. for eutectic tin-lead (SnPb) solder (melting point 183° C.) and greater than about 250° C. for lead-free solder (melting point around 220° C.)). This solder reflow step can be carried out using, for example, forced air convection, infrared furnace, vapor phase, etc. By exposing the substrate to the elevated temperature, the solder paste will melt to form molten solder balls 121 against the upper surface of the solder mask 170. During this process, residual flux 122 may form around part of the molten solder balls 121. Heat is then removed and the molten solder balls 121 are subsequently cooled to form solid solder bumps 123, as shown in FIG. 1E. In FIG. 1F, the residual flux 122 is preferably removed.
Subsequent to forming the solder bumps 123 on the substrate 101, the solder bumps are preferably coined by applying a thermal compression force 150 of sufficient pressure for a sufficient time onto a coining bar 140, as shown in FIG. 1G. U.S. Pat. No. 5,853,517 to Petefish et al. discloses one known method for coining solder balls on an electrical circuit package, the disclosure of which is incorporated by reference herein. The thermal compression force 150 applied through the coining bar 140 results in the formation of coined solder bumps 124. Lastly, the coining bar 140 is removed, as depicted in FIG. 1H. Because of substrate warpage and/or other anomalies of the solder bump process, the solder bumps may have different heights (when measured in a vertical direction above the substrate) relative to one another, which can create yield problems during interconnection of the substrate 101 with an IC die (not shown) during the flip chip bonding process. As previously stated, coining is used to flatten an upper surface of the solder bumps and ensures that the plurality of solder coins are substantially planar.
A stencil mask printing process of the type exemplified in FIGS. 1A through 1H can be used for fine pitch C4 substrate solder bumping of high density interconnect substrates for electronic packages. However, this technique is limited in its applicability for future platforms, particularly with requirements of decreasing C4 pitch and solder bump sizes. For example, attempts at printing at very fine pitches (e.g., less than about 120 μm) often produce unacceptable yields, with issues including mask lift-off, missing bumps, and low volume solder bumps. Another disadvantage of the stencil mask printing process is the requirement of an additional solder coining process after bump formation to form a flat surface.
FIGS. 2A through 2G are cross-sectional views depicting an exemplary process 200 for forming solder bumps on a substrate, in accordance with an embodiment of the present invention. Techniques of the invention provide, for example, a method and apparatus for making substantially flat-topped solder features on a substrate using a simplified injection molded soldering (IMS) process. Upper surfaces of the respective solder features are substantially coplanar relative to one another. Moreover, the illustrative IMS process advantageously eliminates the need for two-step processes of solder reflow step followed by a solder coining step, as required by the stencil printing process depicted in FIGS. 1A through 1H.
Referring now to FIG. 2A, a first step in an embodiment of the invention is illustrated. In this step, a decal solder alloy carrier 205 is formed including at least a first decal 210 and a second decal 220. As is known by those skilled in the art, the term “decal” generally refers to a structure (e.g., a mold) for forming and holding solder, which is initially in molten form when injected into the decal. First and second decals are preferably held together using mechanical means (e.g., clamps, elastic, etc.). Although only two decals are depicted in the figure, it is to be understood that the present invention is not limited to any particular number of decals used to form the solder alloy carrier 205. Decal solder alloy carrier 205 is preferably formed of a material that is non-wettable by solder alloys typically used in the semiconductor technology field, i.e., a material that has no metallurgical affinity with, and thus does not metallurgically bond to the solder alloy. In one illustrative embodiment of the invention, decal solder alloy carrier 205 is formed of a material having a relatively low thermal expansion coefficient, particularly a thermal expansion coefficient sufficiently lower than that of a target substrate onto which the solder alloy is to be transferred. First decal 210 need not be formed of the same material as that of second decal 220, although the first and second decals may be formed of the same material. Suitable materials for forming the decal solder alloy carrier 205 include, but are not limited to, polymer, silicon, germanium, gallium arsenide, glass, quartz, and like materials and/or compositions.
First decal 210 includes a first plurality of openings 211 therein adapted for carrying solder alloy. Likewise, second decal 220 includes a second plurality of openings 221 therein adapted for carrying solder alloy. The openings 211, 221 may be formed, for example, using a conventional laser drilling process and/or a photolithographic process, although alternative means for forming the openings are similarly contemplated (e.g., wet or dry etch, bulk micromachining, surface micromachining). The first and second decals 210, 220 are preferably arranged in abutting contact with one another such that each of the first plurality of openings 211 is in alignment with a corresponding one of the second plurality of openings 221, as shown. Each opening 211 in the first decal 210 and corresponding opening 221 in the second decal 220 forms a composite opening 222 in the decal solder alloy carrier 205. Openings 211 and 221 do not have to be the same diameter or shape. In alternative embodiments in which more than two decals are employed, there will be openings in each decal that are aligned such that there are composite openings that are continuous through all the decals.
FIG. 2B depicts the first and second decals 210, 220 after substantially filling composite openings 222 with molten solder 250. The molten solder 250 may be injected into composite openings according to an IMS process, for example, as described in U.S. Pat. No. 5,673,846, which is incorporated by reference herein, although other means may be employed for filling the composite openings. In general terms, IMS provides for injecting molten solder into the openings 222 formed in the decals 210, 220, and then cooling the solder down, or allowing the solder to cool, so that the solder solidifies within the openings, resulting in the formation of solid solder plugs 251, as shown in FIG. 2C. Typically, however, solder plugs 251 will not have as flat or as level an upper surface as desired.
With reference to FIG. 2D, subsequent to cooling, second decal 220 is removed. Removal of the second decal 220 exposes at least a portion of solder plugs 251, such as a lower portion, thereby allowing the solder plugs to extend through material intervening between first decal 210 and the target substrate for electrical connection to corresponding pads on the substrate. For example, the intervening material may be solder mask 170 formed on substrate 101, as shown in FIG. 1A. The solder plugs 251 preferably remain in first decal 210 without falling through since a first width, W1, of a given opening at an upper surface of the first decal is preferably larger than a second width, W2, of the opening at a bottom surface of the first decal. The reach with which the exposed portions of the respective solder plugs 251 may extend through the intervening material for connection to the substrate will, inherently, be a function of the cross-sectional thickness of the second decal 220 (e.g., about 20 μm). Optionally, a layer of flux 270 may be formed on a bottom surface of each of the solder plugs 251 for improving solder wetting on the pads when the solder plugs are placed in contact with corresponding pads on the substrate so as to facilitate adhesion of the solder plugs to the corresponding pads on the substrate. Alternatively, a formic acid vapor may be applied during the solder transfer process, wherein the formic acid vapor is operative to remove oxide layers and improve adhesion of the exposed solder to the pads.
Referring now to FIG. 2E, solder plugs 251 in first decal 210 are substantially aligned to corresponding pads 160 formed on an upper surface of a substrate 101. As previously described in conjunction with FIG. 1A, a solder mask 170, or an alternative spacer, may be optionally formed on the upper surface of the substrate 101 to prevent bridging of solder between adjacent pads 160. Solder mask 170, when used, includes a plurality of openings therein, each of the openings being aligned with a corresponding one of the pads 160. Under prescribed heat 262 and compressive force 261 applied to a bar 240, or alternative structure suitable for uniformly transferring the compressive force and/or heat to solder plugs 251, the solder plugs are bonded to the corresponding pads 160. That is, solder plugs 251 are under sufficient pressure and heat for a sufficient time to bond to pads 160.
In this embodiment, the heat is preferably not sufficient to reflow the solder plugs; that is, the solder is not fully melted to form molten solder. In accordance with an alternative embodiment, sufficient heat is applied to reflow the solder plugs 251. In still another alternative embodiment, mechanical vibration may be applied to solder plugs 251 to assist in bonding to corresponding pads 160. In this instance, vibrational wetting support can be used to supplement standard oxide removal methods. In yet another alternative embodiment, shown in FIG. 2F, bonding of the solder plugs 251 to corresponding pads 160 is performed under a compressive force 261, without the addition of heat to the bar 240. However, this step preferably takes place in a heated environment, wherein the temperature of the environment may be slightly above the melting point of the solder material forming the solder plugs 251 (e.g., greater than about 180° C. for eutectic SnPb solder and about 220° C. for lead-free solder). Although the solder material forming the solder plugs 251 does melt during transfer, the solder material is constrained by the surrounding geometry/structure, including the top compressive force. These constraining forces are applied until the solder material has solidified, and thus the solder plugs retain this shape. Although FIG. 2E shows heat 262 and compressive force 261 applied to the bar 240, and FIG. 2F shows only compressive force 261 applied to the bar 240, the invention is not so limited. Heat 262 and compressive force 261 can, alternatively or in addition, be applied to the substrate 101. Moreover, the compressive force 261, although shown as being applied to an upper surface of the solder plugs 251, can, alternatively or in addition, be applied to a backside of the substrate 101. Mechanical vibration can be applied to the bar 240, the substrate 101, both the substrate and bar, or neither.
Another function of bar 240 is to form substantially flat and level upper surfaces of solder plugs 251, such that the upper surfaces of the solder plugs reside in substantially the same plane, i.e., coplanar. Application of compressive force 261 to the bar 240 and/or the substrate 101 causes pressure between the bar 240 and solder plugs 251. The pressure between bar 240 and solder plugs 251 causes the upper surfaces of the respective solder plugs 251 to flatten and thereby become substantially coplanar with one another. Likewise, heat 262, when applied, assists in reshaping (reforming) the upper surfaces of solder plugs 251 so as to be substantially flat and coplanar relative to one another. That is, the solder plugs 251 are preferably placed under sufficient pressure and/or heat for a sufficient time so as to produce substantially flat-topped, coplanar solder plugs. During this step, the first decal 210 can prevent bridging of solder between adjacent plugs.
As shown in FIG. 2G, bar 240 and first decal 210 are preferably removed. Remaining are solder plugs 251 bonded on corresponding pads 160 formed on the upper surface of substrate 101, and, optionally, solder mask 170 formed on the upper surface of the substrate. As depicted in the figure, compressive force 261 and/or heat 262 applied to the bar 240 (FIG. 2E) preferably causes the solder alloy material forming the lower portion of solder plugs 251 to substantially fill openings in the solder mask 170 aligned with corresponding pads 160. Accordingly, the lower portions of solder plugs 251 will take on the shape of the openings in solder mask 170.
FIG. 3 is a partial cross-sectional view depicting an exemplary packaged integrated circuit 300 according to an embodiment of the present invention. The packaged integrated circuit 300 comprises a leadframe 310, or an alternative receiving substrate, a plurality of pads 340 formed on an upper surface of the leadframe, an integrated circuit die 320, and a molded encapsulation 360. The die 320 is attached to the leadframe 310 by methods of this invention described herein. For example, bonding pads 330 formed on a bottom surface of die 320 may be electrically connected to corresponding pads 340 formed on the upper surface of leadframe 310 via solder plugs 350. Encapsulation 360 preferably surrounds the die/leadframe combination, as in a conventional manner. Although FIG. 3 shows only one type of integrated circuit package, the invention is not so limited. Rather, the invention may comprise an integrated circuit die enclosed in essentially any package type.
At least a portion of the techniques of the present invention may be implemented in one or more integrated circuits. In forming integrated circuits, die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Individual die are cut or diced from the wafer, then packaged as integrated circuits. In packaging the dies, individual die are attached to a receiving substrate according to methods of the invention. One skilled in the art would know how to dice wafers to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
An integrated circuit formed in accordance with interconnection techniques of the present invention can be employed in essentially any application and/or electronic system. Suitable systems for implementing the invention may include, but are not limited to, personal computers, communication networks, portable communications devices (e.g., cell phones), etc. Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.

Claims (9)

1. An integrated circuit including a substrate and a plurality of alloy deposits formed at selected areas on the substrate, the plurality of alloy deposits being formed by a method comprising the steps of:
providing an alloy carrier comprising at least a first decal including a first plurality of openings formed therein and a second decal including a second plurality of openings formed therein, the first and second decals being arranged in abutting contact with one another such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings;
filling the first and second plurality of openings with molten alloy;
cooling the molten alloy in the first and second plurality of openings to thereby form at least first and second plugs, the first plug having a first surface and a second surface, the second surface being substantially parallel to the first surface, the second plug having a third surface and a fourth surface, the fourth surface being substantially parallel to the third surface;
removing at least one of the first and second decals to at least partially expose at least the first and second plugs;
aligning the alloy carrier with the receiving substrate so that the at least the first and second plugs substantially correspond to the selected areas on the receiving substrate; and
transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas, wherein contact is made between the first surface and the first selected area and between the third surface and the second selected area, wherein the transferring comprises at least one of applying a compression force, applying heat, and applying mechanical vibration to the second and fourth surfaces of the first and second plugs, respectively, such that the second and fourth surfaces are formed substantially within a same plane;
wherein following the transferring step, the second and fourth surfaces of the first and second plugs, respectively, are substantially flat.
2. The integrated circuit of claim 1, wherein the at least first and second plugs continuously remains a solid.
3. The integrated circuit of claim 1, wherein the plurality of decals comprises two decals.
4. The integrated circuit of claim 1, wherein the step of transferring comprises applying the compressive force to at least one of the at least first and second plugs and the substrate.
5. The integrated circuit of claim 1, wherein the step of transferring comprises applying the heat to at least one of the at least first and second plugs and the substrate.
6. The integrated circuit of claim 1, further comprising the step of inserting a spacer between one of the plurality of decals and the substrate, wherein the spacer is formed to avoid bridging of the alloy deposits.
7. The integrated circuit of claim 1, further comprising the step of applying a layer of flux on at least one of the at least first and second plugs and at least one of the selected areas on the receiving substrate, wherein the flux is operative to facilitate adhesion of the at least first and second plugs to corresponding selected areas on the substrate.
8. The integrated circuit of claim 1, further comprising the step of applying a formic acid vapor to at least one of the at least first and second plugs and to at least one of the selected areas on the receiving substrate, wherein the formic acid vapor is operative to improve adhesion of the at least first and second plugs to corresponding selected areas on the substrate.
9. The integrated circuit of claim 1, wherein the substrate is an organic substrate, and wherein the molten alloy comprises molten solder.
US12/181,852 2008-07-29 2008-07-29 Method and apparatus for forming planar alloy deposits on a substrate Expired - Fee Related US7867842B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/181,852 US7867842B2 (en) 2008-07-29 2008-07-29 Method and apparatus for forming planar alloy deposits on a substrate
US12/627,249 US7906420B2 (en) 2008-07-29 2009-11-30 Method and apparatus for forming planar alloy deposits on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/181,852 US7867842B2 (en) 2008-07-29 2008-07-29 Method and apparatus for forming planar alloy deposits on a substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/627,249 Division US7906420B2 (en) 2008-07-29 2009-11-30 Method and apparatus for forming planar alloy deposits on a substrate

Publications (2)

Publication Number Publication Date
US20100028612A1 US20100028612A1 (en) 2010-02-04
US7867842B2 true US7867842B2 (en) 2011-01-11

Family

ID=41608657

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/181,852 Expired - Fee Related US7867842B2 (en) 2008-07-29 2008-07-29 Method and apparatus for forming planar alloy deposits on a substrate
US12/627,249 Expired - Fee Related US7906420B2 (en) 2008-07-29 2009-11-30 Method and apparatus for forming planar alloy deposits on a substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/627,249 Expired - Fee Related US7906420B2 (en) 2008-07-29 2009-11-30 Method and apparatus for forming planar alloy deposits on a substrate

Country Status (1)

Country Link
US (2) US7867842B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150216051A1 (en) * 2011-12-21 2015-07-30 Lawrence Livermore National Security, Llc Method of fabricating electrical feedthroughs using extruded metal vias
US11541472B2 (en) 2020-01-29 2023-01-03 International Business Machines Corporation Ultrasonic-assisted solder transfer

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7931187B2 (en) * 2008-11-12 2011-04-26 International Business Machines Corporation Injection molded solder method for forming solder bumps on substrates
US9216145B2 (en) 2009-10-27 2015-12-22 The Procter & Gamble Company Semi-permanent cosmetic concealer
US10034829B2 (en) 2010-10-27 2018-07-31 Noxell Corporation Semi-permanent mascara compositions
US9237992B2 (en) 2009-10-27 2016-01-19 The Procter & Gamble Company Two-step mascara product
US8138020B2 (en) * 2010-03-25 2012-03-20 International Business Machines Corporation Wafer level integrated interconnect decal and manufacturing method thereof
US9004791B2 (en) 2010-04-30 2015-04-14 The Procter & Gamble Company Package for multiple personal care compositions
US9173824B2 (en) 2011-05-17 2015-11-03 The Procter & Gamble Company Mascara and applicator
US20120309187A1 (en) * 2011-05-30 2012-12-06 International Business Machines Corporation Conformal Coining of Solder Joints in Electronic Packages
US9140681B2 (en) 2012-05-15 2015-09-22 The Procter & Gamble Company Method for quantitatively determining eyelash clumping
KR101940237B1 (en) * 2012-06-14 2019-01-18 한국전자통신연구원 Method for Manufacturing Solder on Pad on Fine Pitch PCB Substrate and Flip Chip Bonding Method of Semiconductor Using The Same
US9082754B2 (en) * 2012-08-03 2015-07-14 International Business Machines Corporation Metal cored solder decal structure and process
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9159690B2 (en) * 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US11270966B2 (en) * 2019-11-18 2022-03-08 International Business Machines Corporation Combination polyimide decal with a rigid mold
CN113319454B (en) * 2021-04-29 2022-08-23 中国电子科技集团公司第二十九研究所 Solder presetting method for welding end of surface-mounted self-contained solid solder connector

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412642A (en) * 1982-03-15 1983-11-01 Western Electric Co., Inc. Cast solder leads for leadless semiconductor circuits
US5244143A (en) * 1992-04-16 1993-09-14 International Business Machines Corporation Apparatus and method for injection molding solder and applications thereof
US5673846A (en) * 1995-08-24 1997-10-07 International Business Machines Corporation Solder anchor decal and method
US5853517A (en) 1996-11-08 1998-12-29 W. L. Gore & Associates, Inc. Method for coining solder balls on an electrical circuit package
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
US6276596B1 (en) * 2000-08-28 2001-08-21 International Business Machines Corporation Low temperature solder column attach by injection molded solder and structure formed
US20020110328A1 (en) * 2001-02-14 2002-08-15 Bischel William K. Multi-channel laser pump source for optical amplifiers
US7332424B2 (en) 2004-08-16 2008-02-19 International Business Machines Corporation Fluxless solder transfer and reflow process

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412642A (en) * 1982-03-15 1983-11-01 Western Electric Co., Inc. Cast solder leads for leadless semiconductor circuits
US5244143A (en) * 1992-04-16 1993-09-14 International Business Machines Corporation Apparatus and method for injection molding solder and applications thereof
US5673846A (en) * 1995-08-24 1997-10-07 International Business Machines Corporation Solder anchor decal and method
US5853517A (en) 1996-11-08 1998-12-29 W. L. Gore & Associates, Inc. Method for coining solder balls on an electrical circuit package
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
US6276596B1 (en) * 2000-08-28 2001-08-21 International Business Machines Corporation Low temperature solder column attach by injection molded solder and structure formed
US20020110328A1 (en) * 2001-02-14 2002-08-15 Bischel William K. Multi-channel laser pump source for optical amplifiers
US7332424B2 (en) 2004-08-16 2008-02-19 International Business Machines Corporation Fluxless solder transfer and reflow process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150216051A1 (en) * 2011-12-21 2015-07-30 Lawrence Livermore National Security, Llc Method of fabricating electrical feedthroughs using extruded metal vias
US11541472B2 (en) 2020-01-29 2023-01-03 International Business Machines Corporation Ultrasonic-assisted solder transfer

Also Published As

Publication number Publication date
US20100028612A1 (en) 2010-02-04
US7906420B2 (en) 2011-03-15
US20100072263A1 (en) 2010-03-25

Similar Documents

Publication Publication Date Title
US7867842B2 (en) Method and apparatus for forming planar alloy deposits on a substrate
US8541299B2 (en) Electrical interconnect forming method
US20100025863A1 (en) Integrated Circuit Interconnect Method and Apparatus
TWI567864B (en) Semiconductor device and method of forming high routing density interconnect sites on substrate
US7736950B2 (en) Flip chip interconnection
US8133761B2 (en) Packaged system of semiconductor chips having a semiconductor interposer
US9263426B2 (en) PoP structure with electrically insulating material between packages
US8117982B2 (en) Method and apparatus for depositing coplanar microelectronic interconnectors using a compliant mold
US8616433B2 (en) Forming low stress joints using thermal compress bonding
US6189772B1 (en) Method of forming a solder ball
US9679875B2 (en) Reduced volume interconnect for three-dimensional chip stack
US11152295B2 (en) Semiconductor package structure and method for manufacturing the same
US7638867B2 (en) Microelectronic package having solder-filled through-vias
KR101827608B1 (en) Variable interconnection joints in package structures
Chan et al. Study of the self-alignment of no-flow underfill for micro-BGA assembly
US20070166878A1 (en) Package structure and method for fabricating the same
KR101408731B1 (en) Template for forming a solder bump and method of formign a solder bump
Ding et al. Mitigation of warpage for large 2.5 D Through Silicon Interposer (TSI) package assembly
JP2022105279A (en) Method and device (assembly of chip and substrate)
JP2005259925A (en) Mounting method
Kikuchi et al. Shape Control of Electronic Devices by Soldering

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GRUBER, PETER ALFRED;LAURO, PAUL ALFRED;NAH, JAE-WOONG;SIGNING DATES FROM 20080722 TO 20080723;REEL/FRAME:021310/0119

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GRUBER, PETER ALFRED;LAURO, PAUL ALFRED;NAH, JAE-WOONG;SIGNING DATES FROM 20080722 TO 20080723;REEL/FRAME:021310/0119

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001

Effective date: 20181127

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20190111

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001

Effective date: 20201117

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001

Effective date: 20201117