KR970706608A - 고정값 저장 셀 장치 및 그것의 제조 방법(fixed value storage cell arrangement and method of producing the same) - Google Patents
고정값 저장 셀 장치 및 그것의 제조 방법(fixed value storage cell arrangement and method of producing the same)Info
- Publication number
- KR970706608A KR970706608A KR1019970701934A KR19970701934A KR970706608A KR 970706608 A KR970706608 A KR 970706608A KR 1019970701934 A KR1019970701934 A KR 1019970701934A KR 19970701934 A KR19970701934 A KR 19970701934A KR 970706608 A KR970706608 A KR 970706608A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- mos transistor
- doped
- substrate
- insulating layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4434725A DE4434725C1 (de) | 1994-09-28 | 1994-09-28 | Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung |
DEP4434725.1 | 1994-09-28 | ||
PCT/DE1995/001262 WO1996010266A1 (de) | 1994-09-28 | 1995-09-14 | Festwert-speicherzellenanordnung und verfahren zu deren herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970706608A true KR970706608A (ko) | 1997-11-03 |
Family
ID=6529456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970701934A KR970706608A (ko) | 1994-09-28 | 1995-09-14 | 고정값 저장 셀 장치 및 그것의 제조 방법(fixed value storage cell arrangement and method of producing the same) |
Country Status (7)
Country | Link |
---|---|
US (1) | US5973373A (de) |
EP (1) | EP0784866B1 (de) |
JP (1) | JP3781125B2 (de) |
KR (1) | KR970706608A (de) |
CN (1) | CN1159865A (de) |
DE (2) | DE4434725C1 (de) |
WO (1) | WO1996010266A1 (de) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19549486C2 (de) * | 1995-11-28 | 2001-07-05 | Siemens Ag | Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung |
DE19544327C2 (de) * | 1995-11-28 | 2001-03-29 | Siemens Ag | Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung |
DE19604260C2 (de) | 1996-02-06 | 1998-04-30 | Siemens Ag | Festwert-Speicherzellenvorrichtung und ein Verfahren zu deren Herstellung |
DE19617646C2 (de) * | 1996-05-02 | 1998-07-09 | Siemens Ag | Speicherzellenanordnung und ein Verfahren zu deren Herstellung |
DE19653107C2 (de) * | 1996-12-19 | 1998-10-08 | Siemens Ag | Verfahren zur Herstellung einer Speicherzellenanordnung |
JP3976374B2 (ja) * | 1997-07-11 | 2007-09-19 | 三菱電機株式会社 | トレンチmosゲート構造を有する半導体装置及びその製造方法 |
IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
DE19732871C2 (de) * | 1997-07-30 | 1999-05-27 | Siemens Ag | Festwert-Speicherzellenanordnung, Ätzmaske für deren Programmierung und Verfahren zu deren Herstellung |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
TW399219B (en) * | 1997-09-26 | 2000-07-21 | Siemens Ag | Pointer-circuit with small space requirement, higher speed and smaller power loss |
US6606122B1 (en) * | 1997-09-29 | 2003-08-12 | California Institute Of Technology | Single chip camera active pixel sensor |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6348711B1 (en) | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
DE19929211B4 (de) * | 1999-06-25 | 2005-10-06 | Infineon Technologies Ag | Verfahren zur Herstellung eines MOS-Transistors sowie einer DRAM-Zellenanordung |
US6429063B1 (en) | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6686604B2 (en) * | 2001-09-21 | 2004-02-03 | Agere Systems Inc. | Multiple operating voltage vertical replacement-gate (VRG) transistor |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US7098107B2 (en) | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
US6583007B1 (en) | 2001-12-20 | 2003-06-24 | Saifun Semiconductors Ltd. | Reducing secondary injection effects |
US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US6826107B2 (en) | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
EP1746645A3 (de) | 2005-07-18 | 2009-01-21 | Saifun Semiconductors Ltd. | Speicherzellenanordnung mit sub-minimalem Wortleitungsabstand und Verfahren zu deren Herstellung |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US8664050B2 (en) * | 2012-03-20 | 2014-03-04 | International Business Machines Corporation | Structure and method to improve ETSOI MOSFETS with back gate |
US8883624B1 (en) | 2013-09-27 | 2014-11-11 | Cypress Semiconductor Corporation | Integration of a memory transistor into high-K, metal gate CMOS process flow |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136378A (ja) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPS6135554A (ja) * | 1984-07-28 | 1986-02-20 | Nippon Telegr & Teleph Corp <Ntt> | 読出し専用メモリ−およびその製造方法 |
US4774556A (en) * | 1985-07-25 | 1988-09-27 | Nippondenso Co., Ltd. | Non-volatile semiconductor memory device |
JPH0715953B2 (ja) * | 1985-08-09 | 1995-02-22 | 株式会社リコー | 書換え可能なメモリ装置とその製造方法 |
JPH0828431B2 (ja) * | 1986-04-22 | 1996-03-21 | 日本電気株式会社 | 半導体記憶装置 |
JPS63102372A (ja) * | 1986-10-20 | 1988-05-07 | Fujitsu Ltd | Eepromの製造方法 |
EP0376568A3 (de) * | 1988-12-27 | 1991-01-09 | Texas Instruments Incorporated | Halbleiter-Nur-Lese-Speicherzelle und Herstellungsverfahren |
US4954854A (en) * | 1989-05-22 | 1990-09-04 | International Business Machines Corporation | Cross-point lightly-doped drain-source trench transistor and fabrication process therefor |
JPH03190165A (ja) * | 1989-12-20 | 1991-08-20 | Sony Corp | 読み出し専用メモリ装置及びその製造方法 |
JPH04226071A (ja) * | 1990-05-16 | 1992-08-14 | Ricoh Co Ltd | 半導体メモリ装置 |
JPH0462966A (ja) * | 1990-07-02 | 1992-02-27 | Fujitsu Ltd | Mosfetマスクrom |
US5200802A (en) * | 1991-05-24 | 1993-04-06 | National Semiconductor Corporation | Semiconductor ROM cell programmed using source mask |
JPH04354159A (ja) * | 1991-05-31 | 1992-12-08 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5641694A (en) * | 1994-12-22 | 1997-06-24 | International Business Machines Corporation | Method of fabricating vertical epitaxial SOI transistor |
US5597753A (en) * | 1994-12-27 | 1997-01-28 | United Microelectronics Corporation | CVD oxide coding method for ultra-high density mask read-only-memory (ROM) |
US5576573A (en) * | 1995-05-31 | 1996-11-19 | United Microelectronics Corporation | Stacked CVD oxide architecture multi-state memory cell for mask read-only memories |
-
1994
- 1994-09-28 DE DE4434725A patent/DE4434725C1/de not_active Expired - Fee Related
-
1995
- 1995-09-14 US US08/817,630 patent/US5973373A/en not_active Expired - Lifetime
- 1995-09-14 CN CN95195345A patent/CN1159865A/zh active Pending
- 1995-09-14 JP JP51125896A patent/JP3781125B2/ja not_active Expired - Fee Related
- 1995-09-14 WO PCT/DE1995/001262 patent/WO1996010266A1/de active IP Right Grant
- 1995-09-14 DE DE59501936T patent/DE59501936D1/de not_active Expired - Fee Related
- 1995-09-14 KR KR1019970701934A patent/KR970706608A/ko active IP Right Grant
- 1995-09-14 EP EP95931136A patent/EP0784866B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE59501936D1 (de) | 1998-05-20 |
EP0784866A1 (de) | 1997-07-23 |
JPH10506237A (ja) | 1998-06-16 |
WO1996010266A1 (de) | 1996-04-04 |
US5973373A (en) | 1999-10-26 |
EP0784866B1 (de) | 1998-04-15 |
CN1159865A (zh) | 1997-09-17 |
DE4434725C1 (de) | 1996-05-30 |
JP3781125B2 (ja) | 2006-05-31 |
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Legal Events
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A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
NORF | Unpaid initial registration fee |