KR970072396A - Mos트랜지스터의 제조방법 및 cmos트랜지스터의 제조방법 - Google Patents

Mos트랜지스터의 제조방법 및 cmos트랜지스터의 제조방법 Download PDF

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KR970072396A
KR970072396A KR1019970015804A KR19970015804A KR970072396A KR 970072396 A KR970072396 A KR 970072396A KR 1019970015804 A KR1019970015804 A KR 1019970015804A KR 19970015804 A KR19970015804 A KR 19970015804A KR 970072396 A KR970072396 A KR 970072396A
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히데아키 구로다
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이데이 노부유키
소니 가부시기가이샤
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Abstract

MSO트랜지스터 및 MOS트랜지스터의 제조방법이 개시(開示)되어 있다. 실리콘기체(基體)상의 게이트산화막상에 실리콘재료로 이루어지는 게이트전극패턴을 형성한다. 게이트전극패턴을 마스크로 하여 실리콘기체에 불순물을 도핑하고, 도핑한 불순물을 활성화시켜 실리콘기체 표층부(表層部)에 확산층을 형성한다. 게이트전극패턴을 덮어 층간절연막을 형성한다. 층간절연막의 상부를 제거하여 게이트전극패턴의 상부를 노출시킨다.노출시킨 게이트전극패턴을 선택적으로 에칭제거한다. 그 후, 게이트패턴이 에칭제거되어 형성된 요부(凹部)에 금속재료를 매입(埋入)하여, CMOS트랜지스터를 얻는다.

Description

MSO트랜지스터의 제조방법 및 CMOS트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4a도∼제4g도는 본 발명에 있어서의 CMOS트랜지스터의 제조방법의 제1실시형태예를 제조공정순으로 설명하기 위한 요부측단면도.

Claims (9)

  1. 실리콘기체(基體)상의 게이트산화막상에 실리콘재료로 이루어지는 게이트전극패턴을 형성하는 제1공정과, 상기 게이트전극패턴을 마스크로 하여 상기 실리콘기체에 불순물을 도핑하고, 도핑한 불순물을 활성화시켜 실리콘기체 표층부(表層部)에 확산층을 형성하는 제2공정과, 상기 게이트전극패턴을 덮어 층간절연막을 형성하는 제3공정과, 상기 층간절연막의 상부를 제거하여 상기 게이트전극패턴의 상부를 노출시키는 제4공정과, 노출시킨 게이트전극패턴을 선택적으로 에칭제거하는 제5공정과, 노출시킨 상기 게이트전극패턴이 에칭제거되어 형성된 요부(凹部)에 금속재료를 매입하는 제6공정과, 를 구비한 것을 특징으로 하는MOS트랜지스터의 제조방법.
  2. 실리콘기체상이 게이트산화막상에, 이 게이트산화막측으로부터 실리콘재료, 실리콘에 대하여 에칭의 선택비가 취해지는 재료, 실리콘재료의 순으로 적층되어 이루어지는 게이트전극패턴을 형성하는 제1공정과, 상기 게이트전극패턴을 마스크로 하여 상기 실리콘기체에 불순물을 도핑하고, 도핑한 불순물을 활성화시켜 상기 실리콘기체 표층부에 확산층을 형성하는 제2공정과, 상기 게이트전극패턴을 덮어 층간절연막을 형성하는 제3공정과, 상기 층간절연막의 상부를 제거하여 상기 게이트전극패턴의 상부를 노출시키는 제4공정과, 노출시킨 게이트전극패턴에 있어서의 상층의 실리콘재료를 선택적으로 에칭제거하는 제5공정과, 상기 게이트전극패턴에 있어서의 하층의 실리콘재료에 불순물을 도핑하고, 도핑한 불순물을 활성화시키는 제6공정과, 상기 게이트전극패턴의 상층의 실리콘재료가 에칭제거되어 형성된 요부에 금속재료를 매입하는 제7공정과를 구비하고, 상기 제5공정과 제7공정과의 사이에, 상기 게이트전극패턴에 있어서의, 실리콘에 대하여 에칭의 선택비가 취해지는 재료를 에칭제거하는 공정을 가진 것을 특징으로 하는 MOS트랜지스터의 제조방법.
  3. 청구항 2에 있어서, 상기 제5공정과 제6공정과의 사이에, 상기 확산층상의 층간절연막을 에칭하여 확산층에 통하는 제2의 요부를 형성하는 공정을 가지고, 상기 제6공정이, 상기 게이트전극패턴에 있어서의 하층의 실리콘재료에 불순물을 도핑하는 동시에, 상기 제2의 요부내를 통하여 확산층에도 불순물을 도핑하는 공정이고, 상기 제7공정이, 상기 게이트전극패턴의 상층의 실리콘재료가 에칭제거되어 형성된 요부에 금속재료를 매입하는 동시에, 상기 확산층에 통하는 제2의 요부내에도 금속재료를 매입하는 공정인 것을 특징으로 하는 MOS트랜지스터의 제조방법.
  4. 청구항 1에 있어서, 상기 제5공정과 제6공정과의 사이에, 실리콘기체 표층부에 불순물을 도핑하는 공정을 가진 것을 특징으로 하는 MOS트랜지스터의 제조방법.
  5. 청구항 2에 있어서, 상기 제5공정과 제7공장과의 사이에, 실리콘기체 표층부에 불순물을 도핑하는 공정을 가진 것을 특징으로 하는 MOS트랜지스터의 제조방법.
  6. 실리콘기체상에 PMOS 영역과 NMOS 영역을 형성하는 동시에, 이들 각 영역의 상기 실리콘기체의 표면에 게이트산화막을 형성하는 제1공정과, 상기 실리콘기체에 있어서의 상기 각 영역의, 상기 게이트산화막상에 각각 실리콘재료로 이루어지는 게이트전극패턴을 형성하는 제2공정과, 상기 NMOS영역을 레지스트층으로 덮고, 이 레지스트층과 상기 게이트전극패턴을 마스크로 하여 상기 실리콘기체의 PMOS영역에 P형의 불순물을 도핑하는 동시에, 상기 PMOS 영역을 레지스트층으로 덮고, 이 레지스트충과 상기 게이트전극패턴을 마스크로하여 상기 실리콘기체의 NMOS 영역에 N형의 불순물을 도핑하고, 또한 도핑한 불순물을 활성화시켜, 상기 실리콘기체에 있어서의 상기 NMOS 및 PMOS 영역의 표층부에 각각 확산층을 형성하는 제3공정과, 상기 NMOS 및 PMOS 영역의 상기 게이트전극패턴을 덮어 층간절연막을 형성하는 제4공정과, 상기 층간절연막의 상부를 제거하여 상기 게이트전극패턴의 상부를 노출시키는 제5공정과, 노출시킨 게이트전극패턴을 선택적으로 에칭제거하는 제6공정과, 노출시킨 상기 게이트전극패턴이 에칭제거되어 형성된 요부에 금속재료를 매입하는 제7공정과, 를 구비한 것을 특징으로 하는 CMOS 트랜지스터의 제조방법.
  7. 실리콘기체상에 PMOS 영역과 NMOS영역을 형성하는 동시에, 이들 각 영역의 상기 실리콘기체의 표면에 게이트산화막을 형성하는 제1공정과, 상기 실리콘기체에 있어서의 상기 각 영역의, 상기 게이트산화막상에 각각, 이 게이트 산화막측으로부터 불순물을 함유하지 않은 실리콘재료, 실리콘에 대하여 에칭의 선택비가 취해지는 재료, 실리콘재료의 순으로 적층되어 이루어지는 게이트전극패턴을 형성하는 제2공정과, 상기 NMOS 영역을 레지스트층으로 덮고, 이 레지스트층과 상기 게이트전극패턴을 마스크로 하여 상기 실리콘기체의 PMOS 영역에 P형의 불순물을 도핑하는 동시에, 상기 PMOS 영역을 레지스트층으로 덮고, 이 레지스트층과 상기 게이트전극패턴을 마스크로 하여 상기 실리콘기체의 NMOS 영역에 N형의 불순물을 도핑하고, 또한 도핑한 불순물을 활성화시켜, 상기 실리콘기체의 있어서의 상기 NMOS 및 PMOS 영역의 표층부에 각각 확산층을 형성하는 제3공정과, 상기 PMOS 및 NMOS 영역의 상기 게이트전극패턴을 덮어 층간절연막을 형성하는 제4공정과, 상기 층간절연막의 상부를 제거하여 상기 게이트전극패턴의 상부를 노출시키는 제5공정과, 노출시킨 게이트전극패턴에 있어서의 상층의 실리콘재료를 선택적으로 에칭제거하는 제6공정과, 상기 PMOS 영역의 게이트전극패턴에 있어서의 하층의 실리콘재료에 P형의 불순물을 도핑하는 동시에, 상기 NMOS 영역의 게이트전극패턴에 있어서의 하층의 실리콘재료에 N형의 불순물을 도핑하고, 또한 도핑한 불순물을 활성화시키는 제7공정과, 상기 게이트전극패턴의 상층의 실리콘재료가 에칭제거되어 형성된 요부에 금속재료를 매입하는 제8공정과를 구비하고, 상기 제6공정과 제8공정과의 사이에, 상기 게이트전극패턴에 있어서의, 실리콘에 대하여 에칭의 선택비가 취해지는 재료를 에칭제거하는 공정을 가진 것을 특징으로 하는 CMOS 트랜지스터의 제조방법.
  8. 청구항 6에 있어서, 상기 제6공정과 제7공정과의 사이에, 실리콘기체의 PMOS 영역의 표층부에 P형의 불순물의 도핑하는 동시에, 실리콘기체의 NMOS 영역의 표층부에 N형의 불순물을 도핑하는 공정을 가진 것을 특징으로 하는 CMOS 트랜지스터의 제조방법.
  9. 청구항 7에 있어서, 상기 제6공정과 제8공정과의 사이에, 실리콘기체의 PMOS 영역의 표층부에 P형의 불순물을 도핑하는 동시에, 실리콘기체의 NMOS 영역의 표층부에 N형의 불순물을 도핑하는 공정을 가진 것을 특징으로 하는 CMOS 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970015804A 1996-04-30 1997-04-28 Mos트랜지스터의제조방법및cmos트랜지스터의제조방법 KR100486130B1 (ko)

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