KR970067892A - 고주파 집적회로장치 및 그 제조방법 - Google Patents

고주파 집적회로장치 및 그 제조방법 Download PDF

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Publication number
KR970067892A
KR970067892A KR1019960013253A KR19960013253A KR970067892A KR 970067892 A KR970067892 A KR 970067892A KR 1019960013253 A KR1019960013253 A KR 1019960013253A KR 19960013253 A KR19960013253 A KR 19960013253A KR 970067892 A KR970067892 A KR 970067892A
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South Korea
Prior art keywords
laminate
substrates
substrate
concave portion
layer
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KR1019960013253A
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English (en)
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KR100367936B1 (ko
Inventor
노리유키 요시카와
구니히코 가나자와
사토시 마키오카
가즈키 다테오카
Original Assignee
스기야마 가즈히코
마쯔시다 덴시 고교 가부시키가이샤
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Priority claimed from JP06236896A external-priority patent/JP3235452B2/ja
Application filed by 스기야마 가즈히코, 마쯔시다 덴시 고교 가부시키가이샤 filed Critical 스기야마 가즈히코
Publication of KR970067892A publication Critical patent/KR970067892A/ko
Application granted granted Critical
Publication of KR100367936B1 publication Critical patent/KR100367936B1/ko

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    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

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Abstract

복수의 기판을 적층하여 구성되는 적층체에는 일부의 기판을 부분적으로 제거하여 이루어지는 오목부가 설치되어 있다. 오목부의 저면상에는 FET등의 능동소자를 내장하는 반도체 칩이 탑재되어 있다. 고주파 정합회로, 바이어스 회로 등의 수동소자는 적층체의 최상층, 최하층이나 각 기판 사이의 중간층으로 분산하여 배치되어 있다. 예를 들면, 고주파 정합회로의 일부인 칩 부품은 최상층에 바이어스 회로는 중간층에 배치되어 있다. 주요한 발열체인 능동소자가 내장되는 반도체 칩의 아랫쪽에는 적은 기판밖에 존재하고 있지 않으므로 적층체의 각 기판을 알루미나 등의 범용 재료로 구성하여도 방열성이 충분히 높게 유지된다. 이 특성을 이용하여 높은 실장밀도에서 휴대전화 등의 이동통신용으로 사용 가능한 고주파 집적회로장치를 실현할 수 있다.

Description

고주파 집적회로장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제1실시예에 관한 고주파 집적회로장치의 단면도

Claims (21)

  1. 고주파 신호용의 적어도 하나의 능동소자와 복수의 수동소자를 포함하는 복수의 회로요소를 구비한 고주파 집접회로장치로서 유전재료로 구성되는 복수의 기판을 적층하여 구성되고 상기 복수의 기판 중 맨 위의 기판 상면상의 영역인 최상층과 각 기판 사이의 영역인 적어도 하나의 중간층과 상기 복수의 기판 중 맨 아래의 기판 하면상의 영역인 최하층과 상기 각 기판 측면상의 영역인 측방층으로 상기 회로요소가 분산하여 배치 가능하게 구성된 적층체와 상기 적층체의 각 기판 중 일부의 기판을 부분적으로 제거하여 형성된 오목부와 상기 오목부의 저면 상에 탑재되고 상기 증동소자를 가지는 반도체 칩을 구비하며 상기 능동소자 이외의 회로요소는 상기 적층체의 각 층으로 분산하여 배치되어 있는 것을 특징으로 하는 고주파 집적회로장치.
  2. 제1항에 있어서 상기 오목부는 상기 적층체 중의 맨 아래 기판을 제외하는 모든 기판의 일부를 제거하여 형성되고, 상기 반도체 칩은 상기 맨 아래 기판의 중 상기 오목부 내에서 노출하여 오목부 저면이 되는 영역상에 탑재되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  3. 제1항에 있어서 상기 적층체 중의 맨 아래 기판의 하면 상에서 상기 반도체 칩의 아랫쪽으로 위치하는 영역에 설치된 방열용 부재를 더 구비하고 있는 것을 특징으로 하는 고주파 집적회로 장치.
  4. 제3항에 있어서 상기 적층체의 오목부 아랫쪽 기판의 상기 반도체 칩의 형성영역과 상기 방열부재의 형성영역 사이에 형성된 관통구멍과 상기 관통구멍 내에 채워 넣어진 열전도부재를 더 구비하고 있는 것을 특징으로 하는 고주파 집적회로 장치.
  5. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 적층체 중의 상기 각 기판은 산화알루미늄 및 질화알루미늄 중 적어도 어느 하나에 의하여 구성되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  6. 제1항, 제2항, 또는 제3항에 있어서 상기 적층체 중의 각 기판은 다결정 산화페닐렌(PPO)에 의하여 구성되는어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  7. 제6항에 있어서 상기 적층체 중의 맨 아래 기판의 하면 상에서 상기 반도체 칩의 아랫쪽에 위치하는 영역에 설치된 방열용 부재와 상기 적층체의 오목부 아랫쪽의 기판에서 상기 반도체 칩과 상기 방열부재 사이의 부분을 선택적으로 제거하여 형성된 관통구멍과 상기 관통구멍 내의 채워 넣어진 열전도부재를 더 구비하고 있는 것을 특징으로 하는 고주파 집적회로 장치.
  8. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 적층체 중의 상기 각 기판중 상기 오목부 아랫쪽의 기판은 산화알루미늄 및 질화알루미늄 중 적어도 어느 하나에 의하여 구성되어 있고, 상기 적층체 중의 각 기판 중 상기 오목부 아랫쪽의 기판을 제외하는 모든 기판은 유리 세라믹에 의하여 구성되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  9. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 회로요소에는 필터회로를 가지는 바이어스 회로와 고주파 정합회로가 포함되어 있고, 상기 필터회로와 고주파 정합회로가 상기 적층체의 각 층으로 서로 다르게 구성되는 층으로 분산하여 배치되어 있음과 동시에 해당 고주파 집적회로장치의 기본 주파수는 800MHz 이상인 것을 특징으로 하는 고주파 집적회로 장치.
  10. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 적층체 중의 오목부에는 상기 저면보다도 높은 중간면이 존재하도록 적어도 하나의 계단부가 형성되어 있고 상기 회로요소에는 상기 중간면 상에 형성된 배선층이 포함되어 있으며 상기 오목부 저면상의 반도체 칩과 배선층이 본딩와이어에 의하여 결선되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  11. 제10항에 있어서 상기 본딩와이어의 최고 부위는 적층체 맨 위의 기판 상면보다도 낮은 것을 특징으로 하는 고주파 집적회로 장치.
  12. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 반도체 칩은 상기 능동소자가 배설된 면을 상기 오목부의 저면측을 향한 상태에서 상기 오목부 저면을 구성하는 기판 상에 플립칩ㆍ본딩에 의하여 탑재되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  13. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 적층체의 오목부 중 상기 반도체 칩을 포함하는 영역이 포팅수지에 의하여 밀봉되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  14. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 회로요소에는 마이크로 스트립라인 및 칩 부품으로 구성되는 고주파 정합회로와 배선층이 포함되어 있고 상기 고주파 정합회로와 배선층은 상기 적층체의 최상층에 배설되어 있고, 상기 고주파 정합회로 및 배선층 중, 상기 배선층의 납땜용 부분과 상기 고주파 정합회로의 정합용 마이크로 스트립라인의 부분을 제외하는 영역 및 상기 칩 부품 상에 수지계 재료 및 유리계 재료 중 어느 하나에 의하여 구성되는 코팅제가 선택적으로 도포되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  15. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 적층체의 최상층 위에 수지계 재료 및 유리계 재료 중 어느 하나에 의하여 구성되는 코팅재가 그 상면상에 다른 부재가 돌출하지 않도록 두껍게 도포되고, 상기 코팅재의 상면이 평탄화되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  16. 제15항에 있어서 상기 코팅재의 평탄화된 상면상에 도전성 재료가 도포되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  17. 제1항, 제2항,제3항 또는 제4항에 있어서 상기 회로요소에는 필터회로를 가지는 바이어스 회로가 포함되어 있고, 상기 필터회로의 스트립리인의 폭이 200㎛ 이상인 것을 특징으로 하는 고주파 집적회로 장치.
  18. 제1항에 있어서 상기 적층체의 오목부는 상기 적층체를 구성하는 상기 복수의 기판 중 맨 위의 기판 일부를 제거하여 형성되어 있고, 상기 반도체 칩은 그 표면측을 상기 오목부의 저면을 향한 상태에서 상기 오목부의 저면상에 플립칩 본딩되어 있으며, 상기 반도체 칩의 이면이 고주파 집적회로장치를 실장하기 위한 기기의 표면과 접촉할 수 있도록 구성되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  19. 제18항에 있어서 상기 회로요소에는 고주파 정합회로의 일부가 되는 칩 부품이 포함되어 있고, 상기 칩 부분은 상기 적층체의 맨 위 기판상에 탑재되어 있는 것을 특징으로 하는 고주파 집적회로 장치.
  20. 유전재료로 구성되는 복수의 기판을 적층하고, 상기 복수의 기판 중 맨 위 기판의 상면상의 영역인 최상층과 각 기판 사이의 영역인 적어도 하나의 중간층과 상기 복수의 기판 중 맨 아래 기판의 하면상의 영역인 최하층과 상기 각 기판의 측면상의 영역인 측방층으로 상기 회로요소가 분산하여 배치 가능하게 구성된 적층체를 형성한 후, 상기 적층체의 각 기판 중 일부의 기판을 부분적으로 제거하고, 저면과 이 저면보다는 높은 중간면이 존재하도록 적어도 하나의 계단부를 가지는 오목부를 형성하며, 상기 중간면, 취상층 및 중간층에 배선전극과 회로요소를 형성하여 두는 공정과 상기 오목부의 저면에 외부기기와의 접속용 전극을 가지는 반도체 칩을 215℃이상인 융점의 땜납재로 다이스본드하는 공정과 상기 반도체 칩의 전극과 상기 오목부 중간면상의 배선전극을 와이어로 접속하는 공정과 상기 다이스본드에 이용한 상기 땜잡재 이하의 융점을 가지는 크립땜납을 납땜마스크를 이용하여 상기 적층체 최상층인 배선층의 소정 장소 위에 도포하는 공정와 상기 크림 납땜이 도포된 영역 위에 칩 부품을 마운트하여 리플로에 의한 납땜을 시행하는 공정을 구비하고 있는 것을 특징으로 하는 고주파 집적회로장치의 제조방법.
  21. 유전재료로 구성되는 복수의 기판을 적층하고, 상기 복수의 기판 중 맨 위 기판의 상면상의 영역인 최상층과 각 기판 사이의 영역인 적어도 하나의 중간층과 상기 복수의 기판 중 맨 아래 기판의 하면상의 영역인 최하층과 상기 각 기판의 측면상의 영역인 측방층으로 상기 회로요소가 분산하여 배치 가능하게 구성된 적층체를 형성한 후, 상기 적층체의 각 기판 중 일부의 기판을 부분적으로 제거하고, 저면과 이 저면보다는 높은 중간면이 존재하도록 적어도 하나의 계단부를 가지는 오목부를 형성하며, 상기 중간면, 최상층 및 중간층에 배선전극과 회로요소를 형성하여 두는 공정과 크립땜납을 납땜마스크를 이용하여 상기 적층체 최상층인 배선층의 소정 장소위에 도포하는 공정와, 상기 크립땜납이 도포된 영역 위에 칩 부품을 마운트하여 리플로에 의한 납땜을 시행하는 공정과, 상기 오목부의 저명에 외부기기과의 접속용 전극을 가지는 반도체 칩을 질화 붕소 혹은은을 포함하는 수지계의 페이스트를 이용하여 다이스본드하는 공정과 상기 반도체 집의 전극과 상기 오목부 중간면상의 배선전극을 와이어로 접속하는 공정을 구비하고 있는 것을 특징으로 하는 고주파 집적회로장치의 제조방법.
KR1019960013253A 1996-03-19 1996-04-27 적층체를구비한고주파집적회로장치 KR100367936B1 (ko)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100518643B1 (ko) * 2002-01-24 2005-10-05 미쓰비시덴키 가부시키가이샤 반도체장치 및 그 제조방법, 인쇄 마스크
KR100527223B1 (ko) * 1998-04-10 2005-11-08 다이요 유덴 가부시키가이샤 고주파 전력 증폭 회로 및 고주파 전력 증폭 모듈
US7339269B2 (en) 2001-09-28 2008-03-04 Fujitsu Ten Limited High frequency IC package, high frequency unit using high frequency IC package, and manufacturing method thereof
US7560811B2 (en) 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device
KR20230144782A (ko) * 2022-04-08 2023-10-17 숭실대학교산학협력단 하이브리드 집적회로

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748156B1 (fr) * 1996-04-26 1998-08-07 Suisse Electronique Microtech Dispositif comprenant deux substrats destines a former un microsysteme ou une partie d'un microsysteme et procede d'assemblage de deux substrats micro-usines
JPH10322147A (ja) * 1996-10-04 1998-12-04 Toshiba Corp 高周波電力増幅器およびこれを用いた移動体通信装置
US5918112A (en) * 1997-07-24 1999-06-29 Motorola, Inc. Semiconductor component and method of fabrication
WO1999033172A1 (fr) * 1997-12-22 1999-07-01 Hitachi, Ltd. Systeme d'amplification de puissance et terminal de communication radio mobile
JP3859340B2 (ja) * 1998-01-06 2006-12-20 三菱電機株式会社 半導体装置
US6075995A (en) * 1998-01-30 2000-06-13 Conexant Systems, Inc. Amplifier module with two power amplifiers for dual band cellular phones
US6229404B1 (en) * 1998-08-31 2001-05-08 Kyocera Corporation Crystal oscillator
US6404048B2 (en) * 1998-09-03 2002-06-11 Micron Technology, Inc. Heat dissipating microelectronic package
JP2000165085A (ja) * 1998-11-24 2000-06-16 Nec Corp フレキシブルボード及びその不要輻射防止方法並びに携帯 電話機
JP2000307452A (ja) * 1999-02-16 2000-11-02 Murata Mfg Co Ltd 高周波複合部品及びそれを用いた携帯無線機
JP3500335B2 (ja) 1999-09-17 2004-02-23 株式会社東芝 高周波回路装置
US6631555B1 (en) * 2000-02-08 2003-10-14 Cardiac Pacemakers, Inc. Method of thin film deposition as an active conductor
JP2001284783A (ja) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd 表面実装用基板及び表面実装構造
US6861905B2 (en) * 2000-05-08 2005-03-01 Renesas Technology Corp. Power amplifier system and mobile communication terminal device
JP3609692B2 (ja) * 2000-05-24 2005-01-12 松下電器産業株式会社 高周波信号増幅装置およびその製造方法
CN1543298A (zh) * 2000-06-27 2004-11-03 ���µ�����ҵ��ʽ���� 陶瓷叠层器件
US6487083B1 (en) * 2000-08-10 2002-11-26 Nortel Networks Ltd. Multilayer circuit board
JP3822040B2 (ja) * 2000-08-31 2006-09-13 株式会社ルネサステクノロジ 電子装置及びその製造方法
US6462950B1 (en) * 2000-11-29 2002-10-08 Nokia Mobile Phones Ltd. Stacked power amplifier module
TW575949B (en) * 2001-02-06 2004-02-11 Hitachi Ltd Mixed integrated circuit device, its manufacturing method and electronic apparatus
SG100635A1 (en) * 2001-03-09 2003-12-26 Micron Technology Inc Die support structure
US6798055B2 (en) * 2001-03-12 2004-09-28 Micron Technology Die support structure
US6455925B1 (en) * 2001-03-27 2002-09-24 Ericsson Inc. Power transistor package with integrated flange for surface mount heat removal
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP2003100937A (ja) * 2001-09-26 2003-04-04 Hitachi Ltd 高周波モジュール
EP1298969A1 (en) * 2001-09-27 2003-04-02 Agilent Technologies, Inc. (a Delaware corporation) Base member for mounting high-frequency components
US20030066679A1 (en) * 2001-10-09 2003-04-10 Castro Abram M. Electrical circuit and method of formation
US6633005B2 (en) * 2001-10-22 2003-10-14 Micro Mobio Corporation Multilayer RF amplifier module
KR100423405B1 (ko) * 2001-12-04 2004-03-18 삼성전기주식회사 온도보상 수정발진기
JP2003188338A (ja) * 2001-12-13 2003-07-04 Sony Corp 回路基板装置及びその製造方法
TW523894B (en) 2001-12-24 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor device and its manufacturing method
JP2003258192A (ja) * 2002-03-01 2003-09-12 Hitachi Ltd 半導体装置およびその製造方法
FR2837061A1 (fr) * 2002-03-11 2003-09-12 Thales Sa Substrat multicouches ceramique pour composant de puissance, module et circuit electronique comportant le substrat et procede de fabrication du substrat
JP3575478B2 (ja) * 2002-07-03 2004-10-13 ソニー株式会社 モジュール基板装置の製造方法、高周波モジュール及びその製造方法
US6847111B2 (en) * 2002-07-18 2005-01-25 Orient Semiconductor Electronics, Ltd. Semiconductor device with heat-dissipating capability
US20040080917A1 (en) * 2002-10-23 2004-04-29 Steddom Clark Morrison Integrated microwave package and the process for making the same
US6806563B2 (en) * 2003-03-20 2004-10-19 International Business Machines Corporation Composite capacitor and stiffener for chip carrier
US7116557B1 (en) * 2003-05-23 2006-10-03 Sti Electronics, Inc. Imbedded component integrated circuit assembly and method of making same
WO2005024946A1 (ja) * 2003-09-04 2005-03-17 Renesas Technology Corp. 半導体装置およびその製造方法
FI20031341A (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
JP3999759B2 (ja) * 2004-04-02 2007-10-31 富士通株式会社 基板及び電子機器
US7411279B2 (en) * 2004-06-30 2008-08-12 Endwave Corporation Component interconnect with substrate shielding
US7348666B2 (en) * 2004-06-30 2008-03-25 Endwave Corporation Chip-to-chip trench circuit structure
JP4014591B2 (ja) * 2004-10-05 2007-11-28 シャープ株式会社 半導体装置および電子機器
TW200612345A (en) * 2004-10-07 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof
KR100772460B1 (ko) * 2005-05-26 2007-11-01 텔레포스 주식회사 집적 수동소자 칩 및 그 제조방법
US7279983B2 (en) * 2005-11-18 2007-10-09 Semiconductor Components Industries, L.L.C. Output amplifier structure with bias compensation
DE102006032925B8 (de) * 2006-07-15 2008-11-06 Schott Ag Elektronische Baugruppe und Verfahren zur Verkapselung elektronischer Bauelemente und integrierter Schaltungen
US7838976B2 (en) * 2006-07-28 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a semiconductor chip enclosed by a body structure and a base
KR101478810B1 (ko) 2006-07-28 2015-01-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 축전 장치
US8232621B2 (en) * 2006-07-28 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7675365B2 (en) * 2007-01-10 2010-03-09 Samsung Electro-Mechanics Systems and methods for power amplifiers with voltage boosting multi-primary transformers
DE102007056269A1 (de) * 2007-10-22 2009-04-23 Rohde & Schwarz Gmbh & Co. Kg Gekühltes Multichipmodul
US7576607B2 (en) * 2008-01-03 2009-08-18 Samsung Electro-Mechanics Multi-segment primary and multi-turn secondary transformer for power amplifier systems
US7812701B2 (en) 2008-01-08 2010-10-12 Samsung Electro-Mechanics Compact multiple transformers
US8044759B2 (en) * 2008-01-08 2011-10-25 Samsung Electro-Mechanics Overlapping compact multiple transformers
US7746174B2 (en) * 2008-06-12 2010-06-29 Samsung Electro-Mechanics Company, Ltd. Systems and methods for power amplifier with integrated passive device
JP4557186B2 (ja) * 2008-06-25 2010-10-06 株式会社村田製作所 無線ｉｃデバイスとその製造方法
EP2161747A1 (en) * 2008-09-04 2010-03-10 Shinko Electric Industries Co., Ltd. Electronic component package and method of manufacturing the same
US20100059876A1 (en) * 2008-09-05 2010-03-11 Shinko Electric Industries Co., Ltd. Electronic component package and method of manufacturing the same
US8076587B2 (en) * 2008-09-26 2011-12-13 Siemens Energy, Inc. Printed circuit board for harsh environments
JP5509724B2 (ja) * 2009-08-20 2014-06-04 富士通株式会社 マルチチップモジュールの製造方法
JP5635247B2 (ja) * 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
US8217272B2 (en) * 2009-12-18 2012-07-10 Intel Corporation Apparatus and method for embedding components in small-form-factor, system-on-packages
US8125276B2 (en) * 2010-03-12 2012-02-28 Samsung Electro-Mechanics Sharing of inductor interstage matching in parallel amplification system for wireless communication systems
JP2016096300A (ja) 2014-11-17 2016-05-26 三菱電機株式会社 プリント回路板
JP6139585B2 (ja) * 2015-03-05 2017-05-31 株式会社東芝 高周波モジュール及びマイクロ波送受信装置
US9960127B2 (en) 2016-05-18 2018-05-01 Macom Technology Solutions Holdings, Inc. High-power amplifier package
WO2018004686A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate
US10134658B2 (en) 2016-08-10 2018-11-20 Macom Technology Solutions Holdings, Inc. High power transistors
WO2018125097A1 (en) * 2016-12-28 2018-07-05 Xu Yi Elyn Embedded component and methods of making the same
WO2018168591A1 (ja) * 2017-03-13 2018-09-20 株式会社村田製作所 モジュール
US11410897B2 (en) * 2019-06-27 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a dielectric layer edge covering circuit carrier
US20230420430A1 (en) * 2022-06-24 2023-12-28 Wolfspeed, Inc. Modular power transistor component assemblies with flip chip interconnections

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3809076A1 (de) * 1988-03-18 1989-09-28 Philips Patentverwaltung Schaltungsanordnung zur auswertung eines video-synchronsignales
JPH02198158A (ja) * 1989-01-27 1990-08-06 Hitachi Ltd 半導体装置
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
JPH04150058A (ja) * 1990-10-12 1992-05-22 Nec Corp 半導体集積回路
JPH04256203A (ja) * 1991-02-07 1992-09-10 Mitsubishi Electric Corp マイクロ波帯ｉｃ用パッケージ
JPH05275609A (ja) * 1992-03-26 1993-10-22 Hitachi Ltd 半導体モジュール基板
US5702985A (en) * 1992-06-26 1997-12-30 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method
US5317196A (en) * 1992-08-28 1994-05-31 At&T Bell Laboratories Encapsulant method and apparatus
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
JP2901835B2 (ja) * 1993-04-05 1999-06-07 株式会社東芝 半導体装置
US5510758A (en) * 1993-04-07 1996-04-23 Matsushita Electric Industrial Co., Ltd. Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5523422A (en) * 1994-10-14 1996-06-04 E. I. Du Pont De Nemours And Company Monomer precursor isomerization

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527223B1 (ko) * 1998-04-10 2005-11-08 다이요 유덴 가부시키가이샤 고주파 전력 증폭 회로 및 고주파 전력 증폭 모듈
US7339269B2 (en) 2001-09-28 2008-03-04 Fujitsu Ten Limited High frequency IC package, high frequency unit using high frequency IC package, and manufacturing method thereof
KR100518643B1 (ko) * 2002-01-24 2005-10-05 미쓰비시덴키 가부시키가이샤 반도체장치 및 그 제조방법, 인쇄 마스크
US7560811B2 (en) 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device
KR100939402B1 (ko) * 2005-12-08 2010-01-28 야마하 가부시키가이샤 반도체 장치
KR20230144782A (ko) * 2022-04-08 2023-10-17 숭실대학교산학협력단 하이브리드 집적회로

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