KR970067800A - 반도체장치 - Google Patents

반도체장치 Download PDF

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KR970067800A
KR970067800A KR1019960038854A KR19960038854A KR970067800A KR 970067800 A KR970067800 A KR 970067800A KR 1019960038854 A KR1019960038854 A KR 1019960038854A KR 19960038854 A KR19960038854 A KR 19960038854A KR 970067800 A KR970067800 A KR 970067800A
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electrode
electrode portions
main surface
thickness
portions
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KR100194746B1 (ko
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요시히로 토미타
아키요시 사와이
가쓰노리 아사이
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기타오카 다카시
미쓰비시덴키 주식회사
요시토미 마사오
료덴세미컨덕터시스템 엔지니어링 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H—ELECTRICITY
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    • H01L2924/013—Alloys
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

반도체칩을 플립 칩 방식으로 실장하는 반도체장치에 관한 것으로, 반도체칩과 실장기판 사이에 형성되는 전기적 접속수단의 피로수명의 향상을 도모하기 위해, LSI칩1의 이면에 각각이 범프전극2 및 랜드전극3으로 이루어지는 여러개의 돌기 전극부20이 마련되고, 범프전극2가 제1의 두께를 갖는 대략 구형상으로 이루어지고, 제2의 두께를 갖는 대략 구형상의 여러개의 접속단자5가 랜드2전극3중 대응하는 랜드전극3에 가열용융에 의해 집적 접속되며, 여러개의 접속패턴6이 LSI칩1에 비해서 평면형상의 면적이 큰 배선판7이 상면에 형성되고, 배선기판7의 하면에는 각각 접속패턴8 및 외부전극9로 이루어지는 여러개의 외부전극부30이 마련되고, 외부전극9가 제3의 두께를 갖는 대략 구형상으로 이루어지고, 여러개의 접속패턴6이 접속단자5중 대응하는 접속단자5에 가열용융에 의해 집적 접속되는 구성으로 되어 있다, 이러한 구성으로 하는 것에 의해, 여러개의 외부전극부 형성시의 설계자유도가 향상하여 위하는 실장기판상에 배치할 수 있으며, 여러개의 돌기전극부의 열피로를 억제하여 장치의 신뢰성을 향상시킬 수 있다.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 1은 본 발명의 실시예1의 제1의 형태의 반도체장치의 구성을 도시한 단면도

Claims (10)

  1. 제1 및 제2의 주면을 갖고, 제1의 두께를 갖고 제2의 주면에 형성된 여러개의 돌기전극부를 포함하는 반도체칩, 각각 제2의 두께를 갖고 상기 여러개의 돌기전극부 중 대응하는 돌기전극부에 직접 접속되는 여러개의 접속단자, 상기 여러개의 돌기전극부를 포함하는 상기 반도체칩의 제2의 주면상을 피복하도록 형성된 수지 및 제1 및 제2의 주면을 갖고 상기 제1의 주면에 형성된 여러개의 전극 영역과 제3의 두께를 갖고 상기 제2의 주면에 형성된 여러개의 외부전극부를 각각 포함하는 접속판을 구비하고, 상기 여러개의 전극영역은 각각 상기 여러개의 외부전극부 중 대응하는 외부전극부에 전기적으로 접속되고 또한 각각 상기 여러개의 접속단자 중 대응하는 접속단자에 직접 접속되는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 수지는 상기 반도체칩 전체를 더 피복하도록 형성되는것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 접속판은 상기 반도체칩보다 큰 평면형상을 갖고, 상기 외부전극부의 인접하는 전극부 사이의 간격은 상기 돌기전극부의 인접하는 전극부 사이의 간격보다 넓은 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 접속판은 상기 반도체칩과 동일한 평면형상을 갖고, 상기 외부전극부의 인접하는 전극부 사이의 간격은 상기 돌기전극부의 인접하는 전극부 사이의 간격과 동일한 것을 특징으로 하는 반도체 장치.
  5. 제3항에 있어서, 상기 돌기전극부는 각각 상기 수지의 계면에 형성된 평탄한 도체페턴을 그의 선단영역에 갖고, 상기 돌기전극부의 상기 도체페턴은 상기 접속단자 중 대응하는 접속단자에 직접 접속되어 있는 것을 특징으로 하는 반도체 장치.
  6. 제5항에 있어서, 상기 전극영역은 각각 제2의 도체패턴을 포함하고, 상기 외부전극부는 각각 상기 접속판의 제2의 주면의 접속영역에 직접 접속된 제3의 도체패턴을 포함하는 것을 특징으로 하는 반도체 장치.
  7. 제5항에 있어서, 상기 수지는 상기 접속단자 및 상기 전극영역을 포함하는 상기 접속판의 제1의 주면상에 또 형성되는 반도체 장치.
  8. 제3항에 있어서, 상기 돌기전극부, 상기 접속단자 및 상기 외부전극부의 주면부의 융점을 각각 T1, T2 및T3으로 설정했을 때, T1＞T2≥T3의 관계를 만족하는 것을 특징으로 하는 반도체 장치.
  9. 제3항에 있어서, 상기 돌기전극부의 주요부는 융점T1을 갖는 제1의 제료로 구성되고, 상기 외부 전극부의 주요부는 융점T2(T2＜T1)을 갖는 제2의 재료로 구성되고, 상기 접속단자는 각각 상기 제1의 재료로 이루어지는 제1 영역과 상기 제2의 재료로 이루어지는 제2의 영역으로 이루어지고, 상기 접속단자의 상기 제1 영역이 상기 돌기전극부중 대응하는 돌기전극부와 직접 접속되어 있는 것을 특징으로 하는 반도체 장치.
  10. 제3항에 있어서, 제1 및 제2의 주면을 갖고, 상기 제1의 두께를 갖고 상기 제2의 주면에 형성된 여러개의 제2 돌기전극부를 포함하는 제2의 반도체칩, 각각 상기 제2의 두께를 갖고 여러개의 제2 돌기전극부중 대응하는 돌기전극부에 직접 접속되어 있는 여러개의 제2 접속단자 및 상기 여러개의 제2 돌기전극부를 포함하는 상기 제2 반도체칩의 제2의 주면상을 피복하도록 형성된 제2의 수지를 더 구비하고, 상기 접속판은 제1의 주면에 형상된 여러개의 제2 전극영역과 상기 제3의 두께를 갖고 상기 제2의 주면에 형성된 여러개의 제2 외부전극부를 더 포함하고, 상기 여러개의 제2 전극영역은 각각 상기 여러개의 제2 외부전극부중 대응하는 제2 외부전극부에 전기적으로 접속되고 또한 상기 여러개의 제2 접속단자중 대응하는 제2 접속단자에 직접 접속되는 것을 특징으로 하는 반도체 장치.
KR1019960038854A 1996-03-27 1996-09-09 반도체장치 KR100194746B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP07221596A JP3863213B2 (ja) 1996-03-27 1996-03-27 半導体装置
JP96-72215 1996-03-27

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KR970067800A true KR970067800A (ko) 1997-10-13
KR100194746B1 KR100194746B1 (ko) 1999-06-15

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US (1) US5666008A (ko)
JP (1) JP3863213B2 (ko)
KR (1) KR100194746B1 (ko)
CN (1) CN1128475C (ko)
DE (1) DE19644297A1 (ko)
TW (1) TW362264B (ko)

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KR20000017577A (ko) * 1998-08-27 2000-03-25 어드밴티스트 코포레이션 고성능 집적 회로칩 패키지

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KR100194746B1 (ko) 1999-06-15
TW362264B (en) 1999-06-21
CN1160932A (zh) 1997-10-01
US5666008A (en) 1997-09-09
JP3863213B2 (ja) 2006-12-27
DE19644297A1 (de) 1997-10-02
CN1128475C (zh) 2003-11-19

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