CN112117196B - 安装构造 - Google Patents
安装构造 Download PDFInfo
- Publication number
- CN112117196B CN112117196B CN202010424588.9A CN202010424588A CN112117196B CN 112117196 B CN112117196 B CN 112117196B CN 202010424588 A CN202010424588 A CN 202010424588A CN 112117196 B CN112117196 B CN 112117196B
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- Prior art keywords
- terminal
- mounting
- connection
- terminal portion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims abstract description 166
- 229920005989 resin Polymers 0.000 claims abstract description 74
- 239000011347 resin Substances 0.000 claims abstract description 74
- 238000007789 sealing Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000017525 heat dissipation Effects 0.000 abstract description 15
- 239000000463 material Substances 0.000 description 17
- 239000010410 layer Substances 0.000 description 10
- 238000007747 plating Methods 0.000 description 10
- 239000002344 surface layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
本发明提供一种能够确保已安装的配线衬底表面上的散热面积的半导体装置及半导体装置的安装构造。本发明的半导体装置(A1)具备半导体元件(3)、第1引脚(1)、多个第2引脚(2)及密封树脂(5)。第1引脚(1)具有沿厚度方向观察时为矩形状且搭载半导体元件(3)的搭载部(110)、分别从搭载部(110)的4个角延伸的4个连结部(130)、及分别连接于各连结部(130)的前端的4个第1端子部(120)。各第1端子部(120)的一部分从密封树脂(5)露出。第2引脚(2)沿厚度方向观察时,在相邻的第1端子部(120)之间排列且分别各配置多个,而且具有一部分从密封树脂(5)露出的第2端子部(220)、及从第2端子部(220)朝向搭载部(110)延伸的连接部(210)。连结部(130)的连结部宽度尺寸(W1)大于与该连结部(130)相邻的第2引脚(2)的连接部(210)的连接部宽度尺寸(W2)。
Description
技术领域
本发明涉及一种半导体装置及半导体装置的安装构造。
背景技术
作为表面安装在配线衬底的半导体装置,开发了QFN(Quad Flat Non-leadedpackage,四方形扁平无引脚封装)型半导体装置。在专利文献1中,揭示了QFN型半导体装置的一例。QFN型半导体装置是沿着4个侧面分别配置着多个电极垫。另外,QFN型半导体装置有在背面配置着用来释放半导体元件发出的热的散热垫的半导体装置。
图17表示这种以往的半导体装置A100的仰视图。半导体装置A100使搭载半导体元件的第1引脚1从密封树脂5的背面露出。半导体装置A100安装在配线衬底时,第1引脚1的背面连接于配线衬底的散热垫用焊盘。由此,半导体元件发出的热经由第1引脚1传递到散热垫用焊盘而释放。
另一方面,在半导体装置A100的底面配置着使多个第2引脚2分别从密封树脂5的背面露出的电极垫。各第2引脚2通过接合线4连接于半导体元件3。多个电极垫沿着4个侧面分别并排配置多个。半导体装置A100安装在配线衬底时,各电极垫分别连接于配线衬底的电极垫用焊盘。由此,电极垫用焊盘以包围散热垫用焊盘周围的方式配置。因此,难以在配线衬底的表面上扩展散热垫用焊盘、或者设置从将散热垫用焊盘包围的电极垫用焊盘之间连接至散热垫用焊盘的配线。也就是说,存在难以扩大配线衬底表面上的散热面积,而导致无法在配线衬底的表面上确保充分的散热面积的情况。
[背景技术文献]
[专利文献]
[专利文献1]日本专利特开2013-21052号公报
发明内容
[发明要解决的问题]
本发明是基于所述情况而想到的,它的课题在于:提供一种能够确保已安装的配线衬底表面上的散热面积的半导体装置。
[解决问题的技术手段]
由本发明提供的半导体装置具备:半导体元件;第1引脚,具有沿厚度方向观察时为矩形状且搭载所述半导体元件的搭载部、分别从所述搭载部的4个角延伸的4个连结部、及分别连接于所述各连结部的前端的4个第1端子部;多个第2引脚,沿所述厚度方向观察时,在相邻的所述第1端子部之间,与所述搭载部的各端缘平行排列且分别各配置多个;以及密封树脂,将所述第1引脚及所述各第2引脚各覆盖至少一部分;且所述各第1端子部的一部分从所述密封树脂露出,所述各第2引脚具有一部分从所述密封树脂露出的第2端子部、及从所述第2端子部朝向所述搭载部延伸的连接部,所述连结部的连结部宽度尺寸大于与该连结部相邻的所述第2引脚的所述连接部的连接部宽度尺寸,所述连结部宽度尺寸是与该连结部延伸的方向及所述厚度方向正交的方向的尺寸,所述连接部宽度尺寸是与该连接部延伸的方向及所述厚度方向正交的方向的尺寸。
[发明的效果]
根据本发明,搭载着半导体元件的搭载部经由宽度尺寸较大的连结部而连接于第1端子部。由于第1端子部的一部分从密封树脂露出,所以将半导体装置安装在配线衬底时,可将第1端子部的露出部分连接于配线衬底上的焊盘。由此,本发明的半导体装置能够将半导体元件发出的热经由连结部释放到配线衬底上的连接着第1端子部的焊盘。连接第1端子部的焊盘可扩展到比由连接第2引脚的焊盘所包围的区域更靠外侧。因此,本发明的半导体装置能够确保已安装的配线衬底表面上的散热面积。
本发明的其他特征及优点通过以下参照附图进行的详细说明而更加明确。
附图说明
图1是表示本发明的第1实施方式的半导体装置的俯视图。
图2是图1所示的半导体装置的主要部分俯视图。
图3是图1所示的半导体装置的仰视图。
图4是沿着图1的IV-IV线的剖视图。
图5是沿着图1的V-V线的剖视图。
图6是图1所示的半导体装置的主要部分放大俯视图。
图7是表示在配线衬底安装着图1所示的半导体装置的状态的俯视图。
图8是沿着图7的VIII-VIII线的主要部分放大剖视图。
图9是表示用于比较的半导体装置的俯视图。
图10是表示在用于比较的配线衬底安装着用于比较的半导体装置的状态的俯视图。
图11的(a)是表示安装着用于比较的半导体装置的用于比较的配线衬底中的温度分布的图,图11的(b)是表示安装着图1所示的半导体装置的配线衬底中的温度分布的图。
图12是表示在另一配线衬底安装着图1所示的半导体装置的状态的主要部分放大剖视图。
图13是表示本发明的第2实施方式的半导体装置的仰视图。
图14是表示在配线衬底安装着本发明的第2实施方式的半导体装置的状态的主要部分放大剖视图。
图15是表示本发明的第3实施方式的半导体装置的仰视图。
图16是表示在配线衬底安装着本发明的第3实施方式的半导体装置的状态的主要部分放大剖视图。
图17是表示以往的半导体装置的仰视图。
具体实施方式
以下,参照附图对本发明的优选实施方式具体进行说明。
(第1实施方式)
基于图1~图6对本发明的第1实施方式的半导体装置A1进行说明。半导体装置A1具备第1引脚1、第2引脚2、半导体元件3、接合线4及密封树脂5。半导体装置A1是所谓的QFN(Quad Flat Non-leaded package)型封装。
图1是表示半导体装置A1的俯视图。图2是表示半导体装置A1的主要部分俯视图。图3是表示半导体装置A1的仰视图。图4是沿着图1的IV-IV线的剖视图。图5是沿着图1的V-V线的剖视图。图6是主要部分放大俯视图。在图2及图6中,为了便于理解,透过密封树脂5以假想线(双点划线)表示密封树脂5的外形。
这些图所示的半导体装置A1是表面安装在各种设备的配线衬底的装置。半导体装置A1的沿厚度方向观察时的形状为矩形状。为了便于说明,将半导体装置A1的厚度方向设为z方向,将与z方向正交的沿着半导体装置A1的一边的方向(图1中的左右方向)设为x方向,将与z方向及x方向正交的方向(图1中的上下方向)设为y方向。半导体装置A1的大小并无特别限定,在本实施方式中,例如x方向尺寸为2~10mm左右,y方向尺寸为2~10mm左右,z方向尺寸为0.5~2mm左右。
第1引脚1及第2引脚2包含金属,优选包含Cu及Ni中的任一种、或者它们的合金或42合金等。在本实施方式中,以第1引脚1及第2引脚2包含Cu的情况为例进行说明。第1引脚1及第2引脚2的厚度例如为0.08~0.5mm,在本实施方式中为0.125mm左右。第1引脚1及第2引脚2例如通过对金属板实施蚀刻加工而形成。此外,第1引脚1及第2引脚2也可通过对金属板实施冲切加工或弯折加工等而形成。
如图2所示,沿z方向观察时,第1引脚1配置在半导体装置A1的中央,并扩展到半导体装置A1的x方向及y方向的两端部。第1引脚1负责支撑半导体元件3且对半导体元件3发出的热进行散热的功能。此外,第1引脚1也可与半导体元件3导通。第1引脚1具备搭载部110、4个第1端子部120及4个连结部130。
搭载部110沿z方向观察时位于第1引脚1的中央,且沿z方向观察时为大致矩形状。沿z方向观察时,搭载部110的各边与x方向或y方向平行。搭载部110具有搭载部主面111及搭载部背面112。搭载部主面111及搭载部背面112在z方向上相互朝向相反侧。搭载部主面111是朝向图4及图5的上方的面。搭载部主面111是搭载半导体元件3的面。搭载部背面112是朝向图4及图5的下方的面。搭载部背面112从密封树脂5露出,成为背面端子。在本实施方式中,搭载部主面111大于搭载部背面112。此外,搭载部主面111与搭载部背面112也可为相同大小。
各第1端子部120沿z方向观察时分别配置在半导体装置A1的4个角。各第1端子部120沿z方向观察时为矩形状。各第1端子部120具有第1端子部主面121、第1端子部背面122及2个第1端子部端面123。第1端子部主面121及第1端子部背面122在z方向上相互朝向相反侧。第1端子部主面121是朝向图4及图5的上方的面。第1端子部背面122是朝向图4及图5的下方的面。第1端子部端面123是将第1端子部主面121与第1端子部背面122相连的面,且与第1端子部主面121及第1端子部背面122正交。1个第1端子部端面123朝向x方向外侧,1个第1端子部端面123朝向y方向外侧。第1端子部背面122及2个第1端子部端面123分别从密封树脂5露出并相连,成为端子(参照图5)。
各连结部130分别与搭载部110及各第1端子部120相连。各连结部130沿z方向观察时,分别从位于半导体装置A1的中央的搭载部110的4个角呈放射状延伸,且与分别配置在半导体装置A1的4个角的第1端子部120中的任一个相连。连结部130的厚度(z方向的尺寸)为搭载部110的厚度的一半左右。连结部130例如通过半蚀刻处理而形成。连结部130具有连结部主面131及连结部背面132。连结部主面131及连结部背面132在z方向上相互朝向相反侧。连结部主面131是朝向图4及图5的上方的面。连结部主面131、搭载部主面111及第1端子部主面121是同一平面的成为一体的面(参照图2及图5)。连结部背面132是朝向图4及图5的下方的面。
在第1引脚1中的从密封树脂5露出的所有部分形成有未图示的表层镀覆层。在本实施方式中,在搭载部背面112、第1端子部背面122及第1端子部端面123形成有表层镀覆层。表层镀覆层包含焊料润湿性比第1引脚1的母材高的材质,在本实施方式中,例如包含Au。表层镀覆层例如通过置换型无电解镀覆而形成。此外,也可不形成表层镀覆层。
如图2所示,多个第2引脚2沿z方向观察时,在半导体装置A1的x方向的两端部或y方向的两端部相互隔开并且分别与第1引脚1隔开地配置。更具体来说,在配置于半导体装置A1的y方向一端(在图2中为上侧端)的2个第1端子部120之间,多个第2引脚2与搭载部110的y方向一侧(在图2中为上侧)的端缘平行地排成一列而配置。另外,在配置于半导体装置A1的y方向另一端(在图2中为下侧端)的2个第1端子部120之间,多个第2引脚2与搭载部110的y方向另一侧(在图2中为下侧)的端缘平行地排成一列而配置。另外,在配置于半导体装置A1的x方向一端(在图2中为右侧端)的2个第1端子部120之间,多个第2引脚2与搭载部110的x方向一侧(在图2中为右侧)的端缘平行地排成一列而配置。另外,在配置于半导体装置A1的x方向另一端(在图2中为左侧端)的2个第1端子部120之间,多个第2引脚2与搭载部110的x方向另一侧(在图2中为左侧)的端缘平行地排成一列而配置。
各第2引脚2分别经由接合线4与半导体元件3导通。各第2引脚2具有连接部210及第2端子部220。
第2端子部220沿z方向观察时为矩形状,在第2引脚2中,相对于第1引脚1的搭载部110配置在相反侧。第2端子部220具有第2端子部主面221、第2端子部背面222及第2端子部端面223。第2端子部主面221及第2端子部背面222在z方向上相互朝向相反侧。第2端子部主面221是朝向图4及图5的上方的面。第2端子部背面222是朝向图4及图5的下方的面。第2端子部端面223是将第2端子部主面221及第2端子部背面222相连的面,在第2端子部220中,朝向与第1引脚1的搭载部110相反侧。第2端子部背面222及第2端子部端面223分别从密封树脂5露出并相连,成为端子(参照图4)。
连接部210从第2端子部220朝向第1引脚1的搭载部110延伸。在本实施方式中,与搭载部110的y方向两侧的端缘平行地排列的第2引脚2越靠x方向两端侧配置,连接部210就相对于y方向越倾斜。另外,与搭载部110的x方向两侧的端缘平行地排列的第2引脚2越靠y方向两端侧配置,连接部210就相对于x方向越倾斜。这是为了易于通过接合线4将搭载于搭载部主面111的半导体元件3与各第2引脚2的第2端子部220连接。在本实施方式中,分别配置在最靠两端侧(与连结部130相邻)的第2引脚2的连接部210是与相邻的连结部130延伸的方向大致平行地延伸。此外,各连接部210也可不相对于x方向或y方向倾斜。
连接部210的厚度(z方向的尺寸)为第2端子部220的厚度的一半左右。连接部210例如通过半蚀刻处理而形成。连接部210具有连接部主面211及连接部背面212。连接部主面211及连接部背面212在z方向上相互朝向相反侧。连接部主面211是朝向图4及图5的上方的面。连接部主面211是供接合线4接合的面。连接部主面211及第2端子部主面221互为同一平面(参照图2及图4)。连接部背面212是朝向图4及图5的下方的面。此外,连接部210的厚度也可与第2端子部220的厚度相同。在此情况下,连接部背面212及第2端子部背面222互为同一平面。
在第2引脚2中的从密封树脂5露出的所有部分形成有未图示的表层镀覆层。在本实施方式中,在第2端子部背面222及第2端子部端面223形成有表层镀覆层。该表层镀覆层与第1引脚1的表层镀覆层相同,例如包含Au,通过置换型无电解镀覆而形成。此外,也可不形成表层镀覆层。
在本实施方式中,如图6所示,第1引脚1的连结部130的与该连结部130延伸的方向及z方向正交的方向的尺寸即连结部宽度尺寸W1足够大。具体来说,连结部宽度尺寸W1大于与该连结部130相邻的第2引脚2的连接部210的连接部宽度尺寸W2,为连接部宽度尺寸W2的3倍左右,该连接部宽度尺寸W2是与该连接部210延伸的方向及z方向正交的方向的尺寸。此外,连结部宽度尺寸W1并无限定,但理想的是连接部宽度尺寸W2的2倍以上。在本实施方式中,连结部宽度尺寸W1为0.3mm左右。此外,连结部宽度尺寸W1理想的是0.2mm以上。
另外,在本实施方式中,如图6所示,分别与第1引脚1的连结部130相邻且隔着该连结部130配置的2个第2引脚2(的连接部210)间的最小距离L1足够大。具体来说,最小距离L1为该第2引脚2的一个与该连结部130之间的最小距离L2的5倍左右。此外,最小距离L1并无限定,但理想的是最小距离L2的4倍以上。也就是说,最小距离L2相对于最小距离L1的比率理想的是1/4以下。
半导体元件3是发挥半导体装置A1的电性功能的要素。半导体元件3的种类并无特别限定,适当选择各种集成电路元件或主动功能元件、被动功能元件等。如图1及图2所示,在本实施方式中,半导体元件3沿z方向观察时为矩形状。
半导体元件3具有元件主面31、元件背面32及多个电极垫33。元件主面31及元件背面32在z方向上相互朝向相反侧。元件主面31是朝向图4及图5的上方的面。元件背面32是朝向图4及图5的下方的面。如图2所示,多个电极垫33配置在元件主面31。在本实施方式中,沿着矩形状的元件主面31的各端缘分别在一列各配置多个。此外,电极垫33的配置并无限定。半导体元件3搭载于第1引脚1的搭载部主面111。具体来说,半导体元件3的元件背面32通过接合材6接合于搭载部主面111。接合材6包含一般的绝缘性接合材或导电性接合材。在本实施方式中,由于未在元件背面32配置电极垫,所以使用绝缘性接合材作为接合材6。此外,在元件背面32配置着电极垫且使该电极垫与第1引脚1导通的情况下,使用导电性接合材作为接合材6。
多条接合线4用来使半导体元件3与第2引脚2导通。在本实施方式中,形成在半导体元件3的元件主面31的多个电极垫33与多个第2引脚2的连接部主面211分别通过多条接合线4连接。接合线4的材料并无特别限定,可列举Au、Al、Cu等。在本实施方式中,接合线4例如包含Au。
密封树脂5覆盖第1引脚1及第2引脚2的各一部分、半导体元件3及接合线4。密封树脂5例如包含黑色的环氧树脂。此外,密封树脂5的材料并无限定。
密封树脂5具有树脂主面51、树脂背面52及树脂侧面53。树脂主面51及树脂背面52在z方向上相互朝向相反侧。树脂主面51是朝向图4及图5的上方的面,树脂背面52是朝向图4及图5的下方的面。树脂侧面53是将树脂主面51及树脂背面52相连的面。在本实施方式中,树脂侧面53有4个,分别朝向x方向或y方向。
密封树脂5覆盖第1引脚1中的除搭载部背面112、第1端子部背面122及第1端子部端面123以外的部分。搭载部背面112、第1端子部背面122及第1端子部端面123从密封树脂5露出。搭载部背面112及第1端子部背面122与树脂背面52互为同一平面。第1端子部端面123与树脂侧面53互为同一平面。另外,密封树脂5覆盖各第2引脚2中的除第2端子部背面222及第2端子部端面223以外的部分。第2端子部背面222及第2端子部端面223从密封树脂5露出。第2端子部背面222与树脂背面52互为同一平面。第2端子部端面223与树脂侧面53互为同一平面。
接下来,对半导体装置A1向配线衬底上的安装进行说明。图7及图8是用来说明半导体装置A1向配线衬底9上的安装构造的图。图7是表示在配线衬底9安装着半导体装置A1的状态的俯视图。图8是沿着图7的VIII-VIII线的主要部分放大剖视图。此外,在图7中,透过半导体装置A1以假想线(双点划线)表示半导体装置A1的外形。
配线衬底9是在例如包含玻璃环氧树脂的基材上形成有例如包含Cu的配线图案的衬底。此外,基材及配线图案的材料并无限定。如图7所示,配线衬底9具备搭载部焊盘91、第1端子部焊盘92、第2端子部焊盘93、连接配线94及第2端子部连接配线95作为配线图案。
搭载部焊盘91为矩形状的焊盘,以各边与x方向或y方向平行的方式配置。第1端子部焊盘92是位于将搭载部焊盘91的对角线延长后的线上的矩形状的焊盘。对于1个搭载部焊盘91,以包围该搭载部焊盘91的方式配置着4个第1端子部焊盘92。各第1端子部焊盘92的各边与搭载部焊盘91的各边平行。也就是说,各第1端子部焊盘92的各边与x方向或y方向平行。连接配线94是将搭载部焊盘91与第1端子部焊盘92连接的配线,沿搭载部焊盘91的对角线方向延伸。对于1个搭载部焊盘91配置着4个连接配线94,各连接配线94与搭载部焊盘91及4个第1端子部焊盘92中的任一个相连。在半导体装置A1中,为了配置连结部130,分别与连结部130相邻且隔着该连结部130配置的2个第2引脚2的间隔(最小距离L1)变得足够大。因此,分别连接这2个第2引脚2的2个第2端子部焊盘93的间隔也变得足够大。因此,连接配线94可配置在该2个第2端子部焊盘93之间。
第2端子部焊盘93为朝向搭载部焊盘91延伸的长矩形状,且在搭载部焊盘91的周围配置着多个。各第2端子部焊盘93在相邻的2个第1端子部焊盘92之间相互隔开,并且分别与搭载部焊盘91、第1端子部焊盘92及连接配线94隔开地配置。更具体来说,在配置于搭载部焊盘91的y方向一侧(在图7中为上侧)的2个第1端子部焊盘92之间,多个第2端子部焊盘93与x方向平行地排成一列而配置。另外,在配置于搭载部焊盘91的y方向另一侧(在图7中为下侧)的2个第1端子部焊盘92之间,多个第2端子部焊盘93与x方向平行地排成一列而配置。另外,在配置于搭载部焊盘91的x方向一侧(在图7中为右侧)的2个第1端子部焊盘92之间,多个第2端子部焊盘93与y方向平行地排成一列而配置。另外,在配置于搭载部焊盘91的x方向另一侧(在图7中为左侧)的2个第1端子部焊盘92之间,多个第2端子部焊盘93与y方向平行地排成一列而配置。第2端子部连接配线95是与第2端子部焊盘93相连的配线。对于1个第2端子部焊盘93配置着1个第2端子部连接配线95,因此,第2端子部连接配线95配置与第2端子部焊盘93相同的数量。各第2端子部连接配线95相对于第2端子部焊盘93,向与搭载部焊盘91相反侧延伸。
在本实施方式中,如图7所示,连接配线94的与该连接配线94延伸的方向及z方向正交的方向的尺寸即连接配线宽度尺寸W3足够大。具体来说,连接配线宽度尺寸W3大于与该连接配线94相邻的第2端子部焊盘93的第2端子部焊盘宽度尺寸W4,为第2端子部焊盘宽度尺寸W4的3倍左右,该第2端子部焊盘宽度尺寸W4是与该第2端子部焊盘93延伸的方向及z方向正交的方向的尺寸。此外,连接配线宽度尺寸W3并无限定,但理想的是第2端子部焊盘宽度尺寸W4的2倍以上。在本实施方式中,连接配线宽度尺寸W3为0.3mm左右。此外,连接配线宽度尺寸W3理想的是0.2mm以上。
另外,在本实施方式中,如图7所示,分别与连接配线94相邻且隔着该连接配线94配置的2个第2端子部焊盘93之间的最小距离L3足够大。具体来说,最小距离L3为该第2端子部焊盘93的一个与该连接配线94之间的最小距离L4的5倍左右。此外,最小距离L3并无限定,但理想的是最小距离L4的4倍以上。也就是说,最小距离L4相对于最小距离L3的比率理想的是1/4以下。
此外,搭载部焊盘91、第1端子部焊盘92及第2端子部焊盘93的形状并不限定于矩形状。
半导体装置A1安装在配线衬底9,如图8所示,各端子通过焊料99与形成在配线衬底9的配线图案接合。在搭载部焊盘91接合第1引脚1的搭载部背面112。在各第1端子部焊盘92分别接合第1引脚1的任一第1端子部背面122。在各第2端子部焊盘93分别接合任一第2引脚2的第2端子部背面222。
此外,搭载部焊盘91及第1端子部焊盘92也可通过例如导孔连接于配置在配线衬底9内部的配线图案或形成在相反侧的面上的配线图案。
接下来,对半导体装置A1的作用效果进行说明。
根据本实施方式,半导体装置A1使从密封树脂5露出的搭载部背面112连接于搭载部焊盘91,从而安装于配线衬底9。半导体元件3搭载在搭载部110。搭载部焊盘91经由连接配线94连接于第1端子部焊盘92。因为连接配线宽度尺寸W3足够大,所以半导体元件3发出的热经由搭载部110、搭载部焊盘91及连接配线94传递到第1端子部焊盘92而释放。也就是说,配线衬底9表面上的散热面积扩大到将搭载部焊盘91、连接配线94及第1端子部焊盘92相加所得的面积。因此,半导体装置A1能够确保配线衬底9表面上的散热面积。
另外,根据本实施方式,搭载着半导体元件3的搭载部110经由连结部130连接于第1端子部120。第1端子部背面122从密封树脂5露出。半导体装置A1使第1端子部背面122连接于第1端子部焊盘92,从而安装在配线衬底9。因为连结部宽度尺寸W1足够大,所以半导体元件3发出的热经由搭载部110、连结部130及第1端子部120传递到配线衬底9上的第1端子部焊盘92而释放。也就是说,半导体装置A1可利用连结部130及第1端子部120进一步促进向第1端子部焊盘92的散热。
图9~图11是用来说明安装着半导体装置A1的配线衬底9中的散热状态的模拟的图。图9及图10是用来说明用于比较的半导体装置A1'及配线衬底9'的图,图11是表示模拟结果的图。
图9是表示用于比较的半导体装置A1'的俯视图,且是与图1对应的图。如图9所示,相对于半导体装置A1,半导体装置A1'未配置第1端子部120,而配置着悬空引脚130'来代替连结部130,第2引脚2配置到悬空引脚130'的附近。图10是表示在配线衬底9'安装着半导体装置A1'的状态的俯视图,且是与图7对应的图。此外,在图10中,透过半导体装置A1'以假想线(双点划线)表示半导体装置A1'的外形。如图10所示,配线衬底9'是在配线衬底9中未配置连接配线94的配线衬底。
图11的(a)是表示在安装着半导体装置A1'的配线衬底9'中使半导体元件3放热后的温度分布的图。图11的(b)是表示在安装着半导体装置A1的配线衬底9中使半导体元件3放热后的温度分布的图。如图11的(a)所示,在安装着半导体装置A1'的配线衬底9'中,仅搭载部焊盘91(图11的(a)的中央附近)的温度上升。另一方面,如图11的(b)所示,在安装着半导体装置A1的配线衬底9中,搭载部焊盘91(图11的(b)的中央附近)的热传递到第1端子部焊盘92(图11的(b)的四角附近)而释放。由此,与安装着半导体装置A1'的配线衬底9'(参照图11的(a))相比较,搭载部焊盘91的温度下降。另外,安装着半导体装置A1'的配线衬底9'中的热阻为34.0℃/W,与此相对,安装着半导体装置A1的配线衬底9中的热阻为27.7℃/W。由此也可知,热阻下降,散热效果得到改善。
另外,根据本实施方式,与连结部130相邻的第2引脚2的连接部210是与该连结部130延伸的方向大致平行地延伸。因此,可进一步增大连结部宽度尺寸W1。
另外,根据本实施方式,第1端子部120具有从树脂侧面53露出的第1端子部端面123与从树脂背面52露出的第1端子部背面122相连而成的端子(参照图5)。在将半导体装置A1安装在配线衬底9的情况下,该端子通过焊料99与形成在配线衬底9的第1端子部焊盘92接合。在第1端子部端面123形成由焊料99所形成的焊接内圆角(参照图8),所以也能够从安装后的外观来确认第1端子部120的接合状态。另外,能够利用形成在第1端子部端面123的焊接内圆角提高安装强度。
此外,在本实施方式中,对第1端子部端面123及第2端子部端面223与密封树脂5的树脂侧面53互为同一平面的情况进行了说明,但并不限于此。第1端子部端面123及第2端子部端面223可从树脂侧面53突出,也可从树脂侧面53凹陷。另外,第1端子部端面123及第2端子部端面223可平坦,可弯曲,也可形成凹凸。另外,第1端子部端面123及第2端子部端面223的形状也不受限定。
另外,在本实施方式中,对将搭载部背面112连接于搭载部焊盘91的情况进行了说明,但并不限于此。例如,如图12所示,配线衬底9也可不形成搭载部焊盘91及连接配线94。在此情况下,也是经由连结部130连接于搭载部110的第1端子部120连接于第1端子部焊盘92,因此,半导体元件3发出的热经由搭载部110、连结部130及第1端子部120传递到第1端子部焊盘92而释放。因此,可通过增大第1端子部焊盘92的面积来确保配线衬底9表面上的散热面积。
(第2实施方式)
基于图13及图14,对本发明的第2实施方式的半导体装置A2进行说明。在这些图中,对与所述半导体装置A1相同或类似的要素标注相同符号,并省略重复说明。
图13是表示半导体装置A2的仰视图,且是与第1实施方式中的图3对应的图。图14是表示在配线衬底9安装着半导体装置A2的状态的主要部分放大剖视图,且是与第1实施方式中的图8对应的图。
本实施方式的半导体装置A2与半导体装置A1的不同点在于:搭载部背面112未从密封树脂5露出。本实施方式的搭载部110的厚度(z方向的尺寸)与连结部130的厚度相同,为第1端子部120的厚度的一半左右。搭载部110例如通过半蚀刻处理而形成。因此,在本实施方式中,搭载部背面112未从密封树脂5露出。
在本实施方式中,也是经由连结部130连接于搭载部110的第1端子部120连接于第1端子部焊盘92,因此,半导体元件3发出的热经由搭载部110、连结部130及第1端子部120传递到第1端子部焊盘92而释放。因此,可通过增大第1端子部焊盘92的面积来确保配线衬底9表面上的散热面积。
(第3实施方式)
基于图15及图16,对本发明的第3实施方式的半导体装置A3进行说明。在这些图中,对与所述半导体装置A1相同或类似的要素标注相同符号,并省略重复说明。
图15是表示半导体装置A3的仰视图,且是与第1实施方式中的图3对应的图。图16是表示在配线衬底9安装着半导体装置A3的状态的主要部分放大剖视图,且是与第1实施方式中的图8对应的图。
本实施方式的半导体装置A3与半导体装置A1的不同点在于:连结部背面132从密封树脂5露出。本实施方式的连结部130的厚度(z方向的尺寸)与搭载部110及第1端子部120的厚度相同。连结部背面132、搭载部背面112及第1端子部背面122是同一平面的成为一体的面,也与树脂背面52成为同一平面。因此,在本实施方式中,连结部背面132也从密封树脂5露出。如图16所示,连结部背面132通过焊料99接合于连接配线94。
在本实施方式中,也能发挥与第1实施方式相同的效果。进而,根据本实施方式,连结部130的厚度比第1实施方式的连结部130厚。由此,连结部130更易于从搭载部110向第1端子部120传递热。另外,因为连结部背面132连接于连接配线94,所以半导体元件3发出的热也从连结部130传递到连接配线94。因此,半导体装置A3能够进一步促进散热。
本发明的半导体装置及半导体装置的安装构造并不限定于所述实施方式。本发明的半导体装置及半导体装置的安装构造的各部的具体构成可自如地进行各种设计变更。
(附记1)
一种半导体装置,具备:
半导体元件;
第1引脚,具有沿厚度方向观察时为矩形状且搭载所述半导体元件的搭载部、分别从所述搭载部的4个角延伸的4个连结部、及分别连接于所述各连结部的前端的4个第1端子部;
多个第2引脚,沿所述厚度方向观察时,在相邻的所述第1端子部之间,与所述搭载部的各端缘平行排列且分别各配置多个;以及
密封树脂,将所述第1引脚及所述各第2引脚各覆盖至少一部分;且
所述各第1端子部的一部分从所述密封树脂露出,
所述各第2引脚具有一部分从所述密封树脂露出的第2端子部、及从所述第2端子部朝向所述搭载部延伸的连接部,
所述连结部的连结部宽度尺寸大于与该连结部相邻的所述第2引脚的所述连接部的连接部宽度尺寸,所述连结部宽度尺寸是与该连结部延伸的方向及所述厚度方向正交的方向的尺寸,所述连接部宽度尺寸是与该连接部延伸的方向及所述厚度方向正交的方向的尺寸。
(附记2)
根据附记1所述的半导体装置,其中
所述连结部宽度尺寸为所述连接部宽度尺寸的2倍以上。
(附记3)
根据附记1或2所述的半导体装置,其中
所述连结部宽度尺寸为0.2mm以上。
(附记4)
根据附记1至3中任一项所述的半导体装置,其中
最小距离L2相对于最小距离L1的比率为1/4以下,所述最小距离L1是分别与所述连结部相邻且隔着该连结部配置的2个所述第2引脚间的最小距离,所述最小距离L2是该第2引脚的一个与该连结部之间的最小距离。
(附记5)
根据附记1至4中任一项所述的半导体装置,其中
所述搭载部具有搭载所述半导体元件的搭载部主面、及在所述厚度方向上朝向与所述搭载部主面相反侧的搭载部背面,且
所述搭载部背面从所述密封树脂露出。
(附记6)
根据附记5所述的半导体装置,其中
所述连结部具有在所述厚度方向上朝向与所述搭载部主面相同侧的连结部主面,且
所述搭载部主面与所述连结部主面为同一平面。
(附记7)
根据附记5或6所述的半导体装置,其中
所述第1端子部具有在所述厚度方向上朝向与所述搭载部背面相同侧的第1端子部背面,且
所述第1端子部背面从所述密封树脂露出。
(附记8)
根据附记7所述的半导体装置,其中
所述第1端子部还具有与所述第1端子部背面正交且从所述密封树脂露出的第1端子部端面。
(附记9)
根据附记5至8中任一项所述的半导体装置,其中
所述连结部由所述密封树脂覆盖。
(附记10)
根据附记5至9中任一项所述的半导体装置,其中
所述连结部具有在所述厚度方向上朝向与所述搭载部背面相同侧的连结部背面,且
所述连结部背面从所述密封树脂露出。
(附记11)
根据附记5至10中任一项所述的半导体装置,其中
所述各第2引脚的所述连接部延伸的方向相对于所述第2端子部延伸的方向倾斜,且越靠近所述连结部的所述第2引脚,该倾斜越大。
(附记12)
根据附记5至11中任一项所述的半导体装置,其中
与所述连结部相邻的所述第2引脚的所述连接部延伸的方向与该连结部延伸的方向大致平行。
(附记13)
一种安装构造,是具备根据附记5至12中任一项所述的半导体装置、及供安装所述半导体装置的配线衬底的半导体装置的安装构造,且
所述配线衬底具备:
搭载部焊盘,接合所述搭载部背面;
4个第1端子部焊盘,分别接合所述各第1端子部;
多个第2端子部焊盘,分别接合所述各第2端子部;及
4个连接配线,分别连接于所述搭载部焊盘及所述各第1端子部焊盘。
(附记14)
根据附记13所述的安装构造,其中
所述各第2端子部焊盘朝向所述搭载部焊盘延伸,且
所述连接配线的连接配线宽度尺寸大于与该连接配线相邻的所述第2端子部焊盘的第2端子部焊盘宽度尺寸,所述连接配线宽度尺寸是与该连接配线延伸的方向及所述厚度方向正交的方向的尺寸,所述第2端子部焊盘宽度尺寸是与该第2端子部焊盘延伸的方向及所述厚度方向正交的方向的尺寸。
(附记15)
根据附记14所述的安装构造,其中
所述连接配线宽度尺寸为所述第2端子部焊盘宽度尺寸的2倍以上。
(附记16)
根据附记14或15所述的安装构造,其中
所述连接配线宽度尺寸为0.2mm以上。
(附记17)
根据附记14至16中任一项所述的安装构造,其中
最小距离L4相对于最小距离L3的比率为1/4以下,所述最小距离L3是分别与所述连接配线相邻且隔着该连接配线配置的2个所述第2端子部焊盘的最小距离,所述最小距离L4是该第2端子部焊盘的一个与该连接配线之间的最小距离。
[符号的说明]
A1~A3半导体装置1 第1引脚
110 搭载部
111 搭载部主面
112 搭载部背面
120 第1端子部
121 第1端子部主面
122 第1端子部背面
123 第1端子部端面
130 连结部
131 连结部主面
132 连结部背面
2 第2引脚
210 连接部
211 连接部主面
212 连接部背面
220 第2端子部
221 第2端子部主面
222 第2端子部背面
223 第2端子部端面
3 半导体元件
31 元件主面
32 元件背面
33 电极垫
4 接合线
5 密封树脂
51 树脂主面
52 树脂背面
53 树脂侧面
6 接合材
9 配线衬底
91 搭载部焊盘
92 第1端子部焊盘
93 第2端子部焊盘
94 连接配线
95 第2端子部连接配线
99 焊料
Claims (13)
1.一种安装构造,是具备半导体装置、及安装所述半导体装置的配线衬底的半导体装置的安装构造,
所述半导体装置具备:
半导体元件;
第1引脚,具有沿厚度方向观察时为矩形状且搭载所述半导体元件的搭载部、分别从所述搭载部的4个角延伸的4个连结部、及分别连接于所述各连结部的前端的4个第1端子部;
多个第2引脚,沿所述厚度方向观察时,在相邻的所述第1端子部之间,与所述搭载部的各端缘平行排列且分别各配置多个;以及
密封树脂,将所述第1引脚及所述各第2引脚各覆盖至少一部分;且
所述搭载部具有搭载所述半导体元件的搭载部主面、及在所述厚度方向上朝向与所述搭载部主面相反侧的搭载部背面,
所述各第1端子部的一部分从所述密封树脂露出,
所述连结部具有在所述厚度方向上朝向与所述搭载部背面相同侧的连结部背面,
所述连结部背面从所述密封树脂露出,
所述各第2引脚具有一部分从所述密封树脂露出的第2端子部、及从所述第2端子部朝向所述搭载部延伸的连接部,
所述连结部的连结部宽度尺寸大于与该连结部相邻的所述第2引脚的所述连接部的连接部宽度尺寸,所述连结部宽度尺寸是与该连结部延伸的方向及所述厚度方向正交的方向的尺寸,所述连接部宽度尺寸是与该连接部延伸的方向及所述厚度方向正交的方向的尺寸,
所述配线衬底具备:
搭载部焊盘,接合所述搭载部背面;
4个第1端子部焊盘,分别接合所述各第1端子部;
多个第2端子部焊盘,分别接合所述各第2端子部;及
4个连接配线,分别接合所述各连结部背面,并且分别连接于所述搭载部焊盘及所述各第1端子部焊盘;
所述各第2端子部焊盘朝向所述搭载部焊盘延伸;且
所述连接配线的连接配线宽度尺寸大于与该连接配线相邻的所述第2端子部焊盘的第2端子部焊盘宽度尺寸的2倍以上,所述连接配线宽度尺寸是与该连接配线延伸的方向及所述厚度方向正交的方向的尺寸,所述第2端子部焊盘宽度尺寸是与该第2端子部焊盘延伸的方向及所述厚度方向正交的方向的尺寸;
最小距离L4相对于最小距离L3的比率为1/4以下,所述最小距离L3是分别与所述连接配线相邻且隔着该连接配线配置的2个所述第2端子部焊盘的最小距离,所述最小距离L4是该第2端子部焊盘中的一个与该连接配线之间的最小距离。
2.根据权利要求1所述的安装构造,其中
所述多个第2端子部焊盘任一个都为相同形状。
3.根据权利要求1所述的安装构造,其中
所述连结部宽度尺寸为所述连接部宽度尺寸的2倍以上。
4.根据权利要求1或3所述的安装构造,其中
所述连结部宽度尺寸为0.2mm以上。
5.根据权利要求1或3所述的安装构造,其中
最小距离L2相对于最小距离L1的比率为1/4以下,所述最小距离L1是分别与所述连结部相邻且隔着该连结部配置的2个所述第2引脚间的最小距离,所述最小距离L2是该第2引脚中的一个与该连结部之间的最小距离。
6.根据权利要求1或3所述的安装构造,其中
所述搭载部背面从所述密封树脂露出。
7.根据权利要求1所述的安装构造,其中
所述连结部具有在所述厚度方向上朝向与所述搭载部主面相同侧的连结部主面,且
所述搭载部主面与所述连结部主面为同一平面。
8.根据权利要求1所述的安装构造,其中
所述第1端子部具有在所述厚度方向上朝向与所述搭载部背面相同侧的第1端子部背面,且
所述第1端子部背面从所述密封树脂露出。
9.根据权利要求8所述的安装构造,其中
所述第1端子部还具有与所述第1端子部背面正交且从所述密封树脂露出的第1端子部端面。
10.根据权利要求1所述的安装构造,其中
所述连结部由所述密封树脂覆盖。
11.根据权利要求1所述的安装构造,其中
所述各第2引脚的所述连接部延伸的方向相对于所述第2端子部延伸的方向倾斜,且越靠近所述连结部的所述第2引脚,该倾斜越大。
12.根据权利要求1所述的安装构造,其中
与所述连结部相邻的所述第2引脚的所述连接部延伸的方向与该连结部延伸的方向大致平行。
13.根据权利要求1所述的安装构造,其中
所述连接配线宽度尺寸为0.2mm以上。
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CN109524380A (zh) * | 2017-09-20 | 2019-03-26 | 大口电材株式会社 | 半导体元件搭载用基板及其制造方法 |
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TWI338358B (en) | 2003-11-19 | 2011-03-01 | Rohm Co Ltd | Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same |
JP3805767B2 (ja) | 2003-11-19 | 2006-08-09 | ローム株式会社 | リードフレームの製造方法およびそれを用いた半導体装置の製造方法 |
JP2008258411A (ja) * | 2007-04-05 | 2008-10-23 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
WO2009081494A1 (ja) * | 2007-12-26 | 2009-07-02 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
JP2013021052A (ja) | 2011-07-08 | 2013-01-31 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP5798021B2 (ja) * | 2011-12-01 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP2004228260A (ja) * | 2003-01-22 | 2004-08-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006287073A (ja) * | 2005-04-04 | 2006-10-19 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
CN109524380A (zh) * | 2017-09-20 | 2019-03-26 | 大口电材株式会社 | 半导体元件搭载用基板及其制造方法 |
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US12087675B2 (en) | 2024-09-10 |
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