JP2021002587A - 半導体装置、および、半導体装置の実装構造 - Google Patents
半導体装置、および、半導体装置の実装構造 Download PDFInfo
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- JP2021002587A JP2021002587A JP2019115522A JP2019115522A JP2021002587A JP 2021002587 A JP2021002587 A JP 2021002587A JP 2019115522 A JP2019115522 A JP 2019115522A JP 2019115522 A JP2019115522 A JP 2019115522A JP 2021002587 A JP2021002587 A JP 2021002587A
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 179
- 229920005989 resin Polymers 0.000 claims abstract description 73
- 239000011347 resin Substances 0.000 claims abstract description 73
- 238000007789 sealing Methods 0.000 claims abstract description 48
- 235000014676 Phragmites communis Nutrition 0.000 claims description 21
- 244000089486 Phragmites australis subsp australis Species 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000007747 plating Methods 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 244000273256 Phragmites communis Species 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-AKLPVKDBSA-N lead-210 Chemical compound [210Pb] WABPQHHGFIMREM-AKLPVKDBSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
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Abstract
Description
図1〜図6に基づき、本開示の第1実施形態にかかる半導体装置A1について説明する。半導体装置A1は、第1リード1、第2リード2、半導体素子3、ボンディングワイヤ4、および封止樹脂5を備えている。半導体装置A1は、いわゆるQFN(Quad Flat Non-leaded package)タイプのパッケージである。
図13および図14に基づき、本開示の第2実施形態にかかる半導体装置A2について説明する。これらの図において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。
図15および図16に基づき、本開示の第3実施形態にかかる半導体装置A3について説明する。これらの図において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。
半導体素子と、
厚さ方向視矩形状であり、かつ、前記半導体素子が搭載される搭載部、前記搭載部の4個の角からそれぞれ延びる4個の連結部、および、前記各連結部の先端にそれぞれ接続する4個の第1端子部を有する第1リードと、
前記厚さ方向視において、隣り合う前記第1端子部の間で、前記搭載部の各端縁に平行に並んでそれぞれ複数ずつ配置されている複数の第2リードと、
前記第1リードおよび前記各第2リードの少なくとも一部ずつを覆う封止樹脂と、
を備える半導体装置であって、
前記各第1端子部の一部は、前記封止樹脂から露出しており、
前記各第2リードは、前記封止樹脂から一部が露出する第2端子部と、前記第2端子部から前記搭載部に向かって延びる接続部とを有し、
前記連結部の、当該連結部が延びる方向および前記厚さ方向に直交する方向の寸法である連結部幅寸法は、当該連結部に隣接する前記第2リードの前記接続部の、当該接続部が延びる方向および前記厚さ方向に直交する方向の寸法である接続部幅寸法より大きい、
半導体装置。
〔付記2〕
前記連結部幅寸法は、前記接続部幅寸法の2倍以上である、
付記1に記載の半導体装置。
〔付記3〕
前記連結部幅寸法は、0.2mm以上である、
付記1または2に記載の半導体装置。
〔付記4〕
前記連結部にそれぞれ隣接し、かつ、当該連結部を挟んで配置される2個の前記第2リード間の最小距離L1に対する、当該第2リードの一方と当該連結部との間の最小距離L2の割合は、1/4以下である、
付記1ないし3のいずれかに記載の半導体装置。
〔付記5〕
前記搭載部は、前記半導体素子が搭載される搭載部主面と、前記厚さ方向において前記搭載部主面とは反対側を向く搭載部裏面とを有し、
前記搭載部裏面は前記封止樹脂から露出している、
付記1ないし4のいずれかに記載の半導体装置。
〔付記6〕
前記連結部は、前記厚さ方向において、前記搭載部主面と同じ側を向く連結部主面を有し、
前記搭載部主面と前記連結部主面とは面一である、
付記5に記載の半導体装置。
〔付記7〕
前記第1端子部は、前記厚さ方向において、前記搭載部裏面と同じ側を向く第1端子部裏面を有し、
前記第1端子部裏面は前記封止樹脂から露出している、
付記5または6に記載の半導体装置。
〔付記8〕
前記第1端子部は、前記第1端子部裏面に直交し、かつ、前記封止樹脂から露出する第1端子部端面をさらに有する、
付記7に記載の半導体装置。
〔付記9〕
前記連結部は、前記封止樹脂に覆われている、
付記5ないし8のいずれかに記載の半導体装置。
〔付記10〕
前記連結部は、前記厚さ方向において、前記搭載部裏面と同じ側を向く連結部裏面を有し、
前記連結部裏面は、前記封止樹脂から露出している、
付記5ないし9のいずれかに記載の半導体装置。
〔付記11〕
前記各第2リードの前記接続部が延びる方向は、前記第2端子部が延びる方向に対して傾斜しており、前記連結部に近い前記第2リードほど、当該傾斜が大きい、
付記5ないし10のいずれかに記載の半導体装置。
〔付記12〕
前記連結部に隣接する前記第2リードの前記接続部が延びる方向は、当該連結部が延びる方向と略平行である、
付記5ないし11のいずれかに記載の半導体装置。
〔付記13〕
付記5ないし12のいずれかに記載の半導体装置と、前記半導体装置が実装される配線基板と、を備える半導体装置の実装構造であって、
前記配線基板は、
前記搭載部裏面が接合される搭載部ランドと、
前記各第1端子部がそれぞれ接合される4個の第1端子部ランドと、
前記各第2端子部がそれぞれ接合される複数の第2端子部ランドと、
前記搭載部ランドと前記各第1端子部ランドとにそれぞれ接続する4個の接続配線と、
を備えている、
実装構造。
〔付記14〕
前記各第2端子部ランドは、前記搭載部ランドに向かって延びており、
前記接続配線の、当該接続配線が延びる方向および前記厚さ方向に直交する方向の寸法である接続配線幅寸法は、当該接続配線に隣接する前記第2端子部ランドの、当該第2端子部ランドが延びる方向および前記厚さ方向に直交する方向の寸法である第2端子部ランド幅寸法より大きい、
付記13に記載の実装構造。
〔付記15〕
前記接続配線幅寸法は、前記第2端子部ランド幅寸法の2倍以上である、
付記14に記載の実装構造。
〔付記16〕
前記接続配線幅寸法は、0.2mm以上である、
付記14または15に記載の実装構造。
〔付記17〕
前記接続配線にそれぞれ隣接し、かつ、当該接続配線を挟んで配置される2個の前記第2端子部ランドの最小距離L3に対する、当該第2端子部ランドの一方と当該接続配線の間の最小距離L4の割合は、1/4以下である、
付記14ないし16のいずれかに記載の実装構造。
1 :第1リード
110 :搭載部
111 :搭載部主面
112 :搭載部裏面
120 :第1端子部
121 :第1端子部主面
122 :第1端子部裏面
123 :第1端子部端面
130 :連結部
131 :連結部主面
132 :連結部裏面
2 :第2リード
210 :接続部
211 :接続部主面
212 :接続部裏面
220 :第2端子部
221 :第2端子部主面
222 :第2端子部裏面
223 :第2端子部端面
3 :半導体素子
31 :素子主面
32 :素子裏面
33 :電極パッド
4 :ボンディングワイヤ
5 :封止樹脂
51 :樹脂主面
52 :樹脂裏面
53 :樹脂側面
6 :接合材
9 :配線基板
91 :搭載部ランド
92 :第1端子部ランド
93 :第2端子部ランド
94 :接続配線
95 :第2端子部接続配線
99 :はんだ
Claims (17)
- 半導体素子と、
厚さ方向視矩形状であり、かつ、前記半導体素子が搭載される搭載部、前記搭載部の4個の角からそれぞれ延びる4個の連結部、および、前記各連結部の先端にそれぞれ接続する4個の第1端子部を有する第1リードと、
前記厚さ方向視において、隣り合う前記第1端子部の間で、前記搭載部の各端縁に平行に並んでそれぞれ複数ずつ配置されている複数の第2リードと、
前記第1リードおよび前記各第2リードの少なくとも一部ずつを覆う封止樹脂と、
を備える半導体装置であって、
前記各第1端子部の一部は、前記封止樹脂から露出しており、
前記各第2リードは、前記封止樹脂から一部が露出する第2端子部と、前記第2端子部から前記搭載部に向かって延びる接続部とを有し、
前記連結部の、当該連結部が延びる方向および前記厚さ方向に直交する方向の寸法である連結部幅寸法は、当該連結部に隣接する前記第2リードの前記接続部の、当該接続部が延びる方向および前記厚さ方向に直交する方向の寸法である接続部幅寸法より大きい、
半導体装置。 - 前記連結部幅寸法は、前記接続部幅寸法の2倍以上である、
請求項1に記載の半導体装置。 - 前記連結部幅寸法は、0.2mm以上である、
請求項1または2に記載の半導体装置。 - 前記連結部にそれぞれ隣接し、かつ、当該連結部を挟んで配置される2個の前記第2リード間の最小距離L1に対する、当該第2リードの一方と当該連結部との間の最小距離L2の割合は、1/4以下である、
請求項1ないし3のいずれかに記載の半導体装置。 - 前記搭載部は、前記半導体素子が搭載される搭載部主面と、前記厚さ方向において前記搭載部主面とは反対側を向く搭載部裏面とを有し、
前記搭載部裏面は前記封止樹脂から露出している、
請求項1ないし4のいずれかに記載の半導体装置。 - 前記連結部は、前記厚さ方向において、前記搭載部主面と同じ側を向く連結部主面を有し、
前記搭載部主面と前記連結部主面とは面一である、
請求項5に記載の半導体装置。 - 前記第1端子部は、前記厚さ方向において、前記搭載部裏面と同じ側を向く第1端子部裏面を有し、
前記第1端子部裏面は前記封止樹脂から露出している、
請求項5または6に記載の半導体装置。 - 前記第1端子部は、前記第1端子部裏面に直交し、かつ、前記封止樹脂から露出する第1端子部端面をさらに有する、
請求項7に記載の半導体装置。 - 前記連結部は、前記封止樹脂に覆われている、
請求項5ないし8のいずれかに記載の半導体装置。 - 前記連結部は、前記厚さ方向において、前記搭載部裏面と同じ側を向く連結部裏面を有し、
前記連結部裏面は、前記封止樹脂から露出している、
請求項5ないし9のいずれかに記載の半導体装置。 - 前記各第2リードの前記接続部が延びる方向は、前記第2端子部が延びる方向に対して傾斜しており、前記連結部に近い前記第2リードほど、当該傾斜が大きい、
請求項5ないし10のいずれかに記載の半導体装置。 - 前記連結部に隣接する前記第2リードの前記接続部が延びる方向は、当該連結部が延びる方向と略平行である、
請求項5ないし11のいずれかに記載の半導体装置。 - 請求項5ないし12のいずれかに記載の半導体装置と、前記半導体装置が実装される配線基板と、を備える半導体装置の実装構造であって、
前記配線基板は、
前記搭載部裏面が接合される搭載部ランドと、
前記各第1端子部がそれぞれ接合される4個の第1端子部ランドと、
前記各第2端子部がそれぞれ接合される複数の第2端子部ランドと、
前記搭載部ランドと前記各第1端子部ランドとにそれぞれ接続する4個の接続配線と、
を備えている、実装構造。 - 前記各第2端子部ランドは、前記搭載部ランドに向かって延びており、
前記接続配線の、当該接続配線が延びる方向および前記厚さ方向に直交する方向の寸法である接続配線幅寸法は、当該接続配線に隣接する前記第2端子部ランドの、当該第2端子部ランドが延びる方向および前記厚さ方向に直交する方向の寸法である第2端子部ランド幅寸法より大きい、
請求項13に記載の実装構造。 - 前記接続配線幅寸法は、前記第2端子部ランド幅寸法の2倍以上である、
請求項14に記載の実装構造。 - 前記接続配線幅寸法は、0.2mm以上である、
請求項14または15に記載の実装構造。 - 前記接続配線にそれぞれ隣接し、かつ、当該接続配線を挟んで配置される2個の前記第2端子部ランドの最小距離L3に対する、当該第2端子部ランドの一方と当該接続配線の間の最小距離L4の割合は、1/4以下である、
請求項14ないし16のいずれかに記載の実装構造。
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