KR970054270A - Soi기판의 제조방법 - Google Patents

Soi기판의 제조방법 Download PDF

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KR970054270A
KR970054270A KR1019960064571A KR19960064571A KR970054270A KR 970054270 A KR970054270 A KR 970054270A KR 1019960064571 A KR1019960064571 A KR 1019960064571A KR 19960064571 A KR19960064571 A KR 19960064571A KR 970054270 A KR970054270 A KR 970054270A
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single crystal
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타다지 아토지
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미타라이 후지오
캐논 가부시기가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

SOI기판의 제조방법은, 다공성Si영역위의 비다공성Si영역을 효율적으로 제거하고, 또한 유리기판을 필연적으로 에칭하여야 하는 문제와 상대적으로 두꺼운 다공성Si영역을 필요로하는 문제를 해결한다.
SOI기판의 제조방법은, 제1비다공성단결정Si영역(100)위에 비다공성단결정Si영역(101)을 형성하기 위하여 단결정Si기판의 표면층을 다공화하는 단계와, 다공성단결정Si영역의 표면의 상부에 제2비다공성단결정Si영역(102)을 형성하는 단계와, 상기 제2비다공성단결정Si영역의 표면에 절연영역(103)을 개재하여 지지기판(110)을 접착하는 단계와, 제1비다공성단결정Si영역(100)을 제거하는 단계와, 다공성단결정Si영역(101)을 제거하는 단계를 구비한 SOI기판의 제조방법에 있어서, 제1비다공성단결정Si영역(100)을 제거하는 단계는, 비다공성단결정Si영역(100)의 에칭레이트가 다공성단결정Si영역(101)의 에칭레이트보다 큰 드라이에칭을 행하는 단계를 포함하는 것을 특징으로 한다.

Description

SOI기판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(a)도, 제1(b)도, 제1(c)도, 제1(d)도, 제1(e)도는 본 발명의 실시예와 제1, 2예의 공정을 개략적으로 설명하기 위한 단면도.

Claims (7)

  1. 제1비다공성단결정Si영역위에 다공성단결정Si영역을 형성하기 위하여 단결정Si 기판의 표면층을 다공화하는 단계와; 상기 다공성단결정Si영역의 표면위에 제2비다공성단결정Si영역을 형성하는 단계와; 절연영역을 개재하여 지지기판을 상기 제2비다공성단결정Si영역의 표면에 접착하는 단계와; 상기 제1비다공성단결정Si영역을 제거하는 단계와; 상기 다공성단결정Si영역을 제거하는 단계를 구비한 SOI기판의 제조방법에 있어서, 상기 제1비다공성단결정Si영역을 제거하는 상기 단계는, 비다공성단결정Si영역의 에칭레이트가 다공성단결정Si영역의 에칭레이트보다 큰 드라이에칭을 행하는 단계로 포함하는 것을 특징으로 하는 SOI기판의 제조방법.
  2. 제1항에 있어서, 상기 제1비다공성단결정Si영역을 제거하는 상기 단계는, 드라이에칭을 행하는 상기 단계전에, 그라인더에 의해 상기 제1비다공성단결정Si영역을 부분적으로 그라인딩하는 단계를 포함하는 것을 특징으로 하는 SOI기판의 제조방법.
  3. 제1항에 있어서, 활성화이온종(activated ion species)이 전기에너지나 광에너지에 의한 이온화에 의해 형성되고 상기 활성화이온종이 기판면에 수직인 방향으로 가속화되고 또한 상기 기판면에서 반응이 발생하는 방식으로 상기 드라이에칭에 행해지는 것을 특징으로 하는 SOI기판의 제조방법.
  4. 제3항에 있어서, 상기 기판위에 평행판전극을 설치하고 상기 평행판전극과 상기 기판사이에 셀프바이어스의 변경을 관찰함으로써, 다공성단결정Si영역이 상기 드라이에칭에 의해 표면전체에 대해서 노출되는 에칭의 종료점을 결정하는 것을 특징으로 하는 SOI기판의 제조방법.
  5. 제1항에 있어서, 상기 다공성단결정Si영역을 제거하는 상기 공정은, 다공성단결정Si영역의 에칭레이트가 비다공성단결정Si영역의 에칭레이트보다큰 웨트에칭에 의해 행해지는 것을 특징으로 하는 SOI기판의 제조방법.
  6. 제1항에 있어서, 상기 다공성단결정Si영역을 제거하는 상기 공정은, 다공성단결정Si영역의 에칭레이트가 비다공성단결정Si영역의 에칭레이트보다 큰 드라이에칭에 의해 행해지는 것을 특징으로 하는 SOI기판의 제조방법.
  7. 제6항에 있어서, 다공성단결정Si영역의 에칭레이트는 비다공성단결정Si영역의 에칭레이트보다 큰 상기 드라이에칭은, 적어도 전기에너지나 광에너지에 의해 분해로부터 초래되는 활성화라디컬이 다공영역의 구멍에 침투하여 내부쪽으로부터 다공영역을 에칭하는 방식으로, 행해지는 것을 특징으로 하는 SOI기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960064571A 1995-12-12 1996-12-12 Soi기판의 제조방법 KR100236689B1 (ko)

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JP95-322921 1995-12-12
JP32292195 1995-12-12
JP96-325105 1996-12-05
JP32510596A JP3250721B2 (ja) 1995-12-12 1996-12-05 Ｓｏｉ基板の製造方法

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EP (1) EP0779650B1 (ko)
JP (1) JP3250721B2 (ko)
KR (1) KR100236689B1 (ko)
CN (1) CN1076862C (ko)
CA (1) CA2192631C (ko)
DE (1) DE69629094T2 (ko)
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EP0779650B1 (en) 2003-07-16
EP0779650A3 (en) 1997-07-02
CA2192631C (en) 2000-08-29
SG71006A1 (en) 2000-03-21
CA2192631A1 (en) 1997-06-13
JP3250721B2 (ja) 2002-01-28
DE69629094D1 (de) 2003-08-21
CN1076862C (zh) 2001-12-26
US6103009A (en) 2000-08-15
EP0779650A2 (en) 1997-06-18
JPH09223782A (ja) 1997-08-26
CN1155755A (zh) 1997-07-30
KR100236689B1 (ko) 2000-01-15
DE69629094T2 (de) 2004-02-19

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