KR960043300A - 플래쉬 이이피롬(flash eeprom)셀, 그 제조방법, 프로그램 및 독출방법 - Google Patents

플래쉬 이이피롬(flash eeprom)셀, 그 제조방법, 프로그램 및 독출방법 Download PDF

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KR960043300A
KR960043300A KR1019950012040A KR19950012040A KR960043300A KR 960043300 A KR960043300 A KR 960043300A KR 1019950012040 A KR1019950012040 A KR 1019950012040A KR 19950012040 A KR19950012040 A KR 19950012040A KR 960043300 A KR960043300 A KR 960043300A
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control gate
source
drain
floating gates
flash
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KR1019950012040A
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KR100187656B1 (ko
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송복남
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김주용
현대전자산업 주식회사
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Priority to KR1019950012040A priority Critical patent/KR100187656B1/ko
Priority to US08/644,211 priority patent/US5812449A/en
Priority to GB9928015A priority patent/GB2342228B/en
Priority to GB9609979A priority patent/GB2300969B/en
Priority to JP8118037A priority patent/JP2828951B2/ja
Priority to CNB961100192A priority patent/CN1134789C/zh
Publication of KR960043300A publication Critical patent/KR960043300A/ko
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Publication of KR100187656B1 publication Critical patent/KR100187656B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5612—Multilevel memory cell with more than one floating gate

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Abstract

본 발명은 플래쉬 이이피롬(FLASH EEPROM)셀, 그 제조방법, 프로그램 및 독출방법에 관한 것으로, 4진 정보를 프로그램 및 독출할 수 있는 메모리 셀을 구현하기 위하여 채널(Channel)영역 상부에 두개의 플로팅게이트(Floating Gate)을 형성하고, 그 두개의 플로팅게이트 각각의 프로그램 및 소거 여부에 따라 4진 정보의 출력을 얻을 수 있도록 하므로써 대용량의 메모리 소자를 구현할 수 있도록 한 플래쉬 이이피롬 셀, 그 제조방법, 프로그램 및 독출방법에 관한 것이다.

Description

플래쉬 이이피롬(FLASH EEPROM)셀, 그 제조방법, 프로그램 및 독출방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A 내지 제1E도는 본 발명에 따른 플래쉬 이이피롬 셀의 제조방법을 설명하기 위한 소자의 단면도, 제2A 내지 제2D도는 본 발명에 따른 플래쉬 이이피롬 셀의 프로그램 동작을 설명하기 위한 동작상태도, 제3A 내지 제3D도는 제2A 내지 제2D도를 설명하기 위한 개념도.

Claims (14)

  1. 플래쉬 이이피롬 셀에 있어서, 서로 수평으로 인접되며 터널산화막에 의해 하부의 실리콘기판과 전기적으로 분리되는 제1 및 제2플로팅게이트와, 상기 제1 및 제2플로팅게이트를 포함하는 상부면에 형성되는 유전체막과, 상기 유전체막 상부에 형성되며 상기 유전체막에 의해 상기 제1 및 제2플로팅게이트와 전기적으로 분리되는 콘트롤게이트와, 상기 실리콘기판에 형성되며 상기 제1 및 제2플로팅게이트 각각의 외측부와 일부 중첩되도록 형성되는 소오스 및 드레인으로 이루어진 것을 특징으로 하는 플래쉬 이이피롬 셀.
  2. 제1항에 있어서, 상기 유전체막은 산화막-질화막-산화막으로 이루어진 것을 특징으로 하는 플래쉬 이이피롬 셀.
  3. 플래쉬 이이피롬 셀의 제조방법에 있어서, 실리콘기판상에 터널산화막 및 제1폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 플로팅게이트전극용 마스크를 이용한 사진 및 식각공정으로 상기 제1폴리실리콘층을 패터닝하여 제1 및 제2플로팅게이트를 각각 형성하는 단계와, 상기 단계로부터 전체면에 감광막을 도포한 후 상기 제1 및 제2플로팅게이트의 상부에만 감광막이 잔류되도록 패터닝하고 노출된 실리콘기판에 불순물이온을 주입하여 소오스 및 드레인을 형성하는 단계와, 상기 단계로부터 전체상부면에 유전체막 및 제2폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 콘트롤게이트전극용 마스크를 이용한 사진 및 시각공정으로 상기 제2폴리실리콘층 및 유전체막을 순차적으로 패터닝하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 이이피롬 셀의 제조방법.
  4. 제3항에 있어서, 상기 터널산화막은 80 내지 120Å의 두께로 형성되는 것을 특징으로 하는 플래쉬 이이피롬 셀의 제조방법.
  5. 제3항에 있어서, 상기 제1 및 제2플로팅게이트는 수평으로 서로 인접되게 형성되는 것을 특징으로 하는 플래쉬 이이피롬 셀의 제조방법.
  6. 제3항에 있어서, 상기 유전체막은 산화막-질화막-산화막이 순차적으로 형성된 것을 특징으로 하는 플래쉬 이이피롬 셀의 제조방법.
  7. 제1 및 제2플로팅게이트에 핫 일렉트론이 주입되도록 콘트롤게이트, 소오스 및 드레인에 바이어스 전압을 인가한 후 상기 콘트롤게이트, 소오스 및 드레인에 인가되는 바이어스 전압의 조건에 따라 상기 제1 및 제2플로팅게이트에 주입된 핫 일렉트론을 선택적으로 소거시켜 4진 정보가 프로그램되도록 하는 것을 특징으로 하는 플래쉬 이이피롬 셀 프로그램방법.
  8. 제7항에 있어서, 상기 제1 및 제2플로팅게이트로 핫 일렉트론을 주입시키기 위해 상기 콘트롤게이트에 인가하는 전압은 드레인에 인가되는 전압보다 높게 하고 소오스에는 접지전위가 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 프로그램방법.
  9. 제7항에 있어서, 상기 제2플로팅게이트에 주입된 핫 일렉트론을 방전시키기 위해 상기 콘트롤게이트는 접지전위가 되게 하고 소오스는 플로트시키는 한편 드레인에는 상기 콘트롤게이트에 인가되는 전압보다 높은 전압이 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 프로그램방법.
  10. 제7항에 있어서, 상기 제1플로팅게이트에 주입된 핫 일렉트론을 방전시키기 위해 상기 콘트롤게이트는 접지전위가 되게 하고 드레인을 플로트시키는 한편 소오스에는 상기 콘트롤게이트에 인가되는 전압보다 높은 전압이 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 프로그램방법.
  11. 제7항에 있어서, 상기 제1 및 제2플로팅게이트에 주입한 핫 일렉트론을 방전시키기 위해 상기 콘트롤게이트는 접지전위가 되게 하고 소오스 및 드레인에는 상기 콘트롤게이트에 인가되는 전압보다 높되 동일한 크기의 전압이 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 프로그램방법.
  12. 제1 및 제2플로팅게이트에 선택적으로 주입된 핫 일렉트론에 의해 프로그램된 4진 정보를 독출하기 위하여 순방향 독출 및 역방향 독출을 각각 실시한 후 드레인 및 소오스전류의 유무에 따라 저장된 정보가 독출되도록 하는 것을 특징으로 하는 플래쉬 이이피롬 셀 독출방법.
  13. 제12항에 있어서, 상기 순방향 독출시 소오스는 접지전위가 되게 하고 콘트롤게이트에는 드레인에 인가되는 전압보다 높은 전압이 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 독출방법.
  14. 제12항에 있어서, 상기 역방향 독출시 드레인은 접지전위가 되게 하고 콘트롤게이트에는 소오스에 인가되는 전압보다 높은 전압이 인가되도록 한 것을 특징으로 하는 플래쉬 이이피롬 셀 독출방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950012040A 1995-05-16 1995-05-16 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법 KR100187656B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019950012040A KR100187656B1 (ko) 1995-05-16 1995-05-16 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법
US08/644,211 US5812449A (en) 1995-05-16 1996-05-10 Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same
GB9928015A GB2342228B (en) 1995-05-16 1996-05-13 Method of programming a flash eeprom cell
GB9609979A GB2300969B (en) 1995-05-16 1996-05-13 Method of reading a flash eeprom cell
JP8118037A JP2828951B2 (ja) 1995-05-16 1996-05-13 フラッシュｅｅｐｒｏｍの製造方法
CNB961100192A CN1134789C (zh) 1995-05-16 1996-05-16 快速eeprom单元及其制造方法、编程方法和读出方法

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KR1019950012040A KR100187656B1 (ko) 1995-05-16 1995-05-16 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법

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KR960043300A true KR960043300A (ko) 1996-12-23
KR100187656B1 KR100187656B1 (ko) 1999-06-01

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CN1159059A (zh) 1997-09-10
US5812449A (en) 1998-09-22
GB2300969B (en) 2000-05-31
JPH09120998A (ja) 1997-05-06
KR100187656B1 (ko) 1999-06-01
JP2828951B2 (ja) 1998-11-25
CN1134789C (zh) 2004-01-14
GB2300969A (en) 1996-11-20

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