GB2342228A - Method of programming an EEPROM having two floating gates - Google Patents
Method of programming an EEPROM having two floating gates Download PDFInfo
- Publication number
- GB2342228A GB2342228A GB9928015A GB9928015A GB2342228A GB 2342228 A GB2342228 A GB 2342228A GB 9928015 A GB9928015 A GB 9928015A GB 9928015 A GB9928015 A GB 9928015A GB 2342228 A GB2342228 A GB 2342228A
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- source
- drain
- floating gates
- control gate
- information
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- 238000000034 method Methods 0.000 title claims description 17
- 239000002784 hot electron Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000012544 monitoring process Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/561—Multilevel memory cell aspects
- G11C2211/5612—Multilevel memory cell with more than one floating gate
Abstract
The EEPROM is programmed by biasing control gate 8A and source and drain regions 5,6 so that floating gates 3A and 3B are charged by hot electron injection to provide a first memory state. Additional memory states are provided by biasing the control and source/drain regions so that the floating gates are selectively discharged. The device has four memory states with one bit of information being stored on each floating gate. The device is read by applying forward and reverse bias across the source/drain region in sequence and monitoring the output current.
Description
2342228 FLASH EEPROM CELL, METHOD OF MANUFACTURING THE SAME, METHOD OF
PROGRAMMING AND METHOD OF READING THE SAME The present invention relates to a flash EEPROM cell, a method of manufacturing the same, and a method of programming and reading the same and, more particularly, to a flash EEPROM cell constructed in such a way that two floating gates are formed on top of a channel region and an output of 4-numeration information is obtained depending on the program or erasure of each of the two floating gates.
In general, the demand for electrically erasable programmable read only memory(EEPROM) device having both the functions of electrically programming and erasing is increasing due to its inherent advantages. Since this EEPROM device programs or erases only binary information, that is, 1,011 or 'till, in one cell, the amount of information that can be presented by one byte (eight (8) cells) is 256 (=21) However, if a cell has 4-numeration information, that is, 11011, 11111, 11211 or 11311, the amount of information of one byte is 65, 536 (=48) The amount of information is 256 times more than that of a binary cell. Therefore, it is possible to implement a memory device having a capacity of more than one gigabit.
Therefore, the aim of the present invention is to provide a flash EEPROM cell which can solve the above disadvantage by implementing a flash EEPROM device constructed in such a way that two floating gates are formed on top of a channel region and a storage and output of 4- numeration information is obtained depending on the program or erasure of each of the two floating gates.
A flash EEPROM cell, according to the present invention to accomplish the above described aim, is characterized in that it comprises first and second floating gates horizontally adjacent to each other and electrically separated from a silicon substrate below them by a tunnel oxide film; a dielectric film formed on the top surface including said first and second floating gates; a control gate formed on top of said dielectric film and electrically separated from said first and second floating gates by said dielectric film; and a source and drain formed on said silicon substrate and formed to be partially overlapped by outer portions of said first and second floating gates, respectively.
A method of manufacturing a flash EEPROM cell of a first embodiment is characterized in that it comprises the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate; forming each of the first and second floating gates by patterning said first polysilicon layer; forming a source and drain by implanting impurity ions into the entire region of said silicon substrate excluding said region between said first and second floating gates; sequentially forming a dielectric film and second polysilicon layer on the 2 entire top surface; and forming a control gate by sequentially patterning said second polysilicon layer and dielectric film.
A method of manufacturing a flash EEPROM cell of a second embodiment is characterized in that it comprises the steps of sequentially forming a tunnel oxide film and first polysilicon layer on a silicon substrate; patterning said first polysilicon between a first floating gate and second floating gate; sequentially forming a dielectric film and a second polysilicon layer on the entire top surface; sequentially patterning said second polysilicon layer, dielectric film and first and second floating gates by a photolithography and etching process utilizing a mask for a control gate electrode; and forming a source and drain by implementing impurity ions into said silicon substrate.
A method of programming a flash EEPROM cell is characterized in that 4numeration information is programmed by applying bias voltage to a control gate, source and drain so that hot electrons are injected into the first and second floating gates and, thereafter, by selectively erasing said hot electrons injected into said first and second floating gates depending on the condition of bias voltage applied to said con trol gate, source and drain.
A method of reading a flash EEPROM cell is characterized in that stored information is read depending upon existence of drain and source current after performing a forward read and reverse read to read out 4-numeration information programmed by hot electrons injected selectively into the first and second floating gates.
3 For fuller understanding of the nature and aim of the invention, reference should be had to the following detailed description taken in conjunction with the accompanying drawings in which:
FIGS. 1A through 1E are sectional views to illustrate a method of manufacturing a first embodiment of a flash EEPROM cell according to the present invention; FIGS. 2A through 2D are sectional views to illustrate a method of manufacturing a second embodiment of the flash EEPROM cell according to the present invention; FIGS. 3A through 3D are drawings to illustrate an operation of programming the flash EEPROM cell according to the present invention; FIGS. 4A through 4D are drawings to illustrate the concept of FIGS. 3A through 3D; and FIGS. 5A and 5B are drawings to illustrate an operation of reading the flash EEPROM cell according to the present invention.
Similar reference characters refer to similar parts in the several views of the drawings.
FIGS. 1A through 1E are sectional to illustrate a method of manufacturing a first embodiment of a flash EEPROM cell according to the present invention.
FIG. 1A is a sectional view showing a condition in which a tunnel oxide film 2 is formed to a thickness of 80 to 120A on a silicon substrate 1, and thereafter, a first polysilicon layer 4 3 is formed.
FIG. 1B is a sectional view showing a condition in which the first and second floating gates 3A, 3B, horizontally adjoining are formed by patterning the first polysilicon layer 3 by a photolithography and etching process utilizing a mask (not shown) for a floating gate electrode.
FIG. 1C is a sectional view showing a condition in which a source and drain 5, 6 are formed by coating a photoresist 4 on the entire surface, thereafter, patterning the photoresist 4 so that the photoresist 4 remains on top and between the first and second floating gates 3A, 3B and implanting impurity ions into the exposed silicon substrate 1.
FIG. 1D is a sectional view showing a condition in which a dielectric film 7 and second polysilicon layer 8 are sequentially formed on the entire top surface. The dielectric film 7 has an ONO construction in which an oxide film, nitride film and oxide film are sequentially formed.
FIG. 1E is a sectional view showing a condition for the formation of an EEPROM cell in which the dielectric film 7 and a control gate 8A are formed on the first and second floating gates 3A, 3B by sequentially etching the second polysilicon layer 8 and the dielectric film 7 by the photolithography and etching process utilizing a mask (not shown) for a control gate electrode.
FIGS. 2A through 2D are sectional to illustrate a method of manufacturing a second embodiment of a flash EEPROM cell according to the present invention.
FIG. 2A is a sectional view showing a condition in which a tunnel oxide film 2 is formed to a thickness of 80 to 120A on a silicon substrate 1, and thereafter, a first polysilicon layer 3 is formed.
FIG. 2B is a sectional view showing a condition in which the first polysilicon layer 3 between the first and second floating gates 3A, 3B is patterned by the photolithography and etching process.
FIG. 2C is a sectional view showing a condition in which a dielectric film 7 and second polysilicon layer 8 are sequentially formed on the entire top surface. The dielectric film 7 has an ONO construction in which an oxide film, nitride film and oxide film are sequentially formed.
FIG. 2D is a sectional view showing a condition for the formation of an EEPROM cell in which the dielectric film 7 and a control gate 8A are formed on the fist and second floating gates 3A, 3B by sequentially etching the second polysilicon layer 8, dielectric film 7, and the first and second floating gates 3A, 3B by the photolithography and etching process utilizing a mask (not shown) for a control gate electrode, and by forming a source and drain 5, 6 by implanting impurity ions into the silicon substrate 1.
The flow of current at the time of reading out becomes easy by the effective channel length and effective securing of the required area at the time of tunnelling by forming, as described above, two floating gates 3A, 3B to be horizontally adjoining on the tunnel oxide film 2, which is formed thick so as to enable the tunnelling, and by forming the source and drain 5, 6 on the silicon substrate 1 to sufficiently overlap each outer part of 6 the two floating gates 3A, 3B.
Operations of the flash EEPROM cell, manufactured as described above, for programming and reading out the 4 -numeration information (11011, 11111, 11211 or by utilizing such technological principles, are explained below.
FIGS. 3A through 3D are sectional views showing an operation condition to illustrate the programming operation of the flash EEPROM cell according to the present invention, and the operational condition is given as follows with reference to FIGS. 4A through 4D.
First, to program an information 11011 into the cell, that is, to charge all the floating gates, a high voltage of 12 volts is applied to the control gate 8A, 5 volts is applied to the drain 6, and a ground potential is applied to the source 5, as shown in FIG. 3A. Then, a channel is formed in the silicon substrate 1 below the first and second floating gates 3A, 3B by the high potential applied to the control gate 8A, and a high electric field region is formed in the silicon substrate I between the first and second floating gates 3A, 3B by the voltage applied to the drain 6. At this time, hot electrons 9 are generated by current passing through the high electric field region and a portion of the hot electrons 9 are injected into the first and second floating gates 3A, 3B by a vertical electric field formed by the high potential applied to the control gate 8A. Since the threshold voltage of the drain and source 6, 5 is raised to, for example, about 6 volts, the information 11011 is programmed, as shown in FIG. 4A.
To program an information 11111 into the cell, if the ground 7 potential is applied to the control gate 8A, 12 volts are applied to the drain 6 and the source 5 is floated, as shown in FIG. 3B in the condition shown in FIG. 4A, then the electrons 9 charged in the second floating gate 3B are discharged through the drain 6 by the tunnelling, whereby the threshold voltage of the drain 6 is lowered to, for example, about 2 volts, so that the information 1,111 is programmed, as shown in FIG. 4B.
To program an information 11211 into the cell, if the ground potential is applied to the control gate 8A, 12 volts are applied to the source 5 and the drain 6 is floated, as shown in FIG. 3C in the condition shown in FIG. 4A, then the electrons 9 charged in the second floating gate 3A are discharged through the source 5 by the tunnelling, whereby the threshold voltage of the source 5 is lowered to, for example, about 2 volts, so that the information 11211 is programmed, as shown in FIG. 4C.
To program an information 113" into the cell, if the ground potential is applied to the control gate 8A, and 12 volts are applied to the source and drain 5, 6, then the electrons 9 charged in the first and second floating gates 3A, 3B are discharged through the source and drain 5, 6, respectively, so that the threshold voltage of the source and drain 5, 6 is lowered to, for example, about 2 volts, so that the information is programmed, as shown in FIG. 4D.
As described above, the 4-numeration information can be programmed to a cell by changing the condition of the bias voltage applied to the control gate 8A, source and drain 5, 6, wherein, to prevent interaction between the two floating gates at the time of programming an information, the information 8 11211 or 11311 is programmed after programming the information 11011. Now, a read operation for reading out the 4-numeration information programmed in the cell, as described above, is explained with reference to FIGS. SA and 5B.
Since the 4-numeration information is programmed in one cell, as described above, basically two read operations, that is, forward read and reverse read shall be performed to read out the information. Here, a read operation, for example, in the condition where the information 11211 is programmed, as shown in FIG. 4C, is explained.
To perform the forward read in the condition where the electrons 9 are charged only in the second floating gate 3B, as shown in FIG. 4C, 4 volts are applied to the control gate 8A, 3 volts to the drain 6 and ground potential to the source 5, respectively, as shown in FIG. 5A. Then, a drain current, I., exists since a channel is formed in the silicon substrate 1 below the first floating gate 3A on the side of the source 5 into which the electrons 9 are injected. Also, to perform the reverse read in the condition where the electrons 9 are charged only in the second floating gate 3B, as shown in FIG. 4C, 4 volts are applied to the control gate 8A, 3 volts to the source 5 and ground potential to the drain 6, respectively, as shown in FIG. 5B. At this time, a source current, I., does not exist since a channel is not formed in the silicon substrate 1 below the second f loating gate 3B on the side of the drain 6 into which the electrons 9 are injected. In this way, the stored information is read out depending on the existence of the drain or source current( I. or I.,) after the two read operations are performed.
9 For a reference, the condition of flow of drain and source current at the time of reading out the above described information, 11011, 11111, 11211 or 11311, is shown in a table follow.
Information 1 1 stored in a cell Drain current( D) Source current (I,) at the time of at the time of forward read reverse read 0 None None 1 None Flow 2 Flow None 3 Flow Flow As described above, according to the present invention, since the 4- numeration information can be programmed depending on the program or erasure of each of the two floating gates and the accurate reading of the information is possible by forming two floating gates on top of a channel region, the present invention can be utilized in embodying a flash EEPROM cell of large capacitance. Furthermore, since the information is stored in the floating gate, there is an excellent effect that the information can be permanently stored.
The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principles of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope of the present invention are to be encompassed as further embodiments of the present invention.
Claims (5)
1. A method of programming a flash EEPROM cell, comprising the steps of:
applying bias voltage to a control gate, source and drain so that hot electrons are injected into first and second floating gates; selectively erasing said hot electrons injected into said first and second floating gates depending on the condition of bias voltage applied to said control gate, source and drain so that 4-numeration information is programmed into said flash EEPROM cell.
2. The method of claim 1, wherein said voltage applied to said control gate to inject hot electrons into said first and second floating gates is higher than that applied to said drain, and a ground potential is applied to said source.
3. The method of claim 1, wherein a ground potential is applied to said control gate to discharge hot electrons injected into said second floating gate, said source is floated, and said drain is applied with higher voltage than that applied to said control gate.
4. The method of claim 1, wherein a ground potential is applied to said control gate to discharge hot electrons injected into said first floating gate, said drain is floated, and said source is applied with higher voltage than that applied to said control gate.
11 1
5. The method of claim 1, wherein a ground potential is applied to said control gate to discharge hot electrons injected into said first and second floating gates, and said source and drain are applied with same voltage but higher than that applied to said control gate.
(o A method of programming a flash EEPROM cell substantially as hereinbefore described with reference to Figures 3A to 3D and Figures 4A to 4D of the accompanying drawings.
12
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012040A KR100187656B1 (en) | 1995-05-16 | 1995-05-16 | Method for manufacturing a flash eeprom and the programming method |
| GB9609979A GB2300969B (en) | 1995-05-16 | 1996-05-13 | Method of reading a flash eeprom cell |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9928015D0 GB9928015D0 (en) | 2000-01-26 |
| GB2342228A true GB2342228A (en) | 2000-04-05 |
| GB2342228B GB2342228B (en) | 2000-07-12 |
Family
ID=26309323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9928015A Expired - Fee Related GB2342228B (en) | 1995-05-16 | 1996-05-13 | Method of programming a flash eeprom cell |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2342228B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1226878A2 (en) * | 2001-01-24 | 2002-07-31 | Matsushita Electric Industrial Co., Ltd. | Aligned fine particles, method for producing the same and device using the same |
| CN100359603C (en) * | 2002-07-23 | 2008-01-02 | 旺宏电子股份有限公司 | Method of programming, reading and erasing of non volatile storage with multi stage output current |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0051158A1 (en) * | 1980-10-27 | 1982-05-12 | International Business Machines Corporation | Electrically alterable double dense memory |
| US5143860A (en) * | 1987-12-23 | 1992-09-01 | Texas Instruments Incorporated | High density EPROM fabricaiton method having sidewall floating gates |
| US5159570A (en) * | 1987-12-22 | 1992-10-27 | Texas Instruments Incorporated | Four memory state EEPROM |
-
1996
- 1996-05-13 GB GB9928015A patent/GB2342228B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0051158A1 (en) * | 1980-10-27 | 1982-05-12 | International Business Machines Corporation | Electrically alterable double dense memory |
| US5159570A (en) * | 1987-12-22 | 1992-10-27 | Texas Instruments Incorporated | Four memory state EEPROM |
| US5143860A (en) * | 1987-12-23 | 1992-09-01 | Texas Instruments Incorporated | High density EPROM fabricaiton method having sidewall floating gates |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1226878A2 (en) * | 2001-01-24 | 2002-07-31 | Matsushita Electric Industrial Co., Ltd. | Aligned fine particles, method for producing the same and device using the same |
| EP1226878A3 (en) * | 2001-01-24 | 2003-08-13 | Matsushita Electric Industrial Co., Ltd. | Aligned fine particles, method for producing the same and device using the same |
| US7220482B2 (en) | 2001-01-24 | 2007-05-22 | Matsushita Electric Industrial Co., Ltd. | Aligned fine particles, method for producing the same and device using the same |
| CN100359603C (en) * | 2002-07-23 | 2008-01-02 | 旺宏电子股份有限公司 | Method of programming, reading and erasing of non volatile storage with multi stage output current |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9928015D0 (en) | 2000-01-26 |
| GB2342228B (en) | 2000-07-12 |
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| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20130513 |