CN1159059A - 快速eeprom单元及其制造方法、编程方法和读出方法 - Google Patents

快速eeprom单元及其制造方法、编程方法和读出方法 Download PDF

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CN1159059A
CN1159059A CN96110019A CN96110019A CN1159059A CN 1159059 A CN1159059 A CN 1159059A CN 96110019 A CN96110019 A CN 96110019A CN 96110019 A CN96110019 A CN 96110019A CN 1159059 A CN1159059 A CN 1159059A
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宋福男
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Abstract

本发明涉及一快速EEPROM单元及其制造方法、编程方法和读取方法，特别涉及以这种方式所构成的一快速EEPROM单元，即在一沟道区的顶部形成二个浮动栅以实现一存贮单元并从该存贮单元可对4个数字信息编程和读出，并根据二个浮动栅的每一个的编程和擦除而得到4个数字信息的一输出。

Description

快速EEPROM单元及其制造方法、 编程方法和读出方法
本发明涉及一种快速EEPROM单元及其制造方法、编程方法和读出方法，特别涉及以这样一种方式构成的快速EEPROM单元，即在一沟道区的顶部形成二个浮动栅并且按照这二个浮动栅的每一个的编程或擦除而得到4个数字信息的输出。
对于具有电编程和擦除功能的电可擦除可编程只读存贮器(EEPROM)器件来说，由于它固有的优点使得对它的需求不断增加。因为这种EEPROM器件在一单元中仅是二进制信息(即″0″或″1″)编程或擦除，所以由1字节(8单元)所呈现的信息量可以是256(＝28)。但是，如果一单元具有4个数字信息，即″0″、″1″、″2″或″3″则1字节的信息量为65536(＝48)。这个信息量是一二进制单元信息量的256倍。因此，一具有高于千兆比特容量的存贮器件才有可能实施。
因此，本发明的目的是提供一种可以克服上述缺陷的快速EEPROM单元，它是通过以这样一种方式所构成的一快速EEPROM器件来实现的，即在一沟道区域的顶部形成二个浮动栅并且依据这二个浮动栅的每一个的编程或擦除而获得4个数字信息的存贮和输出。
根据本发明的实现上述目的一快速EEPROM单元，其特征是包括有相互水平地邻接并通过一隧道氧化物膜与一低于它们的硅基片电隔离的第一和第二浮动栅；在包括所述第一和第二浮动栅的顶部表面上形成的一介电膜；在所述介电膜的顶部形成并通过所述介电膜与所述第一和第二浮动栅电隔离的一控制栅；和在所述硅基片上形成分别与所述第一和第二浮动栅的外部部分重叠的一源极和漏极。
第一实施例的制造一快速EEPROM单元的一种方法，其特征包括一在硅基片上顺序形成一隧道氧化物膜和一第一多晶硅层；通过摹制所述第一多晶硅层形成第一和第二浮动栅的每一个；通过将杂质离子掺入除所述第一和第二浮动栅之间的所述区域之外的所述硅基片的整个区域形成一源极和漏极；在该整个顶部表面顺序形成一介电膜和第二多晶硅层；和通过摹制所述第二多晶硅层和介电膜形成一控制栅的各个步骤。
第二实施例的制造一快速EEPROM单元的一方法，其特征是包括有在一硅基片上顺序地形成一隧道氧化物膜和第一多晶硅层；在第一浮动栅和第二浮动栅之间摹制所述第一多晶硅；在该整个顶部表面顺序形成一介电膜和一第二多晶硅层；通过利用一用于控制栅电极的一掩膜的光刻和腐蚀处理顺序地摹制所述第二多晶硅层、  介电膜和第一及第二浮动栅；和通过向所述硅基片掺入杂质离子形成一源极和漏极的各个步骤。
一种对一快速EEPROM编程的方法，其特征是通过向一控制栅、源极和漏极施加偏压从而将热电子注入第一和第二浮动栅，并且通过依据施加到所述控制栅、源极和漏极的偏压的状态有选择地擦除被注入到所述第一和第二浮动栅的所述热电子，因而对4数字信息编程。
一种读取一快速EEPROM单元的方法，其特征是在执行一正向读取和反向读取之后根据漏极和源极电流的存在读取所存贮的信息以读出通过有选择地向第一和第二浮动栅注入热电子而被编程的4读数信息。
参照以下结合附图所作的详细说明，将更全面地理解本发明的本质和目的。
图1A至1E所示的剖视图表明了根据本发明的一种快速EEPROM单元的第一实施例的制造方法；
图2A至2D所示的剖视图表明了根据本发明的一种快速EEPROM单元的第二实施例的制造方法；
图3A至3D是表明根据本发明的对该快速EEPROM单元编程的操作的图；
图4A至4D是表明图3A至3D的概念的图；
图5A至5B是表明根据本发明的读取该快速EEPROM单元的操作的图；
在这些图中，相同的标号表示相同的部分。
图1A至1E是表明根据本发明的EEPROM单元的第一实施例的制造方法的剖视图。
图1A的剖视图表明在一硅基片1上形成厚度为80至120A的一隧道氧化物膜2其后形成一第一多晶硅层3的状态。
图1B的剖视图表明通过利用用于一浮动栅电极的掩模(未示出)进行光刻和腐蚀处理而摹制该第一多晶硅层3形成平行邻接的第一和第二浮动栅3A、3B的状态。
图1C的剖视图表明通过在整个表面上涂覆一光刻胶4，随后摹制该光刻胶4，以便该光刻胶4保留在顶部和第一及第二浮动栅3A、3B之间并向暴露的硅基片1掺入杂质离子以形成源极和漏极5，6的状态。
图1D的剖视图表明在整个顶部表面顺序形成一介电膜7和第二多晶硅层8的状态。该介电膜7具有一ONO结构，在该ONO结构中顺序形成一氧化膜、氮化膜和氧化膜。
图1E的剖视图表明了形成一EEPROM单元的状态，其中通过利用用于一控制栅电极的掩模(未示出)通过光刻和腐蚀处理来顺序腐蚀第二多晶硅层8和介电膜7而在第一和第二浮动栅3A、3B上形成介电膜7和控制栅8。
图2A至2D是表明根据本发明一快速EEPROM单元的第二实施例的制造方法的剖面图。
图2A的剖面图表明在一硅基片1上形成一厚度为80至120的隧道氧化物膜2并随后形成一第一多晶硅层3的状态。
图2B的剖面图表明通过光刻和腐蚀处理在第一和第二浮动栅3A、3B之间摹制第一多晶硅层3的状态。
图2C的剖面图表明在整个顶部表面上顺序形成一介电膜7和第二多晶硅层8的状态。该介电膜7具有一ONO结构，在该ONO结构中顺序地形成一氧化物膜、氮化物膜和氧化物膜。
图2D的剖面图表明用来形成一EEPROM单元的状态，在其中通过利用用于一控制栅电极的掩膜(未示出)进行光刻和腐蚀处理通过顺序地腐蚀第二多晶硅层8、介电膜7和第一及第二浮动栅3A、3B在该第一及第二浮动栅3A、3B上形成介电膜7和控制栅8A，并且通过向该硅基片1中掺入杂质离子而形成源极和漏极5、6。
如上所述，由于在隧道效应的时间该有效的沟道长度和有效的所需区域的保障，由于在隧道氧化物膜2上水平地邻接所形成的二个浮动栅3A、3B是构成最厚的部分，并且由于在该硅基片1上形成的源极和漏极5、6与二个浮动栅3A，3B的每个外侧部分足够地重叠，而使得在读出时该电流的流动变得容易。
如上所述制造的该快速FEPROM单元的用来对4数字信息(″0″、″1″、″2″、或″3″)编程和读取的操作所利用的技术原理如下面所述。
图3A至3D的剖视图所表明的一操作状态说明了根据本发明的快速EEPROM的编程操作状态，并且该操作状态如下所述参照图4A至4D给出。
首先，为了将一信息″0″编程到该单元，即如图3A所示，对所有浮动栅充电，将12V的一高电压加到控制栅8A，将5V电压加到漏极6，和该源极5加上地电位。然后，通过加到控制栅8A的高电位在该第一和第二浮动栅3A、3B下面的硅基片1中形成一沟道，并且通过加到漏极6的电压在第一和第二浮动栅3A、3B之间的硅基片1中形成一高电场区。此时，通过电流流经该高电场区而产生热电子9和通过由加到控制栅8A的高电位所形成的垂直电场热电子的一部分被注入到第一和第二浮动栅3A、3B。如图4A所示，因为该漏极和源极6，5的阈值电压被提高到例如大约6伏，所以信息″0″被编程。
为了将一信息″1″编程到该单元，如处于图4A所示状态的图3B所示，如果将地电位加到控制栅8A，12V电压加到漏极6而源极5是浮动的，随后如图4B所示，在第二浮动栅3B中被充电的电子9通过漏极6由于隧道效应而被放电，因而漏极6的阈值电压降低到例如大约为2V，从而信息″1″被编程。
为了将一信息″2″编程到该单元，如图3C所示，如果将地电位加到控制栅8A，12V电压加到源极5和漏极6被浮动，随后如图4C所示，在图4A所示状态中在第二浮动栅3A被充电的电子9通过源极5由于隧道效应而被放电，因此源极的阈值电压降低至例如大约2V，从而该信息″2″被编程。
为了将一信息″3″编程到该单元，如果将地电位加到控制栅8A和将12V电压加到源极和漏极5、6，然后如图4D所示在第一和第二浮动栅3A、3B中被充电的电子9分别通过该源极和漏极5，6被放电，因而该源极和漏极5、6的阈值电压被降低至例如大约2V，从而该信息″3″被编程。
如上所述，通过改变加到控制栅8A，源极和漏极5，6的偏压的状态可对该单元进行4数字信息的编程，在其中为了防止在对一信息进行编程时在二个浮动栅之间的相互影响，应在对信息″0″编程之后对信息″1″、″2″或″3″编程。
现在结合图5A和5B说明对如上所述的用于读出在该单元中被编程的4数字信息的读取操作。
如上所述因为该4数字信息是在一单元中被编程，所以基本上是二种读取操作方式，即利用正向和反向读取来执行该信息的读出。这里对如图4C所示的例如对信息″2″编程的状态的一读取操作作一说明。
为了在如图4C所示的该电子仅在第二浮动栅3B中被充电的状态下执行正向读取，如图5A所示分别将4伏电压加到控制栅8A，将3伏电压加到漏极6和将地电位加到源极5。因为在源极5的一侧在低于第一浮动栅3A的硅基片1中形成了使被射入电子进入的一沟道，所以存在有一漏极电流ID。另外，为了在图4C所示的该电子仅在第二浮动栅3B中被充电的状态下执行反向读取，如图5B所示分别将4伏电压加到控制栅8A，3伏电压加到源极5和将地电位加到漏极6。这时，因为在漏极6的一侧在低于第二浮动栅3B的硅基片1中没有形成一使被射入电子进入的沟道，所以不存在有一源极电流IS。在这种方式中，在二个读取操作被执行之后根据漏极或源极电流(ID或IS)的出现而读出被存贮信息。作为参考，在下面表中示出了在读出上述信息″0″、″1″、″2″或″3″时漏极和源极电流的流动状态。
在一单元中所存贮的信息 在正向读取时的漏极电流(ID) 在反向读取时的源极电流(IS)
    0     无     无
1 无 流动
    2     流动     无
    3     流动     流动
如上所述，根据本发明，因为根据二个浮动栅的每个的编程和擦除可对4数字信息编程并且通过在一沟道区的顶部形成二个浮动栅可准确读取信息，所以本发明可以被利用在所配置的一大容量的快速EEPROM中。另外，因为该信息被存贮在浮动栅中，所以存在有该信息可被永久存贮的极好的效果。
在上面的说明中，虽然在其中描述了具有一定程度特殊性的最佳实施例，但它仅仅例证性的描述了本发明的一些原则。很明显本发明并不仅限于所披露和描述的最佳实施例。因此，在本发明的范围和精神之内所做的适宜的变化都被作为本发明的进一步的实施例。

Claims (18)

1.一种快速EEPROM单元，包括：
水平地相互邻接并通过隧道氧化物膜与低于它们的硅基片电隔离的第一和第二浮动栅；
在顶部表面上形成包括所述第一和第二浮动栅的一介电膜；
在所述介电膜的顶部形成并通过所述介电膜与所述第一和第二浮动栅电隔离的一控制栅；
在所述硅基片上形成并分别与所述第一和第二浮动栅的外部部分重叠的一源极和漏极。
2.如权利要求1所述的快速EEPROM单元，其中所述介电膜是由一氧化物膜—氮化物膜—氧化物膜顺序形成的。
3.一种制造快速EEPROM单元的方法包括有步骤：
在一硅基片上顺序形成一隧道氧化物膜和一第一多晶硅层；
通过摹制所述第一多晶硅层形成第一和第二浮动栅的每一个；
通过向除第一和第二浮动栅之间的区域之外的所述硅基片的整个区域掺入杂质离子而形成一源极和漏极；
在形成所述源极和漏极之后在整个顶部表面上顺序形成一介电膜和第二多晶硅层；和
通过顺序摹刻所述第二多晶硅层和介电膜形成一控制栅。
4.如权利要求3所述的方法，其中所形成的所述隧道氧化物膜的厚度为80至120。
5.如权利要求3所述的方法，其中所形成的所述第一和第二浮动栅是相互水平地相邻。
6.如权利要求3所述的方法，其中所述介电膜是由一氧化物膜—氮化物膜—氧化物膜形成的。
7.一种制造快速EEPROM单元的方法，包括有步骤：
在一硅基片上顺序形成一隧道氧化物膜和第一多晶硅层；
在第一浮动栅和第二浮动栅之间摹制所述第一多晶硅层；
在摹制所述第一多晶硅之后在整个顶部表面上顺序形成一介电膜和一第二多晶硅层；
通过利用用于一控制栅电极的掩模进行光刻和腐蚀处理顺序摹制所述第二多晶硅层、介电膜和第一及第二浮动栅；和
通过向所述硅基片掺入杂质离子形成一源极和漏极。
8.如权利要求7所述的方法，其中形成的所述隧道氧化物膜的厚度为80至120。
9.如权利要求7所述的方法，其中形成的所述第一和第二浮动栅是相互平行地邻接的。
10.如权利要求7所述的方法，其中所述介电膜是由氧化物膜—氮化物膜—氧化物膜所形成的。
11.一种制造快速EEPROM单元的方法，包括有步骤：
将偏压加到一控制栅、源极和漏极使得热电子被注入第一和第二浮动栅；
根据被加到所述控制栅、源极和漏极的偏压的状态有选择地擦除注入到所述第一和第二浮动栅的所述热电子使得4个数字信息被编程到所述快速EEPROM单元中。
12.如权利要求11所述的方法，其中为了将热电子注入到所述第一和第二浮动栅而加到所述控制栅的电压高于加到所述漏极的电压，并且一地电位加到所述源极。
13.如权利要求11所述的方法，其中一地电位加到所述控制栅以使注入所述第二浮动栅的热电子放电，所述源极是浮动的，和所述漏极加有比加到所述控制栅的电压要高的电压。
14.如权利要求11所述的方法，其中一地电位加到所述控制栅以使注入所述第一浮动栅的热电子放电，所述漏极是浮动的，和所述源极加有比加到所述控制栅的电压要高的电压。
15.如权利要求11所述的方法，其中一地电位加到所述控制栅以使注入所述第一浮动栅和第二浮动栅的热电子放电和所述源极和漏极加有相同但高于加到所述控制栅的电压。
16.一种读取具有一源极、漏极、控制栅、第一和第二浮动栅的快速EEPROM单元的方法，包括有步骤：
在一固定电压加到控制栅的情况下，在所述源极和漏极之间提供一正向偏压；
在一固定电压加到所述控制栅的情况下，在所述源极和漏极之间提供一反向偏压；和
根据漏极和源极电流的存在读出通过有选择地将热电子注入到所述第一和第二浮动栅而被编程的4个数字信息。
17.如权利要求16所述的方法，其中在正向偏置时，所述源极加有地电位，而所述控制栅加有比加到所述漏极的电压要高的电压。
18.如权利要求16所述的方法，其中在反向偏置时，所述漏极加有地电位，而所述控制栅加有比加到所述源极的电压要高的电压。
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