CN1647213A - 动态参考编程的算法 - Google Patents
动态参考编程的算法 Download PDFInfo
- Publication number
- CN1647213A CN1647213A CNA038077426A CN03807742A CN1647213A CN 1647213 A CN1647213 A CN 1647213A CN A038077426 A CNA038077426 A CN A038077426A CN 03807742 A CN03807742 A CN 03807742A CN 1647213 A CN1647213 A CN 1647213A
- Authority
- CN
- China
- Prior art keywords
- unit
- array
- flash memory
- sector
- programmed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000003491 array Methods 0.000 claims abstract description 17
- 230000009977 dual effect Effects 0.000 abstract description 9
- 230000001351 cycling effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 22
- 238000007667 floating Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000006698 induction Effects 0.000 description 4
- 238000001802 infusion Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007430 reference method Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
操作 | 单元 | 栅极 | 位线0 | 位线1 | 批注 |
读取 | C0 | 4.7v | 0v | 1.2v至2v | 新增位 |
读取 | C1 | 4.7v | 1.2v至2v | 0v | 正常位 |
编程 | C0 | Vpp | 5至6v | 0v | 热电子 |
编程 | C1 | Vpp | 0v | 5至6v | 热电子 |
单边擦除 | C0 | -6v | 6v | 0v | 热空穴注入 |
双边擦除 | 所有单元 | -6v | 6v | 6v | 热空穴注入 |
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/119,391 US6690602B1 (en) | 2002-04-08 | 2002-04-08 | Algorithm dynamic reference programming |
US10/119,391 | 2002-04-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1647213A true CN1647213A (zh) | 2005-07-27 |
CN100538897C CN100538897C (zh) | 2009-09-09 |
Family
ID=29248246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038077426A Expired - Lifetime CN100538897C (zh) | 2002-04-08 | 2003-02-14 | 动态参考编程的算法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US6690602B1 (zh) |
JP (1) | JP2005522817A (zh) |
KR (1) | KR100935948B1 (zh) |
CN (1) | CN100538897C (zh) |
AU (1) | AU2003219772A1 (zh) |
DE (1) | DE10392492B4 (zh) |
GB (1) | GB2401971B (zh) |
TW (1) | TWI286754B (zh) |
WO (1) | WO2003088260A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101540199B (zh) * | 2008-03-21 | 2012-07-11 | 旺宏电子股份有限公司 | 操作存储器元件的系统及方法 |
Families Citing this family (50)
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US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6928001B2 (en) * | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
US7098107B2 (en) * | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
US6700818B2 (en) * | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US7190620B2 (en) * | 2002-01-31 | 2007-03-13 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6799256B2 (en) * | 2002-04-12 | 2004-09-28 | Advanced Micro Devices, Inc. | System and method for multi-bit flash reads using dual dynamic references |
US6917544B2 (en) * | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
WO2004027392A1 (en) | 2002-09-20 | 2004-04-01 | Enventure Global Technology | Pipe formability evaluation for expandable tubulars |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US6967896B2 (en) * | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US7178004B2 (en) * | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7324374B2 (en) * | 2003-06-20 | 2008-01-29 | Spansion Llc | Memory with a core-based virtual ground and dynamic reference sensing scheme |
US7123532B2 (en) * | 2003-09-16 | 2006-10-17 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
WO2005094178A2 (en) * | 2004-04-01 | 2005-10-13 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
US7366025B2 (en) * | 2004-06-10 | 2008-04-29 | Saifun Semiconductors Ltd. | Reduced power programming of non-volatile cells |
US7095655B2 (en) * | 2004-08-12 | 2006-08-22 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
US20060068551A1 (en) * | 2004-09-27 | 2006-03-30 | Saifun Semiconductors, Ltd. | Method for embedding NROM |
US7638850B2 (en) * | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US7262999B2 (en) * | 2004-11-24 | 2007-08-28 | Macronix International Co., Ltd. | System and method for preventing read margin degradation for a memory array |
US20060146624A1 (en) * | 2004-12-02 | 2006-07-06 | Saifun Semiconductors, Ltd. | Current folding sense amplifier |
CN1838323A (zh) * | 2005-01-19 | 2006-09-27 | 赛芬半导体有限公司 | 可预防固定模式编程的方法 |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
WO2006103734A1 (ja) * | 2005-03-28 | 2006-10-05 | Fujitsu Limited | 不揮発性半導体メモリおよびその読み出し方法並びにマイクロプロセッサ |
US20070141788A1 (en) * | 2005-05-25 | 2007-06-21 | Ilan Bloom | Method for embedding non-volatile memory with logic circuitry |
US7190621B2 (en) * | 2005-06-03 | 2007-03-13 | Infineon Technologies Ag | Sensing scheme for a non-volatile semiconductor memory cell |
US7259993B2 (en) * | 2005-06-03 | 2007-08-21 | Infineon Technologies Ag | Reference scheme for a non-volatile semiconductor memory device |
US8400841B2 (en) * | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
US7184313B2 (en) * | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US7786512B2 (en) * | 2005-07-18 | 2010-08-31 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
JP2007035179A (ja) * | 2005-07-28 | 2007-02-08 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置 |
US20070036007A1 (en) * | 2005-08-09 | 2007-02-15 | Saifun Semiconductors, Ltd. | Sticky bit buffer |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US20070096199A1 (en) * | 2005-09-08 | 2007-05-03 | Eli Lusky | Method of manufacturing symmetric arrays |
US7289359B2 (en) * | 2005-09-09 | 2007-10-30 | Macronix International Co., Ltd. | Systems and methods for using a single reference cell in a dual bit flash memory |
US7224619B2 (en) * | 2005-09-09 | 2007-05-29 | Macronix International Co., Ltd. | Method and apparatus for protection from over-erasing nonvolatile memory cells |
US20070120180A1 (en) * | 2005-11-25 | 2007-05-31 | Boaz Eitan | Transition areas for dense memory arrays |
JP4672024B2 (ja) * | 2005-12-15 | 2011-04-20 | スパンション エルエルシー | 不揮発性記憶装置、および不揮発性記憶装置の制御方法 |
US7352627B2 (en) * | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US7808818B2 (en) * | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US20070173017A1 (en) * | 2006-01-20 | 2007-07-26 | Saifun Semiconductors, Ltd. | Advanced non-volatile memory array and method of fabrication thereof |
US7760554B2 (en) * | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US8253452B2 (en) * | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
KR100666223B1 (ko) * | 2006-02-22 | 2007-01-09 | 삼성전자주식회사 | 메모리셀 사이의 커플링 노이즈를 저감시키는 3-레벨불휘발성 반도체 메모리 장치 및 이에 대한 구동방법 |
US20070255889A1 (en) * | 2006-03-22 | 2007-11-01 | Yoav Yogev | Non-volatile memory device and method of operating the device |
US7701779B2 (en) * | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US7605579B2 (en) * | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |
US20080239599A1 (en) * | 2007-04-01 | 2008-10-02 | Yehuda Yizraeli | Clamping Voltage Events Such As ESD |
US7778098B2 (en) * | 2007-12-31 | 2010-08-17 | Cypress Semiconductor Corporation | Dummy cell for memory circuits |
US7940570B2 (en) * | 2009-06-29 | 2011-05-10 | Spansion Llc | Memory employing separate dynamic reference areas |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US5163021A (en) | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
JP3336813B2 (ja) | 1995-02-01 | 2002-10-21 | ソニー株式会社 | 不揮発性半導体メモリ装置 |
DE69702256T2 (de) | 1996-06-24 | 2001-01-18 | Advanced Micro Devices, Inc. | Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren |
KR100285065B1 (ko) * | 1998-06-12 | 2001-03-15 | 윤종용 | 불 휘발성 반도체 메모리 장치 |
US6538922B1 (en) | 2000-09-27 | 2003-03-25 | Sandisk Corporation | Writable tracking cells |
US6574139B2 (en) | 2001-06-20 | 2003-06-03 | Fujitsu Limited | Method and device for reading dual bit memory cells using multiple reference cells with two side read |
JP4017118B2 (ja) * | 2004-01-23 | 2007-12-05 | パイオニア株式会社 | 強誘電体を用いた記録媒体、記録装置および再生装置 |
-
2002
- 2002-04-08 US US10/119,391 patent/US6690602B1/en not_active Expired - Lifetime
-
2003
- 2003-02-14 JP JP2003585103A patent/JP2005522817A/ja active Pending
- 2003-02-14 CN CNB038077426A patent/CN100538897C/zh not_active Expired - Lifetime
- 2003-02-14 DE DE10392492.2T patent/DE10392492B4/de not_active Expired - Lifetime
- 2003-02-14 GB GB0420863A patent/GB2401971B/en not_active Expired - Fee Related
- 2003-02-14 WO PCT/US2003/004611 patent/WO2003088260A1/en active Application Filing
- 2003-02-14 AU AU2003219772A patent/AU2003219772A1/en not_active Abandoned
- 2003-02-14 KR KR1020047015998A patent/KR100935948B1/ko active IP Right Grant
- 2003-03-28 TW TW092107070A patent/TWI286754B/zh active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101540199B (zh) * | 2008-03-21 | 2012-07-11 | 旺宏电子股份有限公司 | 操作存储器元件的系统及方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20040097313A (ko) | 2004-11-17 |
DE10392492T5 (de) | 2005-05-12 |
JP2005522817A (ja) | 2005-07-28 |
TW200306577A (en) | 2003-11-16 |
US6690602B1 (en) | 2004-02-10 |
GB2401971A (en) | 2004-11-24 |
GB2401971B (en) | 2005-06-22 |
WO2003088260A1 (en) | 2003-10-23 |
AU2003219772A1 (en) | 2003-10-27 |
KR100935948B1 (ko) | 2010-01-12 |
GB0420863D0 (en) | 2004-10-20 |
DE10392492B4 (de) | 2018-03-01 |
CN100538897C (zh) | 2009-09-09 |
TWI286754B (en) | 2007-09-11 |
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Owner name: SPANSION CO.,LTD. Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20070413 Owner name: SPANSION CO., LTD. Free format text: FORMER OWNER: SPANSION CO.,LTD. Effective date: 20070413 |
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Effective date of registration: 20070413 Address after: California, USA Applicant after: Spanson Co. Address before: California, USA Applicant before: ADVANCED MICRO DEVICES, Inc. Effective date of registration: 20070413 Address after: California, USA Applicant after: SPANSION LLC Address before: California, USA Applicant before: Spanson Co. |
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Effective date of registration: 20160317 Address after: California, USA Patentee after: CYPRESS SEMICONDUCTOR Corp. Address before: California, USA Patentee before: SPANSION LLC |
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Granted publication date: 20090909 |