KR960039237A - 스택 반도체 칩을 구비한 3차원 다중 칩 모듈 및 그 제조 방법 - Google Patents

스택 반도체 칩을 구비한 3차원 다중 칩 모듈 및 그 제조 방법 Download PDF

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Publication number
KR960039237A
KR960039237A KR1019960010373A KR19960010373A KR960039237A KR 960039237 A KR960039237 A KR 960039237A KR 1019960010373 A KR1019960010373 A KR 1019960010373A KR 19960010373 A KR19960010373 A KR 19960010373A KR 960039237 A KR960039237 A KR 960039237A
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South Korea
Prior art keywords
conductive
semiconductor chips
insulating carrier
dimensional multi
chip module
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KR1019960010373A
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English (en)
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KR0180451B1 (ko
Inventor
나오지 센바
유조 시마다
Original Assignee
가네꼬 히사시
닛본덴기 가부시끼가이샤
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Publication of KR960039237A publication Critical patent/KR960039237A/ko
Application granted granted Critical
Publication of KR0180451B1 publication Critical patent/KR0180451B1/ko

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Abstract

다수의 반도체 칩들(21a 내지 21d)은 스택 반도체 칩 구조(21)를 형성하도록 서로 순차적으로 결합되고, 스택반도체 칩 구조는 절연 캐리어(22)에 형성된 공동에 수용되고; 반도체 칩들(21a 내지 21d)은 순차적으로 스택되고, 절연 캐리어의 하부 표면에 형성된 도전성 패턴(22c)은 결합 배선들(23)을 통해 반도체 칩들 각각의 전극들(21h/21i)에 접속되고, 3차원 다중 칩 모듈은 스택 반도체 칩 구조 보다 약간 더 높다.

Description

스택 반도체 칩을 구비한 3차원 다중 칩 모듈 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 3차원 다중 칩 모듈의 구조를 도시한 개략 단면도.

Claims (19)

  1. 주 표면, 외부 표면과, 상기 주 표면 및 상기 외부 표면에 노광된 도전성 수단(22b/22c; 25a/25f; 29f/29g)을 포함하는 절연 캐리어(22; 25; 29)를 포함하는 3차원 다중 칩 모듈에 있어서, 상기 절연 캐리어(22; 25; 29)에 의해 지지되고, 집적 회로와 상기 집적 회로에 전기적으로 접속되고 주변 영역에 형성된 도전성 패드들(21h/21i)을 각각 갖는 다수의 반도체 칩들(21a 내지 21d) 및 상기 다수의 반도체 칩들 중 한 칩의 중심 영역과 상기 다수의 반도체 칩들 중 다른 칩의 중심 영역 사이에 삽입된 적어도 하나의 절연 접착제 화합물층(21e/21f/21g)을 포함하는 스택 반도체 칩 구조(21; 26; 30); 및 상기 다수의 반도체 칩들의 상기 도전성 패드들과 상기 절연 캐리어의 상기 도전성 수단 사이에 접속된 도전성 배선들(23; 27; 31)을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  2. 제1항에 있어서, 상기 도전성 패드들, 상기 도전성 수단 및 상기 도전성 배선들을 커버하는 절연 수지 층을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  3. 제1항에 있어서, 상기 주 표면은 상기 스택 반도체 칩 구조가 수용된 공동(22a; 25b; 29c)을 정의하고, 상기 공동의 깊이는 상기 스택 반도체 칩 구조의 높이와 동일하거나 보다 큰 것을 특징으로 하는 3차원 다중 칩 모듈.
  4. 제3항에 있어서, 상기 스택 반도체 칩 구조, 상기 도전성 수단 및 상기 도전성 배선들을 밀봉 하도록 상기 공동을 채우는 절연 수지 층(24; 28; 32)을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  5. 제1항에 있어서, 상기 주 표면에 형성된 도전성 패턴(22c; 29f) 및 상기 외부 표면에 노광된 도전성 관통홀들(22b; 29g)은 상기 도전성 수단을 구성하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  6. 제1항에 있어서, 상기 주 표면에 형성된 도전성 패턴(25a) 및 볼 그리드 어레이(25f)는 상기 도전성 수단을 구성하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  7. 제1항에 있어서, 상기 스택 반도체 칩 구조에서 최하부 위치에 있는 상기 다수의 반도체 칩들 중 한 칩에 부착된 가열 싱크(33)를 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  8. 반도체 칩들을 수용하기 위한 절연 캐리어를 포함하는 3차원 다중 칩 모듈에 있어서, 상기 절연 캐리어는 제1내면, 구멍(41e; 47d)을 정의하는 제2내면, 외부 표면과, 상기 제1내면 및 상기 외부 표면에 노광된 도전성수단(41f/41g)을 각각 갖는 서로 적층된 다수의 절연 캐리어 부재들(41a 내지 41d; 47)을 포함하고, 상기 3차원 다중 칩 모듈은, 상기 구멍에 각각 수용되고, 제1표면 부(42e)에 형성된 도전성 패드들(42g), 상기 제1표면 부(42e) 및 제거된 제2표면 부(42f)에 형성된 집적 회로를 각각 갖는 다수의 반도체 칩들(42a 내지 42d; 48); 및 상기 다수의 반도체 칩들 각각의 상기 도전성 패드들과 상기 다수의 절연 캐리어 부재들 중 한 부재의 상기 도전성 수단 사이에 각각 접속된 다수의 도전성 배선들(43; 50)의 집합들을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  9. 제8항에 있어서, 상기 제1내면은 상기 구멍(41e)이 노광된 공동을 정의하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  10. 제9항에 있어서, 상기 도전성 패드들, 상기 도전성 패턴 및 상기 도전성 배선들의 집합을 밀봉할 뿐만 아니라 상기 다수의 반도체 칩들 중 하나를 상기 다수의 절연 캐리어 부재들 중 관련된 부재에 고정시키도록 상기 공동을 각각 채우는 수지 피스들(44a 내지 44d)을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  11. 제9항에 있어서, 상기 다수의 반도체 칩들에 각각 부착된 다수의 가열 싱크들(51)을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  12. 제8항에 있어서, 도전성 패턴(41f) 및 도전성 관통 홀들(41g)은 상기 도전성 수단을 구성하는 것을 특징으로 하는 3차원 다중 칩 모듈.
  13. 3차원 다중 칩 모듈을 제조하는 방법에 있어서, a) 주 표면, 외부 표면과, 상기 주 표면 및 상기 외부 표면에 노광된 도전성 수단(22b/22d/22e)을 포함하는 절연 캐리어(22)를 제공하는 단계; b) 중심 영역, 상기 중심영역 주위의 주변 영역과, 집적 회로에 전기적으로 접속되고 상기 주변 영역에 노광된 도전성 패드들(22h/21i)을 갖는 반도체 칩(21a)을 상기 절연 캐리어에 장착하는 단계; c) 도전성 배선들(23)을 통해 상기 도전성 수단(22d/22e)에 상기 도전성 패드들(21h/21i)을 접속시키는 단계; d) 접착제 화합물 층(21e)으로 상기 중심 영역을 코팅하는 단계; e) 중심 영역, 상기 중심 영역 주위의 주변 영역과, 상기 주변 영역에 노광된 도전성 패드들(21h/21i)을 갖는 다른 반도체 칩(21b)을 상기 접착제 화합물 층(21e)에 배치하는 단계; f) 상기 다른 반도체 칩의 상기 도전성 패드들(21h/21i)을 도전성 배선들(23)을 통해 상기 도전성 수단(22d/22e)에 접속시키는 단계; 및 g) 필요한 경우, 상기 단계들 d), e) 및 f)를 반복하는 단계를 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  14. 제13항에 있어서, 상기 주 표면은 상기 반도체 칩들(21a 내지 21d)이 수용된 공동(22a)을 정의하고, 상기 공동의 깊이는 상기 반도체 칩들 및 상기 접착제 화합물 층 또는 층들의 높이를 합한 높이와 동일하거나 보다 큰 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  15. 제14항에 있어서, 상기 단계 g) 후에 상기 반도체 칩들(21a 내지 21d), 상기 접착제 화합물 층 또는 층들(21e 내지 21g), 상기 도전성 수단(41f/41g), 상기 도전성 패드들(42g) 및 상기 도전성 배선들(43)을 수지로 밀봉하도록 상기 공동(22a)에 수지(24)를 제공하는 단계를 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  16. 3차원 다중 칩 모듈을 제조하는 방법에 있어서, a) 제1내면, 구멍(41e)을 정의하는 제2내면, 외부 표면과, 상기 제1내면 및 상기 외부 표면에 노광된 도전성 단수(41f/41g)을 각각 갖는 다수의 절연 캐리어 부재들(41a 내지 41d)을 제공하는 단계; b) 상기 공동에 수납된 제1표면 부(42e) 및 상기 구멍으로부터 돌출된 제2표면 부(42f) 상에 형성된 도전성 패드들(42g)을 각각 갖는 다수의 반도체 칩들 각각을 상기 다수의 절연 캐리어 부재들 중 한 부재의 상기 구멍에 수용하는 단계; c) 상기 다수의 반도체 칩들 각각의 상기 도전성 패드들을 도전성 배선들(43)을 통해 상기 다수의 절연 캐리어 부재들 중 한 부재의 상기 도전성 수단에 접속시키는 단계; d) 상기 다수의 절연 캐리어 부재들 중 상기 한 부재의 상기 구멍에 상기 다수의 반도체 칩들 각각을 완전히 수용시키도록 상기 다수의 반도체 칩들 각각의 상기 제2표면 부(42f)를 제거하는 단계; 및 e) 상기 다수의 절연 캐리어 부재들 중 한 부재의 상기 도전성 수단이 상기 다수의 절연 캐리어 부재들 중 다른 부재의 상기 도전성 수단에 전기적으로 접속되는 방식으로 상기 다수의 절연 캐리어 부재들(41a 내지 41d)을 스택하는 단계를 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  17. 제16항에 있어서, 상기 제1 내면은 상기 구멍(41e)이 노광된 공동(45)을 정의하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  18. 제17항에 있어서, 상기 단계 c) 및 상기 단계 d) 사이에 상기 도전성 패드들, 상기 도전성 수단 및 상기 도전성 배선들을 밀봉할 뿐만 아니라 상기 다수의 반도체 칩들 각각을 상기 다수의 절연 캐리어 부재들 중 관련된 부재에 고정시키도록 상기 공동을 수지(44a 내지 44d)로 채우는 단계를 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
  19. 제16항에 있어서, 상기 제2 내면은 상기 단계 b)에서 상기 다수의 반도체 칩들(62) 중 다른 칩이 수용된 적어도 하나의 구멍(60e 내지 60h)을 정의하고, 상기 다수의 반도체 칩들(62) 중 상기 다른 칩은 상기 단계들 c) 및 d)에서 상기 다수의 반도체 칩들 각각에 유사하게 처리되고, 상기 방법은, 서로 스택된 상기 다수의 절연캐리어 부재들을 다수의 3차원 다중 칩 모듈들로 분리시키는 단계들을 더 포함하는 것을 특징으로 하는 3차원 다중 칩 모듈 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960010373A 1995-04-07 1996-04-06 스택 반도체 칩을 구비한 3차원 다중 칩 모듈 및 그 제조방법 KR0180451B1 (ko)

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