KR960035995A - 반도체용 패키지 - Google Patents

반도체용 패키지 Download PDF

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KR960035995A
KR960035995A KR1019960009599A KR19960009599A KR960035995A KR 960035995 A KR960035995 A KR 960035995A KR 1019960009599 A KR1019960009599 A KR 1019960009599A KR 19960009599 A KR19960009599 A KR 19960009599A KR 960035995 A KR960035995 A KR 960035995A
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South Korea
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wiring layer
terminal
terminals
ground
signal
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KR1019960009599A
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KR100186816B1 (ko
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게이이찌 야노
준이찌 구도
고지 야마까와
기요시 이오기
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사또 후미오
가부시끼가이샤 도시바
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Publication of KR100186816B1 publication Critical patent/KR100186816B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PGA나 BGA 등의 반도체용 패키지에 있어서, 반도체 소자의 고집적화에 따른 입출력 신호 수의 증가 및 반도체 소자로부터의 발열량의 증대에 대응시킨 것으로, GHz를 초과한 고주파신호의 전송 특성을 향상시킴과 동시에, 그 오차를 저감한다.
반도체 소자의 탑재면(2a)와 단자 형성면(2b)를 가짐과 동시에, 반도체 소자에 전기적으로 접속되는 내부 배선층(5)가 설치된 질화 알루미늄 다층 기판 등의 세라믹스 다층 기판(2)를 구비한다. 세라믹스 다층 기판(2)의 단자 형성면(2b)에는 내부 배선층(5)와 전기적으로 접속된 입출력 단자군(3)이 배열되어 있다. 입출력 단자군(3)은 신호 단자(4a, 4c), 그라운드 단자(4b) 및 전원 단자(4d)를 갖는다. 이들중, 신호 단자(4a, 4c)는 적어도 1개의 그라운드 단자(4b) 또는 전원 단자(4d)와 인접하여 배열되어 있다.

Description

반도체용 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체용 패키지를 PGA용 패키지에 적용한 한 실시 형태를 도시하는 도면.

Claims (6)

  1. 반도체 소자의 탑재면과 단자 형성면을 갖고, 반도체 소자와 전기적으로 접속되는 내부 배선층을 갖는 세라믹스 다층 기판; 및 상기 내부 배선층과 전기적으로 접속됨과 동시에, 상기 세라믹스 다층 기판의 단자 형성면에 설치되고, 신호 단자, 그라운드 단자 및 전원 단자를 갖는 입출력 단자군을 구비하고, 상기 신호 단자 중 주된 신호 단자는 적어도 1개의 상기 그라운드 단자 또는 전원 단자와 인접하여 배열되어 있는 것을 특징으로 하는 반도체용 패키지.
  2. 제1항에 있어서, 상기 신호 단자는 그 50% 이상이 적어도 1개의 상기 그라운드 단자 또는 전원 단자와 인접하여 배열되어 있는 것을 특징으로 하는 반도체용 패키지.
  3. 제1항에 있어서, 상기 신호 단자는 그 전부가 적어도 1개의 상기 그라운드 단자 또는 전원 단자와 인접하여 배열되어 있는 것을 특징으로 하는 반도체용 패키지.
  4. 제1항에 있어서, 상기 내부 배선층은 신호 배선층, 그라운드 배선층 및 전원 배선층을 갖고, 상기 신호 배선층과 상기 그라운드 배선층 및 전원 배선층 중 적어도 한쪽이 상기 세라믹스 다층 기판의 적층 방향에 대해 번갈아 배치되어 있는 것을 특징으로 하는 반도체용 패키지.
  5. 제1항에 있어서, 상기 입출력 단자군은 핀 단자 또는 범프 단자를 갖는 것을 특징으로 하는 반도체용 패키지.
  6. 반도체 소자의 탑재면과 단자 형성면을 갖는 세라믹스 다층 기판; 상기 세라믹스 다층 기판 내부에 설치된 신호 배선층, 그라운드 배선층 및 전원 배선층을 갖고, 상기 그라운드 배선층 및 전원 배선층 중 적어도 한쪽이 상기 세라믹스 다층 기판 내에 평면 형태로 형성되어 있는 내부 배선층; 상기 그라운드 배선층과 전기적으로 접속되고, 상기 세라믹스 다층 기판의 단자 형성면에 설치된 그라운드 단자; 및 상기 신호 배선층과 전기적으로 접속되고, 상기 세라믹스 다층 기판의 단자 형성면에 설치된 신호 단자를 구비하고, 상기 신호 단자 중 주된 신호 단자는 적어도 1개의 상기 그라운드 단자 또는 전원 단자와 인접하여 배열되어 있는 것을 특징으로 하는 반도체용 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960009599A 1995-03-31 1996-03-30 반도체용 패키지 KR100186816B1 (ko)

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JP7482795 1995-03-31
JP95-074827 1995-03-31

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KR960035995A true KR960035995A (ko) 1996-10-28
KR100186816B1 KR100186816B1 (ko) 1999-03-20

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JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
JPH05160292A (ja) * 1991-06-06 1993-06-25 Toshiba Corp 多層パッケージ
JPH0727164A (ja) * 1993-07-15 1995-01-27 Toyota Motor Corp ショックアブソーバのバルブ構造
US5543661A (en) * 1994-05-31 1996-08-06 Sumitomo Metal Ceramics Inc. Semiconductor ceramic package with terminal vias

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KR100186816B1 (ko) 1999-03-20

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