KR960019653A - 반도체 소자의 소자분리막 형성방법 - Google Patents
반도체 소자의 소자분리막 형성방법 Download PDFInfo
- Publication number
- KR960019653A KR960019653A KR1019940030594A KR19940030594A KR960019653A KR 960019653 A KR960019653 A KR 960019653A KR 1019940030594 A KR1019940030594 A KR 1019940030594A KR 19940030594 A KR19940030594 A KR 19940030594A KR 960019653 A KR960019653 A KR 960019653A
- Authority
- KR
- South Korea
- Prior art keywords
- device isolation
- region
- film
- memory cell
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
- H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
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- Element Separation (AREA)
Abstract
Description
Claims (4)
- 반도체 소자의 소자분리막 형성방법에 있어서, 실리콘기판상에 패드 산화막 및 질화막을 순차적으로 형성시킨후 그 상부에 메모리셀지역의 소자분리영역 및 주변지역의 소자분리영역이 각각 노출되도록 감광막패턴을 형성시키는 단계와, 상기 단계로부터 상기 감광막패턴을 식각마스크로 이용하여 노출된 부분의 상기 질화막을 제거한후 상기 메모리셀지역의 소자분리영역의 노출된 실리콘기판을 소정깊이 식각하여 트렌치를 형성시키는 단계와, 상기 단계로부터 상기 감광막패턴을 제거하고 전체상부면에 채널스톱이온을 주입시키는 단계와, 상기 단계로부터 산화공정을 실시하여 메모리셀지역의 소자분리영역 및 주변지역의 소자분리영역에 소자분리막을 각각 형성시키는 단계와, 상기 단계로부터 잔류된 질화막 및 패드 산화막을 순차적으로 제거시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.
- 제1항에 있어서, 상기 트렌치의 깊이는 05 내지 1㎛정도인 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.
- 제1항에 있어서, 상기 메모리셀지역의 소자분리막은 실리콘기판의 표면까지 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.
- 반도체 소자의 소자분리막에 있어서, 메모리셀지역의 소자분리막은 실리콘기판의 트렌치내에 매몰되게 형성되며, 주변지역의 소자분리막은 실리콘기판 표면 상부로 돌출되도록 형성된 것을 특징으로 하는 반도체 소자의 소자분리막.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940030594A KR0148611B1 (ko) | 1994-11-21 | 1994-11-21 | 반도체 소자의 소자분리막 형성방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940030594A KR0148611B1 (ko) | 1994-11-21 | 1994-11-21 | 반도체 소자의 소자분리막 형성방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960019653A true KR960019653A (ko) | 1996-06-17 |
| KR0148611B1 KR0148611B1 (ko) | 1998-12-01 |
Family
ID=19398484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940030594A Expired - Fee Related KR0148611B1 (ko) | 1994-11-21 | 1994-11-21 | 반도체 소자의 소자분리막 형성방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0148611B1 (ko) |
-
1994
- 1994-11-21 KR KR1019940030594A patent/KR0148611B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR0148611B1 (ko) | 1998-12-01 |
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