KR960005936A - 반도체 소자의 필드산화막 형성방법 - Google Patents

반도체 소자의 필드산화막 형성방법 Download PDF

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Publication number
KR960005936A
KR960005936A KR1019940016110A KR19940016110A KR960005936A KR 960005936 A KR960005936 A KR 960005936A KR 1019940016110 A KR1019940016110 A KR 1019940016110A KR 19940016110 A KR19940016110 A KR 19940016110A KR 960005936 A KR960005936 A KR 960005936A
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KR
South Korea
Prior art keywords
oxide film
forming
field oxide
semiconductor device
silicon substrate
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KR1019940016110A
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English (en)
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KR100187676B1 (ko
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940016110A priority Critical patent/KR100187676B1/ko
Priority to GB9513227A priority patent/GB2291261B/en
Priority to GB9818286A priority patent/GB2326025B/en
Priority to DE19524202A priority patent/DE19524202C2/de
Priority to JP7167354A priority patent/JP2871535B2/ja
Priority to US08/498,912 priority patent/US5541136A/en
Priority to CN95106984A priority patent/CN1050932C/zh
Publication of KR960005936A publication Critical patent/KR960005936A/ko
Priority to GBGB9816594.7A priority patent/GB9816594D0/en
Application granted granted Critical
Publication of KR100187676B1 publication Critical patent/KR100187676B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 소자의 필드 산화막 형성방법을 개시한다.
본 발명은 필드 산화막 형성시 버즈 비크 발생을 제거하고 실리콘 기판의 일부를 돌출시키고 실리콘 기판의 돌출부위에 트렌치를 형성한 다음 필드 산화막을 형성시킨다.

Description

반도체 소자의 필드산화막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2f도는 본 발명에 따른 필드 산화막 형성방법을 설명하기 위한 반도체 소자의 단면도.

Claims (4)

  1. 반도체 소자의 필드 산화막 형성방법에 있어서, 실리콘 기판(1)상에 제1 열산화막(5)을 형성시킨 다음 그 상부에 감광막(6)을 설정된 패턴으로 형성하고 노출되는 제1 열산화막(5) 및 실리콘 기판(1)을 소정깊이로 제거하는 단계와, 상기 단계로부터 상기 감광막(6) 및 제1 열산화막(5)을 제거하고 제2 열산화막(7)을 소정의 폭으로노출시킨 다음 실리콘 기판(1)상에 채널 스토퍼(9)를 형성하는 단계와, 상기 단계로부터 상기 제1 질화막(8) 측벽에 질화막 스페이서(10)를 형성한 다음 상기 제2 열산화막(7) 및 실리콘 기판(1)을 원하는 깊이로 제거하여 트렌치(11)를 형성하는 단계와, 상기 단계로부터 열산화공정에 의해 필드 산화막(12)을 형성하는 단계와, 상기 단계로부터 상기 질화막 스페이서(10), 제1 질화막(8) 및 제2 열산화막(7)을 식각하여 완전한 필드 산화막(13)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.
  2. 제1항에 있어서, 상기 채널 스토퍼(9) 형성시 주입된 불순물 이온이 실리콘 기판의 돌출부위에 존재하도록 한 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.
  3. 제1항에 있어서, 상기 트렌치(11)를 형성할 때 실리콘 기판상(1)의 돌출부위 높이보다 트렌치의 깊이가 더 작게 형성되는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.
  4. 제1항에 있어서, 상기 질화막 스페이서(10), 제1 질화막(8) 및 제2 열산화막 (7)은 습식식각공정에 의해 제거되는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940016110A 1994-07-06 1994-07-06 반도체 소자의 필드산화막 형성방법 KR100187676B1 (ko)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1019940016110A KR100187676B1 (ko) 1994-07-06 1994-07-06 반도체 소자의 필드산화막 형성방법
GB9513227A GB2291261B (en) 1994-07-06 1995-06-29 Method of forming a field oxide film in a semiconductor device
GB9818286A GB2326025B (en) 1994-07-06 1995-06-29 Method of forming a field oxide film in a semicondutor device
DE19524202A DE19524202C2 (de) 1994-07-06 1995-07-03 Verfahren zur Bildung eines Feldoxydfilmes für eine Halbleitervorrichtung
JP7167354A JP2871535B2 (ja) 1994-07-06 1995-07-03 半導体素子のフィールド酸化膜形成方法
US08/498,912 US5541136A (en) 1994-07-06 1995-07-06 Method of forming a field oxide film in a semiconductor device
CN95106984A CN1050932C (zh) 1994-07-06 1995-07-06 半导体器件场氧化层的形成方法
GBGB9816594.7A GB9816594D0 (en) 1994-07-06 1998-07-31 Method of forming a field oxide film in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940016110A KR100187676B1 (ko) 1994-07-06 1994-07-06 반도체 소자의 필드산화막 형성방법

Publications (2)

Publication Number Publication Date
KR960005936A true KR960005936A (ko) 1996-02-23
KR100187676B1 KR100187676B1 (ko) 1999-06-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100432049B1 (ko) * 2001-12-28 2004-05-22 에스케이텔레텍주식회사 액정화면 클리너를 구비하는 이동통신단말기

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990004608A (ko) * 1997-06-28 1999-01-15 김영환 반도체소자의 소자분리절연막 형성방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100432049B1 (ko) * 2001-12-28 2004-05-22 에스케이텔레텍주식회사 액정화면 클리너를 구비하는 이동통신단말기

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