KR940016700A - 플라스틱-몰드형 중공 반도체장치 및 그 제조공정 - Google Patents
플라스틱-몰드형 중공 반도체장치 및 그 제조공정 Download PDFInfo
- Publication number
- KR940016700A KR940016700A KR1019930027853A KR930027853A KR940016700A KR 940016700 A KR940016700 A KR 940016700A KR 1019930027853 A KR1019930027853 A KR 1019930027853A KR 930027853 A KR930027853 A KR 930027853A KR 940016700 A KR940016700 A KR 940016700A
- Authority
- KR
- South Korea
- Prior art keywords
- cover
- base
- semiconductor device
- plastic
- cavity
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims 6
- 239000000463 material Substances 0.000 claims abstract 6
- 229920005989 resin Polymers 0.000 claims abstract 6
- 239000011347 resin Substances 0.000 claims abstract 6
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract 5
- 238000000034 method Methods 0.000 claims 2
- 239000004840 adhesive resin Substances 0.000 claims 1
- 229920006223 adhesive resin Polymers 0.000 claims 1
- 239000000945 filler Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
플라스틱-몰드형 중공 반도체장치가, 베이스와 커버의 본딩 표면뿐만 아니라 커버의 전체 가장자리 표면에 적용되는 열경화성 수지 접합재에 의하여 서로 결합되는 베이스와 커버를 포함한다.
열경화성 수지 접합재는 커버를 베이스상에 형성하고 동시에 그들을 예열한후 적용되고, 따라서 베이스와 커버사이에 있는 내부 가스는 팽창되지 않게되고 쓰루-홀의 생성이 제거되어 핸들링 특성과 신뢰성이 높은 반도체장치를 얻을 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예에 따른 플라스틱-몰드형 중공 반도체장치를 나타내는 측면도, 제 2 도는 제 1 도에서 나타나는 장치에서 사용된 커버의 측면도, 제 3 도는 제 1 도에서 나타나는 장치에서 사용된 베이스, 반도체소자등을 나타내는 측면도, 제 4 도는 커버가 위에 형성된 플라스틱-몰드형 중공 반도체장치의 베이스의 측면도, 제 5 도는 지그에 실장된 플라스틱-몰드형 중공 반도체장치의측면도.
Claims (6)
- 반도체소자가 수납되어 있고, 캐비티를 가지는 베이스와, 상기 캐비티로부터 밀폐 공간을 형성하도록 상기 베이스상에 배치된 커버와, 상기 베이스와 상기 커버의 본딩 표면뿐만 아니라 상기 커버의 가장자리 표면을 커버하여 그들을 밀폐하도록 형성된 열경화성 수지 접합재와를 포함하는 플라스틱-몰드형 반도체장치.
- 플라스틱-몰드형 반도체장치를 제조하는 공정이, 반도체소자가 수납되어 있고, 캐비티를 가지는 베이스상에 캐비티로부터 밀폐 공간이 형성되도록 커버를 형성하는 공정과, 상기 베이스와 상기 커버를 소정의 온도로 미리 가열하는 공정과, 상기 베이스와 상기 커버의 본딩 표면뿐만 아니라 상기 커버의 가장자리 표면을 커버하도록 상기 베이스와 상기 커버에 열경화성 수지 접합재를 적용하는 공정과, 상기 열경화성 수지 접합재를 큐링하는 공정과를 포함하는 플라스틱-몰드형 반도체장치의 제조공정.
- 제 2 항에 있어서, 상기 베이스상에 상기 커버를 재치할때, 상기 커버가 임시-부착 수지에 의하여 상기 베이스에 임시로 부착되는 플라스틱-몰드형 반도체장치의 제조공정.
- 제 3 항에 있어서, 필러 물질이 상기 임시 부착 수지에 첨가되는 플라스틱-몰드형 반도체장치의 제조공정.
- 제 2 항에 있어서, 상기 커버가 상기 베이스의 캐비티의 코너와 접하는 돌기를 가지는 플라스틱-몰드형 반도체장치의 제조공정.
- 제 2 항에 있어서, 상기 커버가 상기 베이스의 캐비티의 코너와 접하는 스텝부를 가지는 플라스틱-몰드형 반도체장치의 제조공정.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP92-339053 | 1992-12-18 | ||
JP33905392A JP3192507B2 (ja) | 1992-12-18 | 1992-12-18 | 樹脂シール中空型半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016700A true KR940016700A (ko) | 1994-07-23 |
KR0133970B1 KR0133970B1 (ko) | 1998-04-18 |
Family
ID=18323815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930027853A KR0133970B1 (ko) | 1992-12-18 | 1993-12-15 | 플라스틱-몰드형 중공 반도체 장치 및 그 제조공정 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5977628A (ko) |
EP (1) | EP0602662B1 (ko) |
JP (1) | JP3192507B2 (ko) |
KR (1) | KR0133970B1 (ko) |
DE (1) | DE69317373T2 (ko) |
SG (1) | SG48716A1 (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI261350B (en) * | 2005-09-02 | 2006-09-01 | Wintek Corp | Electronic member with conductive connection structure |
JP2009143234A (ja) * | 2008-12-24 | 2009-07-02 | Nippon Mining & Metals Co Ltd | キャリア付金属箔 |
CN103262235A (zh) * | 2010-12-16 | 2013-08-21 | 株式会社村田制作所 | 电子部件的制造方法 |
US8906747B2 (en) * | 2012-05-23 | 2014-12-09 | Freescale Semiconductor, Inc. | Cavity-type semiconductor package and method of packaging same |
JP5358724B1 (ja) | 2012-06-28 | 2013-12-04 | 太陽誘電株式会社 | 弾性波デバイス内蔵モジュール及び通信装置 |
JP6106404B2 (ja) | 2012-10-30 | 2017-03-29 | 太陽誘電株式会社 | 電子部品モジュール |
JP7200114B2 (ja) * | 2017-09-25 | 2023-01-06 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
WO2022270633A1 (ja) * | 2021-06-24 | 2022-12-29 | 京セラ株式会社 | 非接触通信媒体 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1081411A (en) * | 1975-12-24 | 1980-07-15 | Philipp W.H. Schuessler | Method for hermetically sealing an electronic circuit package |
JPS6221254A (ja) * | 1985-07-22 | 1987-01-29 | Akita Denshi Kk | 電子装置 |
JPS6237949A (ja) * | 1985-08-12 | 1987-02-18 | Matsushita Electronics Corp | 電子部品塔載用パツケ−ジ |
JPS6384051A (ja) * | 1986-09-26 | 1988-04-14 | Matsushita Electronics Corp | 半導体装置の製造方法 |
JPH02185058A (ja) * | 1989-01-12 | 1990-07-19 | Mitsubishi Electric Corp | 樹脂シール中空パツケージのシール方法 |
JP2503685B2 (ja) * | 1989-10-23 | 1996-06-05 | 日本電気株式会社 | ヒ―トシンク付半導体装置 |
JPH03145746A (ja) * | 1989-10-31 | 1991-06-20 | Toshiba Corp | 中空パッケージ |
US5064968A (en) * | 1990-01-16 | 1991-11-12 | Hughes Aircraft Company | Domed lid for integrated circuit package |
US5081327A (en) * | 1990-03-28 | 1992-01-14 | Cabot Corporation | Sealing system for hermetic microchip packages |
ATE186795T1 (de) * | 1990-07-21 | 1999-12-15 | Mitsui Chemicals Inc | Halbleiteranordnung mit einer packung |
EP0472866A3 (en) * | 1990-07-23 | 1994-09-07 | Nat Semiconductor Corp | Ferroelectric device packaging techniques |
-
1992
- 1992-12-18 JP JP33905392A patent/JP3192507B2/ja not_active Expired - Fee Related
-
1993
- 1993-12-15 KR KR1019930027853A patent/KR0133970B1/ko not_active IP Right Cessation
- 1993-12-17 US US08/168,185 patent/US5977628A/en not_active Expired - Lifetime
- 1993-12-17 DE DE69317373T patent/DE69317373T2/de not_active Expired - Lifetime
- 1993-12-17 SG SG1996000408A patent/SG48716A1/en unknown
- 1993-12-17 EP EP93120389A patent/EP0602662B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0602662A1 (en) | 1994-06-22 |
US5977628A (en) | 1999-11-02 |
EP0602662B1 (en) | 1998-03-11 |
KR0133970B1 (ko) | 1998-04-18 |
DE69317373D1 (de) | 1998-04-16 |
DE69317373T2 (de) | 1998-07-16 |
JP3192507B2 (ja) | 2001-07-30 |
SG48716A1 (en) | 1998-05-18 |
JPH06188326A (ja) | 1994-07-08 |
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